阅读说明：本技术 半导体封装件及用于安装半导体封装件的板 (Semiconductor package and board for mounting semiconductor package ) 是由 林裁贤 金哲奎 郑景文 金汉� 徐允锡 于 2019-03-12 设计创作，主要内容包括：本公开提供一种半导体封装件及用于安装半导体封装件的板,所述半导体封装件包括：半导体芯片,具有有效表面和无效表面,所述有效表面上设置有连接焊盘,并且所述无效表面与所述有效表面相对；包封剂,设置为覆盖所述半导体芯片的至少部分；以及连接构件,包括重新分布层。所述重新分布层包括：多个第一焊盘；多个第二焊盘,围绕所述多个第一焊盘；以及多个第三焊盘,围绕所述多个第二焊盘。所述多个第二焊盘中的每个和所述多个第三焊盘中的每个具有与所述多个第一焊盘中的每个的形状不同的形状。所述多个第二焊盘之间的间隙和所述多个第三焊盘之间的间隙彼此交错。(The present disclosure provides a semiconductor package and a board for mounting the semiconductor package, the semiconductor package including: a semiconductor chip having an active surface on which connection pads are provided and an inactive surface opposite to the active surface; an encapsulant disposed to cover at least a portion of the semiconductor chip; and a connection member including a redistribution layer. The redistribution layer includes: a plurality of first pads; a plurality of second pads surrounding the plurality of first pads; and a plurality of third pads surrounding the plurality of second pads. Each of the plurality of second pads and each of the plurality of third pads has a shape different from a shape of each of the plurality of first pads. Gaps between the plurality of second pads and gaps between the plurality of third pads are staggered with respect to each other.)

1. A semiconductor package, comprising:

a semiconductor chip having an active surface on which connection pads are provided and an inactive surface opposite to the active surface;

an encapsulant covering at least a portion of the semiconductor chip; and

a connection member disposed on the encapsulant and the active surface of the semiconductor chip, the connection member including a redistribution layer,

wherein the redistribution layer comprises: a plurality of first pads; a plurality of second pads disposed along an outer circumference of the connection member to surround the plurality of first pads; and a plurality of third pads disposed along an outer circumference of the connection member to surround the plurality of second pads; and is

Gaps between the plurality of second pads and gaps between the plurality of third pads are staggered with each other in an extending direction of an outer periphery of the connecting member.

2. The semiconductor package according to claim 1, wherein each of the plurality of second pads and each of the plurality of third pads has a shape different from a shape of each of the plurality of first pads.

3. The semiconductor package according to claim 1, wherein each of the plurality of second pads and each of the plurality of third pads has a predetermined length along an outer circumference of the connection member, and

the predetermined lengths are respectively greater than widths of the gaps of the plurality of second pads and the gaps of the plurality of third pads.

4. The semiconductor package of claim 3, wherein each of the plurality of first pads has a circular shape.

5. The semiconductor package of claim 1, wherein the plurality of third pads have at least one gap disposed at least one corner of the connection member, and

at least one of the plurality of second pads is disposed at a corner of the connection member where the at least one gap of the plurality of third pads is disposed.

6. The semiconductor package according to claim 1, wherein at least one of the plurality of first pads is electrically connected to a connection pad for a signal among the connection pads, and

each of the plurality of second pads and each of the plurality of third pads are electrically connected to a connection pad for ground among the connection pads.

7. The semiconductor package according to claim 1, wherein at least one of the plurality of first pads is electrically connected to a connection pad for a signal among the connection pads, and

one of the plurality of second pads and one of the plurality of third pads are each electrically connected to a ground connection pad of the connection pads.

8. The semiconductor package of claim 1, further comprising:

a plurality of electrically connecting metal bumps disposed on the connection member and electrically connected to the plurality of first pads, respectively;

a plurality of first shielding dams disposed on the connection member and electrically connected to the plurality of second pads, respectively; and

a plurality of second shielding dams disposed on the connection member and electrically connected to the plurality of third pads, respectively,

wherein gaps between the plurality of first shielding dams and gaps between the plurality of second shielding dams are staggered with each other in an extending direction of an outer periphery of the connecting member.

9. The semiconductor package according to claim 8, wherein each of the plurality of first shielding dams and each of the plurality of second shielding dams has a dam shape having a predetermined length along an outer circumference of the connection member, and

the predetermined lengths are respectively greater than widths of the gaps of the plurality of first shielding dams and widths of the gaps of the plurality of second shielding dams.

10. The semiconductor package according to claim 9, wherein each of the plurality of electrically connecting metal bumps has a spherical shape.

11. The semiconductor package of claim 8, wherein the plurality of second shielding dams have at least one gap disposed at least one corner of the connection member, and

at least one of the plurality of first shielding dams is disposed at a corner of the connection member where the at least one gap of the plurality of second shielding dams is disposed.

12. The semiconductor package according to claim 8, wherein at least one of the plurality of electrically connecting metal bumps is electrically connected to a connection pad for a signal among the connection pads, and

each of the plurality of first shield dams and each of the plurality of second shield dams are electrically connected to a connection pad for ground among the connection pads.

13. The semiconductor package according to claim 8, wherein at least one of the plurality of electrically connecting metal bumps is electrically connected to a connection pad for a signal among the connection pads, and

each of one of the plurality of first shield dams and one of the plurality of second shield dams is electrically connected to a ground connection pad of the connection pads.

14. The semiconductor package of claim 8, wherein each of the plurality of electrically connecting metal bumps and each of the plurality of first and second shielding dams comprises a low melting point metal comprising tin or an alloy containing tin.

15. The semiconductor package of claim 8, wherein each of the plurality of electrically connecting metal bumps, each of the plurality of first shielding dams, and each of the plurality of second shielding dams are disposed side-by-side at a same height.

16. The semiconductor package according to claim 8, wherein the gaps between the plurality of second shielding dams overlap with one or more of the plurality of first shielding dams, respectively, and the gaps between the plurality of first shielding dams overlap with one or more of the plurality of second shielding dams, in a direction perpendicular to an outer circumference of the connection member.

17. The semiconductor package according to claim 1, wherein the gap between the plurality of second pads overlaps one or more of the plurality of third pads, and the gap between the plurality of third pads overlaps one or more of the plurality of second pads in a direction perpendicular to an outer circumference of the connection member.

18. The semiconductor package of claim 1, wherein the connection member comprises a plurality of redistribution layers disposed at different heights relative to the active surface of the semiconductor chip, and

the redistribution layer including the plurality of first pads, the plurality of second pads, and the plurality of third pads is a redistribution layer of the plurality of redistribution layers that is furthest from the active surface.

19. The semiconductor package of claim 1, further comprising:

a frame having a first through hole provided with the semiconductor chip; and

a backside metal layer disposed on the inactive surface of the semiconductor chip and electrically connected to a metal layer disposed on a surface of the frame by backside metal vias that penetrate the encapsulant.

20. The semiconductor package of claim 19, wherein the backside metal layer is electrically connected to the second and third pads.

21. The semiconductor package of claim 19, wherein the frame further comprises a second via provided with a passive component, and

the encapsulant comprises: a first encapsulant encapsulating the passive component and filling at least a portion of the second via; and a second encapsulant encapsulating the semiconductor chip, filling at least a portion of the first via hole, and encapsulating the first encapsulant.

22. A board for mounting a package, comprising:

a printed circuit board including a plurality of first mounting pads, a plurality of second mounting pads surrounding the plurality of first mounting pads, and a plurality of third mounting pads surrounding the plurality of second mounting pads; and

a semiconductor package mounted on the printed circuit board,

wherein the semiconductor package includes:

a semiconductor chip having an active surface and an inactive surface, the active surface being provided with connection pads, and the inactive surface being opposite to the active surface;

an encapsulant covering at least a portion of the semiconductor chip;

a connection member disposed on the active surface of the semiconductor chip, the connection member including a redistribution layer;

a plurality of electrically connecting metal bumps disposed on the connection member and connected to the plurality of first mounting pads;

a first shield member disposed on the connection member to surround the plurality of electrically connecting metal bumps along an outer circumference of the connection member and connected to the plurality of second mounting pads; and

a second shield member disposed on the connection member to surround the first shield member along an outer circumference of the connection member and connected to the plurality of third mounting pads; and is

Each of the first shield members and each of the second shield members have a plurality of shield dams having a predetermined length along an outer circumference of the connection member.

23. The panel according to claim 22, wherein the plurality of shielding dams of the first shielding member and the plurality of shielding dams of the second shielding member are interleaved with each other in an extending direction of the outer periphery of the connecting member.

24. A semiconductor package, comprising:

a semiconductor chip having an active surface and an inactive surface, the active surface being provided with connection pads, and the inactive surface being opposite to the active surface;

an encapsulant covering at least a portion of the semiconductor chip; and

a connection member disposed on the encapsulant and the active surface of the semiconductor chip, the connection member including a redistribution layer,

wherein the redistribution layer comprises: a plurality of first pads; a plurality of second pads spaced apart from each other by a first gap and surrounding the plurality of first pads; and a plurality of third pads spaced apart from each other by a second gap and surrounding the plurality of second pads; and is

One of the plurality of second pads is disposed between the plurality of first pads and one of the second gaps.

25. The semiconductor package of claim 24, wherein one of the first gaps is disposed between one of the plurality of first pads and the plurality of third pads.

26. The semiconductor package according to claim 24, wherein another one of the second gaps is provided at least one corner of the connection member, and

at least one of the plurality of second pads is disposed at the corner of the connection member at which the other of the second gaps is disposed.

27. The semiconductor package according to claim 24, wherein each of the plurality of second pads and each of the plurality of third pads has a shape different from a shape of each of the plurality of first pads.

28. The semiconductor package according to claim 24, wherein each of the plurality of second pads and each of the plurality of third pads has a predetermined length along an outer circumference of the connection member, and

the predetermined lengths are respectively greater than a width of the first gap of the plurality of second pads and a width of the second gap of the third pad.

29. The semiconductor package of claim 24, further comprising:

a plurality of electrically connecting metal bumps disposed on the connection member and electrically connected to the plurality of first pads, respectively;

a plurality of first shielding dams disposed on the connection member, spaced apart from each other by third gaps, and electrically connected to the plurality of second pads, respectively, an

A plurality of second shielding dams disposed on the connection member, spaced apart from each other by fourth gaps, and electrically connected to the plurality of third pads, respectively;

wherein one of the plurality of first shielding dams is disposed between the plurality of electrically connecting metal bumps and one of the fourth gaps.

30. The semiconductor package of claim 29, wherein one of the third gaps is disposed between the plurality of electrically connecting metal bumps and one of the plurality of second shielding dams.

Technical Field

The present disclosure relates to a semiconductor package and a board for mounting the semiconductor package.

Background

Due to significant advances in the field of Information Technology (IT) such as mobile communication, semiconductors, networks, and the like, market demand for products in which various functions are integrated in a single terminal is rapidly increasing in the field of wireless communication, data communication, games, and the like. Accordingly, surface mounting techniques for mounting a package on a board using solder balls or pads have been widely developed.

Electromagnetic interference (EMI) occurring in the package may be shielded to some extent depending on the internal package design. However, when the package is mounted on a Printed Circuit Board (PCB) through solder balls, pads, etc., there are spaces between the PCB and the package on which the solder balls, pads, etc., are disposed, and there is a limitation in shielding EMI radiated through the spaces.

Disclosure of Invention

An aspect of the present disclosure is to provide a semiconductor package having a structure that effectively shields electromagnetic waves radiated through a space between a board and the semiconductor package when the semiconductor package is mounted on the board.

In detail, an aspect of the present disclosure is to design a pad of a redistribution layer in the following manner: a plurality of shielding members each including at least one or more shielding dams having a predetermined length are introduced to an outer edge of a mounting surface where an electrical connection metal bump of the package is disposed.

According to an aspect of the present disclosure, a semiconductor package includes: a semiconductor chip having an active surface on which connection pads are provided and an inactive surface opposite to the active surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection member disposed on the encapsulant and the active surface of the semiconductor chip, the connection member including a redistribution layer. The redistribution layer includes: a plurality of first pads; a plurality of second pads disposed along an outer circumference of the connection member to surround the plurality of first pads; and a plurality of third pads disposed along an outer circumference of the connection member to surround the plurality of second pads. Each of the plurality of second pads and each of the plurality of third pads has a shape different from a shape of each of the plurality of first pads. Gaps between the plurality of second pads and gaps between the plurality of third pads are staggered with each other in an extending direction of an outer periphery of the connecting member.

According to an aspect of the present disclosure, a board for mounting a package includes: a printed circuit board including a plurality of first mounting pads, a plurality of second mounting pads surrounding the plurality of first mounting pads, and a plurality of third mounting pads surrounding the plurality of second mounting pads; and a semiconductor package mounted on the printed circuit board. The semiconductor package includes: a semiconductor chip having an active surface and an inactive surface, the active surface being provided with connection pads, and the inactive surface being opposite to the active surface; an encapsulant covering at least a portion of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip, the connection member including a redistribution layer; a plurality of electrically connecting metal bumps disposed on the connection member and connected to the plurality of first mounting pads; a first shield member disposed on the connection member to surround the plurality of electrically connecting metal bumps along an outer circumference of the connection member and connected to the plurality of second mounting pads; and a second shield member disposed on the connection member to surround the first shield member along an outer circumference of the connection member and connected to the plurality of third mounting pads. Each of the first shield members and each of the second shield members have a plurality of shield dams having a predetermined length along an outer circumference of the connection member.

According to an aspect of the present disclosure, a semiconductor package includes: a semiconductor chip having an active surface and an inactive surface, the active surface being provided with connection pads, and the inactive surface being opposite to the active surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection member disposed on the encapsulant and the active surface of the semiconductor chip, the connection member including a redistribution layer. The redistribution layer includes: a plurality of first pads; a plurality of second pads spaced apart from each other by a first gap and surrounding the plurality of first pads; and a plurality of third pads spaced apart from each other by a second gap and surrounding the plurality of second pads. One of the plurality of second pads is disposed between the plurality of first pads and one of the second gaps.

Drawings

The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic block diagram illustrating an example of an electronic device system;

fig. 2 is a schematic perspective view showing an example of an electronic device;

fig. 3A and 3B are schematic sectional views showing states of a fan-in type semiconductor package before and after being packaged;

fig. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package;

fig. 5 is a schematic sectional view showing a case where a fan-in type semiconductor package is mounted on a Ball Grid Array (BGA) substrate and is finally mounted on a main board of an electronic device;

fig. 6 is a schematic sectional view showing a case where a fan-in type semiconductor package is embedded in a BGA substrate and finally mounted on a main board of an electronic device;

fig. 7 is a schematic sectional view showing a fan-out type semiconductor package;

fig. 8 is a schematic sectional view showing a case where a fan-out type semiconductor package is mounted on a main board of an electronic device;

fig. 9 is a schematic cross-sectional view showing an example of a semiconductor package;

fig. 10 is a schematic plan view illustrating a design of pads of a lowermost redistribution layer when the semiconductor package in fig. 9 is viewed along a direction "a";

fig. 11 is a schematic plan view showing a design of electrically connecting a metal bump and a shielding member when the semiconductor package in fig. 9 is viewed along a direction "a";

fig. 12 is a schematic sectional view taken along line I-I' in fig. 9.

FIG. 13 is a schematic cross-sectional view taken along line II-II' in FIG. 9;

fig. 14 is a schematic cross-sectional view showing an example of a panel for manufacturing the semiconductor package in fig. 9;

fig. 15A to 15E are process diagrams showing a schematic example of manufacturing the semiconductor package in fig. 9;

fig. 16A and 16B are schematic plan views showing various examples when the semiconductor package in fig. 9 is viewed along the direction "a";

fig. 17 schematically shows another example of a semiconductor package;

fig. 18 schematically shows another example of a semiconductor package;

fig. 19 schematically illustrates another example of a semiconductor package;

fig. 20 is a schematic sectional view showing an electromagnetic shielding effect in a case where the semiconductor package in fig. 9 is mounted on a printed circuit board; and

fig. 21 is a schematic plan view showing that the mounting area is significantly reduced in the case where the semiconductor package in fig. 9 is applied to an electronic device.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

Electronic device

Fig. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to fig. 1, the electronic device 1000 may receive a main board 1010 therein. Motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. that are physically or electrically connected to motherboard 1010. These components may be connected to other components described below by various signal lines 1090.

The chip related component 1020 may include: a memory chip such as a volatile memory (e.g., a Dynamic Random Access Memory (DRAM)), a nonvolatile memory (e.g., a Read Only Memory (ROM)), a flash memory, or the like; an application processor chip such as a central processing unit (e.g., Central Processing Unit (CPU)), a graphics processor (e.g., Graphics Processing Unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and logic chips such as analog-to-digital converters (ADCs), Application Specific Integrated Circuits (ASICs), and the like. However, the chip-related component 1020 is not limited thereto, but may also include other types of chip-related components. Further, the chip related components 1020 may be combined with each other.

Network-related components 1030 may include components that operate according to protocols such as: wireless fidelity (Wi-Fi) (institute of electrical and electronics engineers (IEEE)802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), evolution data optimized (Ev-DO), high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), Enhanced Data GSM Environment (EDGE), global system for mobile communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless and wired protocols specified after the above protocols. However, network-related components 1030 are not so limited, but may also include components that support various other wireless standards or protocols or wired standards or protocols. Further, the network-related component 1030 may be combined with each other together with the above-described chip-related component 1020.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), and so forth. However, the other components 1040 are not limited thereto, but may also include passive components and the like for various other purposes. Further, the other components 1040 may be combined with each other together with the above-described chip-related component 1020 or network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the motherboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a Compact Disc (CD) drive (not shown), a Digital Versatile Disc (DVD) drive (not shown), and so forth. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000 and the like.

The electronic device 1000 may be a smart phone, a Personal Digital Assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game, a smart watch, an automotive component, and so forth. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

Fig. 2 is a schematic perspective view showing an example of the electronic device.

Referring to fig. 2, the semiconductor package may be used for various purposes in various electronic devices 1000 as described above. For example, motherboard 1110 may be housed in main body 1101 of smartphone 1100, and various electronic components 1120 may be physically or electrically connected to motherboard 1110. In addition, other components (such as camera module 1130) that may or may not be physically or electrically connected to motherboard 1110 may be housed in main body 1101. Some of the electronic components 1120 may be chip-related components such as, but not limited to, semiconductor packages 1121. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

Semiconductor package

Typically, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product, and may be damaged by external physical or chemical impact. Therefore, the semiconductor chip itself may not be used, and the semiconductor chip may be packaged and used in an electronic device or the like in a packaged state.

Here, in terms of electrical connection, a semiconductor package is required because of a difference in circuit width between the semiconductor chip and the main board of the electronic device. In detail, the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip are very fine, and the size of the component mounting pads of the main board and the pitch between the component mounting pads of the main board used in the electronic device are significantly larger than the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technique for alleviating the difference in circuit width between the semiconductor chip and the main board is required.

Semiconductor packages manufactured by the packaging technology may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and purposes.

Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.

Fan-in type semiconductor package

Fig. 3A and 3B are schematic sectional views showing states of the fan-in type semiconductor package before and after being packaged.

Fig. 4 is a schematic sectional view illustrating a packaging process of a fan-in type semiconductor package.

Referring to fig. 3A to 4, the semiconductor chip 2220 may be, for example, an Integrated Circuit (IC) in a bare state, and include: a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; a connection pad 2222 formed on one surface of the body 2221 and including a conductive material such as aluminum (Al); and a passivation layer 2223, such as an oxide layer, a nitride layer, or the like, formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222. In this case, since the connection pads 2222 may be very small, it may be difficult to mount an Integrated Circuit (IC) on a medium-sized grade Printed Circuit Board (PCB) and a main board of an electronic device or the like.

Accordingly, the connection members 2240 may be formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220 to redistribute the connection pads 2222. The connection member 2240 may be formed by: an insulating layer 2241 is formed on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin, via holes 2243h that open the connection pads 2222 are formed, and then wiring patterns 2242 and vias 2243 are formed. Then, a passivation layer 2250 protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 may be formed, etc. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in type semiconductor package may have a package form in which all connection pads (e.g., input/output (I/O) terminals) of the semiconductor chip are disposed inside the semiconductor chip, may have excellent electrical characteristics, and may be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in a fan-in type semiconductor package form. In detail, many elements installed in a smart phone have been developed to achieve fast signal transmission while having a compact size.

However, in the fan-in type semiconductor package, since all the I/O terminals need to be disposed inside the semiconductor chip, the fan-in type semiconductor package has a large spatial limitation. Therefore, it is difficult to apply such a structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the above disadvantages, it may not be possible to directly mount and use the fan-in type semiconductor package on the main board of the electronic device. The reason is that: even if the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip are increased by the redistribution process, the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip are still insufficient to directly mount the fan-in type semiconductor package on the main board of the electronic device.

Fig. 5 is a schematic sectional view showing a case where a fan-in type semiconductor package is mounted on a Ball Grid Array (BGA) substrate and is finally mounted on a main board of an electronic device.

Fig. 6 is a schematic sectional view showing a case where a fan-in type semiconductor package is embedded in a BGA substrate and finally mounted on a main board of an electronic device.

Referring to fig. 5, in the fan-in type semiconductor package 2200, connection pads 2222 (i.e., I/O terminals) of the semiconductor chip 2220 may be redistributed through the BGA substrate 2301, and the fan-in type semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device in a state where it is mounted on the BGA substrate 2301. In this case, the solder balls 2270 and the like may be fixed by the underfill resin 2280 and the like, and the outside of the semiconductor chip 2220 may be covered with the molding material 2290 and the like. Alternatively, referring to fig. 6, the fan-in type semiconductor package 2200 may be embedded in a separate BGA substrate 2302, connection pads 2222 (i.e., I/O terminals) of the semiconductor chip 2220 may be redistributed through the BGA substrate 2302 in a state where the fan-in type semiconductor package 2200 is embedded in the BGA substrate 2302, and the fan-in type semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device.

As described above, it may be difficult to directly mount and use the fan-in type semiconductor package on the main board of the electronic device. Accordingly, the fan-in type semiconductor package may be mounted on a separate BGA substrate and then mounted on a main board of an electronic device through a packaging process, or may be mounted and used on the main board of the electronic device in a state in which the fan-in type semiconductor package is embedded in the BGA substrate.

Fan-out type semiconductor package

Fig. 7 is a schematic sectional view showing a fan-out type semiconductor package.

Referring to fig. 7, in the fan-out type semiconductor package 2100, for example, the outside of the semiconductor chip 2120 may be protected by an encapsulant 2130, and connection pads 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 by connection members 2140. In this case, the passivation layer 2150 may also be formed on the connection member 2140, and the under bump metal layer 2160 may also be formed in the opening of the passivation layer 2150. Solder balls 2170 may also be formed on the underbump metallization layer 2160. The semiconductor chip 2120 may be an Integrated Circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connecting member 2140 may include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and a via 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which the I/O terminals of the semiconductor chip are redistributed by the connection members formed on the semiconductor chip and are disposed outside the semiconductor chip. As described above, in the fan-in type semiconductor package, all the I/O terminals of the semiconductor chip need to be provided inside the semiconductor chip. Therefore, as the size of the semiconductor chip is reduced, the size and pitch of the balls need to be reduced, so that a standardized ball layout may not be used in the fan-in type semiconductor package. On the other hand, as described above, the fan-out type semiconductor package has a form in which the I/O terminals of the semiconductor chip are redistributed by the connection members formed on the semiconductor chip and are disposed outside the semiconductor chip. Therefore, even in the case where the size of the semiconductor chip is reduced, the standardized ball layout can be used as it is in the fan-out type semiconductor package, so that the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate BGA substrate, as described below.

Fig. 8 is a schematic sectional view showing a case where the fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to fig. 8, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device by solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection member 2140, the connection member 2140 is formed on the semiconductor chip 2120 and enables the connection pads 2122 to be redistributed to the fan-out region outside the size of the semiconductor chip 2120 so that the standardized ball layout can be used as it is in the fan-out type semiconductor package 2100. As a result, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate BGA substrate or the like.

As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate BGA substrate, the fan-out type semiconductor package can be implemented in a thickness smaller than that of the fan-in type semiconductor package using the BGA substrate. Therefore, the fan-out type semiconductor package can be miniaturized and slimmed. In addition, the fan-out type semiconductor package has excellent thermal and electrical characteristics, making it particularly suitable for mobile products. Accordingly, the fan-out type semiconductor package can be realized in a more compact form than a general Package On Package (POP) type form using a Printed Circuit Board (PCB), and a problem due to the occurrence of a warpage phenomenon can be solved.

On the other hand, the fan-out type semiconductor package refers to a packaging technique for mounting a semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from external impact as described above, and is a concept different from that of a Printed Circuit Board (PCB) or the like such as a BGA substrate (having a specification, a use, or the like different from that of the fan-out type semiconductor package and having a fan-in type semiconductor package embedded therein).

Fig. 9 is a schematic cross-sectional view illustrating an example of a semiconductor package.

Fig. 10 is a schematic plan view illustrating a design of pads of a lowermost redistribution layer when the semiconductor package in fig. 9 is viewed along a direction "a".

Fig. 11 is a schematic plan view illustrating a design of electrically connecting a metal bump and a shielding member when the semiconductor package in fig. 9 is viewed along a direction "a".

Fig. 12 is a schematic sectional view taken along line I-I' in fig. 9.

Fig. 13 is a schematic sectional view taken along line II-II' in fig. 9.

Referring to fig. 9 to 13, the semiconductor package 100A includes: a semiconductor chip 120 having an active surface on which a plurality of connection pads 122 are provided and an inactive surface opposite to the active surface; an encapsulant 130 covering at least a portion of the semiconductor chip 120; a connection member 140 disposed on the active surfaces of the encapsulant 130 and the semiconductor chip 120 and including one or more redistribution layers 142a, 142b, and 142c electrically connected to the plurality of connection pads 122; a plurality of electrical connection metal bumps 170 disposed on the connection member 140 and electrically connected to the plurality of connection pads 122 through the redistribution layers 142a, 142b, and 142 c; a first shield member 175A disposed on the connection member 140 to surround the plurality of electrical connection metal bumps 170 along the outer circumference of the connection member 140; and a second shielding member 175B disposed to surround the first shielding member 175A along the outer circumference of the connection member 140. The first shield member 175A may include at least one or more shield dams 175A, and the second shield member 175B may include at least one or more shield dams 175B having predetermined lengths L1 and L2 along the outer circumference of the connection member 140, respectively. Each of the plurality of electrical connection metal bumps 170 may have a spherical shape, and each of the plurality of first shield dams 175a and each of the plurality of second shield dams 175b may have a dam shape.

As described above, electromagnetic interference (EMI) occurring in the package can be shielded to some extent according to the internal package design. However, when the package is mounted on a Printed Circuit Board (PCB) through solder balls, pads, etc., there is a space between the PCB and the package provided with the solder balls, pads, etc., and there is a limitation in shielding EMI radiated through the space. Typically, the outer edge of the underside of the package is the weakest part of the reliability. Therefore, when the electrically connecting metal bumps are simply provided, board-level reliability may be deteriorated.

On the other hand, in the semiconductor package 100A, the pads 142P1, 142P2, and 142P3 of the lowermost redistribution layer 142C of the connection member 140 are designed as follows: a plurality of shield members 175A and 175B surrounding the electrical connection metal bumps 170 are introduced to the outside of the lower portion of the package where the electrical connection metal bumps 170 for mounting on the printed circuit board are provided. In detail, the lowermost redistribution layer 142C of the connection member 140 includes: a plurality of first pads 142P 1; a plurality of second pads 142P2 disposed to surround the plurality of first pads 142P1 along the outer circumference of the connection member 140; and a plurality of third pads 142P3 disposed to surround the plurality of second pads 142P2 along the outer circumference of the connection member 140. Each of the second and third pads 142P2 and 142P3 is provided to have a shape different from that of each of the first pads 142P 1. For example, each of the second pads 142P2 and each of the third pads 142P3 may have predetermined lengths l1 and l2 along the outer circumference of the connection member 140, and each of the first pads 142P1 may have a circular shape. Accordingly, a plurality of shield members 175A and 175B surrounding the electrical connection metal bumps 170 at the lower portion of the package are introduced to be connected to the plurality of second pads 142P2 and the plurality of third pads 142P 3. Even when the semiconductor package 100A is mounted on the printed circuit board 200 (shown in fig. 20), the space between the semiconductor package 100A and the printed circuit board 200 is blocked at the edges by the plurality of shielding members 175A and 175B to significantly reduce the radiated electromagnetic waves E. In addition, a plurality of shield members 175A and 175B respectively including shield dams 175A and 175B (respectively having predetermined lengths L1 and L2) are provided at such a weak-reliability portion to have an effect of providing a larger area of a similar material, as compared with a case where the electrically connecting metal bump 170 is simply provided. Therefore, reliability (more in detail, board-level reliability) can also be improved.

The first shielding member 175A may discontinuously surround the plurality of electrical connection metal bumps 170 along the outer circumference of the connection member 140, and the second shielding member 175B may discontinuously surround the first shielding member 175A along the outer circumference of the connection member 140. For example, the first shield member 175A may have a plurality of shield dams 175A and a plurality of gaps 175ah formed between the plurality of shield dams 175A, and the second shield member 175B may have a plurality of shield dams 175B and a plurality of gaps 175bh formed between the plurality of shield dams 175B. Due to the presence of the gaps 175ah and 175bh (e.g., spaced dots), the shield dams 175a and 175b are prevented from being disconnected due to stress. In addition, various gases generated during the process may be exhausted to further improve reliability. In this case, the gap 175ah of the first shield member 175A and the gap 175bh (e.g., spaced points) of the second shield member 175B may be disposed not to intersect. Gaps 175bh between the shielding dams 175b may overlap with one or more shielding dams 175a, and gaps 175ah between the shielding dams 175a may overlap with one or more shielding dams 175b in a direction perpendicular to the outer circumference of the connection member 140. Gaps 175bh between the shield dams 175B and gaps 175ah between the shield dams 175A may be staggered from each other in the extending direction of the first shield member 175A and the second shield member 175B along the outer circumference of the connection member 140. The shielding dams 175B and 175A may be staggered from each other in the extending direction of the first and second shielding members 175A and 175B along the outer circumference of the connection member 140, that is, gaps 175bh between the shielding dams 175B and gaps 175ah between the shielding dams 175A are staggered from each other in the extending direction of the outer circumference of the connection member 140. Therefore, the electromagnetic wave E can be effectively shielded while passing through the curved path, as shown in fig. 11. The electromagnetic wave E can be shielded despite the gaps 175ah and 175 bh. For this reason, gaps 142P2h between the plurality of second pads 142P2 connected to the first shield dam 175A of the first shield member 175A and gaps 142P3h between the plurality of third pads 142P3 connected to the second shield dam 175B of the second shield member 175B may also be disposed so as not to intersect. That is, one of the second pads 142P2 may be disposed between the first pad 142P1 and one of the gaps 142P3 h. One of the first shield dams 175a may be disposed between the plurality of electrical connection metal bumps 170 and one of the gaps 175 bh. In a direction perpendicular to the outer circumference of the connection member 140, the gaps 142P3h between the plurality of third pads 142P3 may overlap one or more of the plurality of second pads 142P2, and the gaps 142P2h between the plurality of second pads 142P2 may overlap one or more of the plurality of third pads 142P 3. Gaps 142P3h between the plurality of third pads 142P3 and gaps 142P2h between the plurality of second pads 142P2 may be staggered from each other in an extending direction of the plurality of second pads 142P2 and the plurality of third pads 142P3 along an outer circumference of the connection member 140. The plurality of second pads 142P2 and the plurality of third pads 142P3 may be staggered from each other in an extending direction of the plurality of second pads 142P2 and the plurality of third pads 142P3 along the outer circumference of the connection member 140. The gaps 142P2h between the plurality of second pads 142P2 and the gaps 142P3h between the plurality of third pads 142P3 refer to portions of the material (such as solder balls, etc.) of the shield dams 175a and 175b that are not connected to each other during the reflow process. For example, the following are excluded from the meaning of the gap: the second and third pads 142P2 and 142P3 are partially spaced apart from each other by a predetermined distance in such a manner that materials (such as solder balls, etc.) of the shield dams 175a and 175b disposed on the respective pads 142P2 and 142P3 are connected.

The second shield member 175B may have a gap 175bh formed in at least one corner of the electrical connection metal bump 170 (e.g., a gap 175bh located at a corner of an outer edge of the lower side of the package). In addition, the first shield member 175A may cover a corner of the electrical connection metal bump 170 (e.g., a corner of an outer edge of the lower side of the semiconductor package 100A) where the gap 175bh of the second shield member 175B is formed in a circular form without having the gap 175ah at the corner of the lower outer edge of the semiconductor package 100A. At the lower outer edge of the semiconductor package 100A, the corner region is a portion of weak reliability. When the shield dam 175B of the second shield member 175B or the like is disposed in the corner region, cracks C may easily occur due to stress concentration. Therefore, in detail, the shielding dam 175B of the second shielding member 175B is not disposed in the corner region. However, when the shielding dam 175A of the first shielding member 175A is not disposed in the corner region, the electromagnetic wave is easily radiated to the corner region. In detail, the corner region is covered at least by the shielding dam 175A of the first shielding member 175A. In more detail, as shown in fig. 11, the four corner regions may all have such an arrangement, but the configuration thereof is not limited thereto. To this end, the plurality of third pads 142P3 may have at least one gap 142P3h formed in at least one corner of the connection member 140, and at least one of the plurality of second pads 142P2 may be disposed at the corner of the connection member 140 (the gap 142P3h in which the plurality of third pads 142P3 are formed) to cover the corner in a rounded form. In more detail, as shown in fig. 10, the four corner regions may all have such an arrangement, but the configuration thereof is not limited thereto.

The shield dam 175A of the first shield member 175A may have a predetermined length L1 greater than a width W1 (e.g., a distance between the first shield members 175A) of the gap 175ah of the first shield member 175A, and the shield dam 175B of the second shield member 175B may have a predetermined length L2 greater than a width W2 (e.g., a distance between the second shield members 175B) of the gap 175bh of the second shield member 175B. When the shielding dam 175a has a length of L1 and the shielding dam 175b has a length of L2, an electromagnetic shielding effect and a reliability improvement effect can be achieved. In this case, the number of the shielding dams 175a and 175b and the number of the gaps 175ah and 175bh are not limited. To this end, the length l1 of the plurality of second pads 142P2 may be greater than the width w1 of the gap 142P2h, and the length l2 of the plurality of third pads 142P3 may be greater than the width w2 of the gap 142P3 h.

At least one or more shield dams 175A of the first shield member 175A and at least one or more shield dams 175B of the second shield member 175B may be electrically connected to the at least two connection pads 122, respectively. For example, the shield dams 175a and 175b may be electrically connected to at least two connection pads 122, respectively, in a one-to-many manner. In this case, the shield dam 175A of the first shield member 175A and the shield dam 175B of the second shield member 175B may be electrically connected to the Ground (GND) pattern of the redistribution layers 142a and 142B of the connection member 140. Accordingly, at least two connection pads 122 electrically connected to at least one or more shield dams 175A of the first shield member 175A and at least one or more shield dams 175B of the second shield member 175B may be Ground (GND) pattern connection pads 122 electrically connected to Ground (GND) patterns in redistribution layers 142a, 142B, and 142c of the connection member 140. For this, each of the plurality of second pads 142P2 and each of the plurality of third pads 142P3 may be electrically connected to a Ground (GND) pattern in the connection pad 122. For example, a single pad may be electrically connected to a plurality of connection pads in a one-to-many relationship.

The plurality of electrically connecting metal bumps 170 and the first and second shield members 175A and 175B may be disposed in parallel with each other on the connection member 140 at substantially the same height. In other words, each of the electrical connection metal bumps 170, each of the plurality of first shield dams 175a, and each of the plurality of second shield dams 175b may be disposed at the same height side by side. For example, the first shield member 175A and the second shield member 175B may be disposed at the same height to surround the plurality of electrical connection metal bumps 170. In this case, the plurality of electrically connecting metal bumps 170 may be formed at the same time and may include the same material (e.g., a low melting point metal including tin (Sn) or an alloy including tin).

Hereinafter, each configuration included in the semiconductor package 100A according to an exemplary embodiment will be described in more detail.

The frame 110 is an additional configuration that may provide rigidity of the semiconductor package 100A according to detailed materials and may be used to ensure thickness uniformity of the first and second encapsulants 131 and 132. A plurality of first through holes 110HA1 and 110HA2 and a second through hole 110HB may be formed in the frame 110. The plurality of first through holes 110HA1 and 110HA2 and the second through hole 110HB may be physically spaced apart from each other. Passive components 125a1 and 125a2 may be disposed in the first plurality of vias 110HA1 and 110HA2, respectively. The semiconductor chip 120 may be disposed in the second via hole 110 HB. The passive components 125a1 and 125a2 may be spaced apart from the wall surfaces of the first through holes 110HA1 and 110HA2 by a predetermined distance to be surrounded by the sidewalls of the first through holes 110HA1 and 110HA2, and the semiconductor chip 120 may be spaced apart from the wall surface of the second through hole 110HB by a predetermined distance to be surrounded by the sidewalls of the second through hole 110HB, but their modifications are possible if necessary.

The frame 110 may include a core insulating layer 111. The material of the core insulating layer 111 is not limited. For example, the material of the core insulating layer 111 may be an insulating material. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin (e.g., prepreg, ABF (Ajinomoto build-up) in which a core material such as glass fiber (or glass cloth) is impregnated with an inorganic filler such as silica in the thermosetting resin or the thermoplastic resin.

The frame 110 may include: first and second metal layers 115a and 115b disposed on wall surfaces of the first and second vias 110HA1 and 110HA2 and 110HB formed with the core insulating layer 111 to surround the passive components 125a1 and 125a2 and the semiconductor chip 120, respectively; and a third metal layer 115c and a fourth metal layer 115d disposed on the bottom surface and the top surface of the core insulating layer 111, respectively. Each of the first, second, third, and fourth metal layers 115a, 115b, 115c, and 115d may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, but the material thereof is not limited thereto. Electromagnetic shielding and heat dissipation of the semiconductor chip 120 and the passive components 125a1 and 125a2 may be performed by the first metal layer 115a, the second metal layer 115b, the third metal layer 115c, and the fourth metal layer 115 d. The metal layers 115a, 115b, 115c, and 115d may be connected to each other and may serve as a ground. In this case, the metal layers 115a, 115b, 115c, and 115d may be electrically connected to the ground of the redistribution layers 142a, 142b, and 142c of the connection member 140.

Each of the passive components 125a1 and 125a2 may be a separate capacitor, such as a multilayer ceramic capacitor (MLCC) or a Low Inductance Chip Capacitor (LICC), an inductor, such as a power inductor, a magnetic bead, or the like. The passive components 125a1 and 125a2 may have different thicknesses from each other. In addition, the passive components 125a1 and 125a2 may have a thickness different from that of the semiconductor chip 120. In the semiconductor package 100A according to an exemplary embodiment, the passive components 125a1 and 125a2 are encapsulated through two or more steps to significantly reduce defects caused by thickness variation. The number of passive components 125a1 and 125a2 is not limited and may be greater or less than the number of passive components shown in the figures.

The first encapsulant 131 encapsulates the respective passive components 125a1 and 125a2 and fills at least a portion of each of the first vias 110HA1 and 110HA 2. In an exemplary embodiment, the first encapsulant 131 also encapsulates the frame 110. The first encapsulant 131 includes an insulating material. A material including an inorganic filler and an insulating resin (for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a resin in which a reinforcing material such as an inorganic filler is impregnated in a thermosetting resin or a thermoplastic resin, or the like) may be used. More specifically, ABF, FR-4, Bismaleimide Triazine (BT) resin, and the like can be used. In addition, a molding material such as Epoxy Molding Compound (EMC) may be used. If desired, a photosensitive material (e.g., a photosensitive encapsulant (PIE)) can be used. Further, if necessary, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber (or glass cloth) may be used. In either case, in detail, the first encapsulant 131 is non-conductive.

The semiconductor chip 120 is disposed in the second via hole 110 HB. The semiconductor chip 120 may be spaced apart from the wall surface of the second via 110HB by a predetermined distance to be surrounded by the wall surface of the second via 110HB, but variations thereof are possible if necessary. Semiconductor chip 120 may be an Integrated Circuit (IC) in which hundreds to millions of devices are integrated in a single chip. The IC may be, but is not limited to, a Power Management IC (PMIC). The IC may be: memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; application processor chips such as central processing units (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors; and logic chips such as analog-to-digital converters, Application Specific Integrated Circuits (ASICs), and the like.

The semiconductor chip 120 may be a bare integrated circuit without forming a separate bump or wiring layer, but is not limited thereto. The semiconductor chip 120 may be a packaged integrated circuit, if desired. Integrated circuits may be formed on an active wafer basis. In this case, the base material for forming the body 121 of the semiconductor chip 120 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed in the body 121. The connection pad 122 may be provided to electrically connect the semiconductor chip 120 to another component and may be formed using a conductive material such as aluminum (Al), but the material of the connection pad 120 is not limited thereto. A passivation layer 123 may be disposed on the body 121 to expose the connection pad 122. The passivation layer 123 may be an oxide layer or a nitride layer. Alternatively, the passivation layer 123 may be a double layer of oxide/nitride. Insulating layers (not shown) and the like may also be provided at other desired positions. The semiconductor chip 120 has an active surface on which the connection pads 122 are provided and an inactive surface disposed opposite to the active surface. In the case where the passivation layer 123 is provided on the effective surface of the semiconductor chip 120, the positional relationship of the effective surface of the semiconductor chip 120 is determined based on the lowermost surface of the passivation layer 123.

The second encapsulant 132 encapsulates the semiconductor chip 120. Further, the second encapsulant 132 fills at least part of the via hole 110 HB. In the exemplary embodiment, second encapsulant 132 also encapsulates frame 110. The second encapsulant 132 includes an insulating material. A material including an inorganic filler and an insulating resin (for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a resin in which a reinforcing material such as an inorganic filler is impregnated in a thermosetting resin or a thermoplastic resin, or the like) may be used. More specifically, ABF, FR-4, Bismaleimide Triazine (BT) resin, and the like can be used. In addition, a molding material such as Epoxy Molding Compound (EMC) may be used. If desired, a photoresist material (e.g., a photosensitive encapsulant (PIE)) can be used. Further, if necessary, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber (or glass cloth) may be used.

As described above, in the semiconductor package 100A, the plurality of passive components 125a1 and 125a2 are provided in a single package together with the semiconductor chip 120 to be molded. Therefore, the spacing between the components can be significantly reduced. As a result, as shown in fig. 21, the mounting area of a printed circuit board such as the main board 1101 can be significantly reduced. Furthermore, the electrical path between the semiconductor chip 120 and the passive components 125a1 and 125a2 may be significantly reduced to prevent noise issues. Two or more encapsulation steps may be performed instead of performing only one encapsulation step to significantly reduce yield problems of the semiconductor chip 120 due to poor mounting of the passive components 125a1 and 125a2 or the influence of foreign objects generated when the passive components 125a1 and 125a2 are mounted.

If desired, a backside metal layer 135 may be disposed on the second encapsulant 132 to cover the semiconductor chip 120 and the passive components 125a1 and 125a 2. The backside metal layer 135 may be connected to the fourth metal layer 115d of the frame 110 through backside metal vias 133 that penetrate the first encapsulant 131 and the second encapsulant 132. The semiconductor chip 120 and the passive components 125a1 and 125a2 may be surrounded by metal materials such as the backside metal layer 135 and the backside metal vias 133 to further improve EMI shielding and heat dissipation. The backside metal layer 135 and the backside metal via 133 may further include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The backside metal layer 135 and the backside metal vias 133 may also serve as ground. In this case, the backside metal layer 135 may be electrically connected to the ground of the redistribution layers 142a, 142b, and 142c of the connection member 140 through the metal layers 115a, 115b, 115c, and 115 d. As shown in fig. 13, the backside metal layer 135 may be in the form of a plate covering most of the top surface of the second encapsulant 132. As shown in fig. 13, the backside metal vias 133 may be in the form of trench vias having a predetermined length. In this case, all electromagnetic propagation paths can be blocked to exhibit an excellent electromagnetic shielding effect. However, the shape of the back-side metal layer 135 is not limited thereto, and the back-side metal layer 135 may have a plurality of plate shapes within a range having an electromagnetic shielding effect. An opening may be formed in the center of the backside metal via 133 to provide a gas flow path.

As described above, the semiconductor package 100A may further include the metal layers 115a and 115b disposed on the wall surfaces of the first and second vias 110HA1 and 110HA2 and 110HB on which the core insulating layer 111 is formed, and the metal layers 115c and 115d disposed on the bottom and top surfaces. Therefore, electromagnetic waves flowing into the inside or emitted from the inside of the semiconductor chip 120 and the passive components 125a1 and 125a2 can be effectively shielded. In addition, a heat dissipation effect can be achieved. In addition, the EMI shielding effect and the heat dissipation effect of the semiconductor chip 120 and the passive components 125a1 and 125a2 may be further improved by the backside metal via 133 penetrating the first encapsulant 131 and/or the second encapsulant 132.

The second encapsulant 132 may further include an electromagnetic wave absorbing material, if necessary. For example, the second encapsulant 132 may include magnetic particles and a binder resin, but is not limited thereto. The magnetic particles may be metal particles including at least one selected from the group consisting of iron (Fe), chromium (Cr), aluminum (Al), and nickel (Ni), and may be, for example, Fe-Si-B-Cr-based amorphous metal particles, but are not limited thereto. The magnetic particles may be ferrite particles such as Mn-Zn ferrite, Ni-Zn-Cu ferrite, Mn-Mg ferrite, Ba ferrite, Li ferrite, etc. The binder resin may be an epoxy resin, a polyimide, a liquid crystal polymer, or a mixture thereof, but is not limited thereto. If desired, the porous particles may be used as magnetic particles to more easily achieve electromagnetic absorption characteristics, but are not limited thereto.

As described above, in the semiconductor package 100A according to an exemplary embodiment, the second encapsulant 132 encapsulating the semiconductor chip 120 may have an electromagnetic absorption rate higher than that of the first encapsulant 131. For example, the second encapsulant 132 may include a magnetic material. In the case where electromagnetic shielding is simply performed by the metal layers 115a, 115b, 115c, and 115d, the back-side metal layer 135, and the back-side metal via 133, EMI noise continues to propagate in the semiconductor package 100A. Eventually, EMI noise may leak to the outside through the weakest portion of the EMI shield and may affect devices disposed near the weakest portion of the EMI shield. On the other hand, in the case where the second encapsulant includes a magnetic material, the propagating reflected EMI noise is absorbed by the second encapsulant 132 and leaks to the outside through the ground GND. Thus, a portion susceptible to EMI interference can be eliminated. In this case, in detail, the first encapsulant 131 encapsulating the passive components 125a1 and 125a2 may be a typical insulating material. This is because: since the electrodes are exposed in the case of the passive components 125a1 and 125a2, a short defect occurs when the first encapsulant 131 is conductive.

The connection members 140 may redistribute the connection pads 122 of the semiconductor chip 120 and may electrically connect the semiconductor chip 120 to the passive components 125a1 and 125a 2. Tens to hundreds of connection pads 122 of the semiconductor chip 120 having various functions may be redistributed by the connection members 140, respectively, and may be physically and/or electrically connected to an external device by electrically connecting the metal bumps 170 and the shield members 175A and 175B according to the functions. The connection member 140 may include: a first insulating layer 141a disposed on the lower sides of the frame 110 and the passive components 125a1 and 125a 2; a first redistribution layer 142a disposed on a bottom surface of the first insulating layer 141 a; a first connection via 143a penetrating the first insulating layer 141a to electrically connect the passive components 125a1 and 125a2 to the first redistribution layer 142 a; a second insulating layer 141b disposed on the bottom surface of the first insulating layer 141a and the active surface of the semiconductor chip 120 to cover at least a portion of the first redistribution layer 142 a; a second redistribution layer 142b disposed on a bottom surface of the second insulation layer 141 b; a second connection via 143b penetrating the second insulating layer 141b to electrically connect the first and second redistribution layers 142a and 142b and to electrically connect the connection pad 122 of the semiconductor chip 120 and the second redistribution layer 142 b; a third insulating layer 141c disposed on a bottom surface of the second insulating layer 141b to cover at least a portion of the second redistribution layer 142 b; a third redistribution layer 142c disposed on a bottom surface of the third insulation layer 141 c; and a third connection via 143c penetrating the third insulating layer 141c to electrically connect the second redistribution layer 142b and the third redistribution layer 142 c. The connection member 140 may include a greater number of insulating layers, wiring layers, and connection via layers than those illustrated in the drawings.

The material of the insulating layer 141a may be an insulating material. The insulating material may be a non-photosensitive dielectric (e.g., ABF) including an inorganic filler such as silicon dioxide or aluminum oxide. In this case, the problem of undulation (problem caused by cracks) can be effectively solved. In addition, the electrode open defect caused by the bleeding of the material for forming the first encapsulant 131 can be effectively solved. For example, when a non-photosensitive dielectric including an inorganic filler is used as the material of the first insulating layer 141a, problems (e.g., a waving problem or an electrode opening defect) occurring when simply using a photosensitive dielectric (PID) can be more effectively solved.

A photosensitive dielectric (PID) may be used as the material of the second insulating layer 141 b. In this case, similar to the case of the related art, a fine pitch may be introduced through the photolithographic via, allowing tens to millions of connection pads 122 of the semiconductor chip 120 to be effectively redistributed. The photoactive dielectric (PID) may include a small amount of inorganic filler or may not include inorganic filler. An excellent synergistic effect can be achieved by selectively controlling, for example, the material of the first insulating layer 141a on which the first redistribution layer 142a (for redistributing the passive components 125a1 and 125a 2) and the first connection via 143a are formed and the material of the second insulating layer 141b on which the second redistribution layer 142b (for redistributing the connection pads 122 of the semiconductor chip 120) and the second connection via 143b are formed.

If necessary, the first insulating layer 141a formed using a non-photosensitive dielectric including an inorganic filler may have a multi-layer structure, the second insulating layer 141b formed using a photosensitive dielectric (PID) may include a plurality of layers, and both the first insulating layer 141a and the second insulating layer 141b may include a plurality of layers. The second via hole 110HB may penetrate the first insulating layer 141a formed using a non-photosensitive dielectric. In the case where the first insulating layer 141a includes a plurality of layers, the second via hole 110HB may penetrate all of the plurality of layers.

The Coefficient of Thermal Expansion (CTE) of the first insulating layer 141a may be less than the CTE of the second insulating layer 141 b. This is because the first insulating layer 141a includes an inorganic filler. The second insulating layer 141b may include a small amount of inorganic filler, if necessary. However, the weight percentage of the inorganic filler included in the first insulating layer 141a may be greater than the weight percentage of the inorganic filler included in the second insulating layer 141 b. Accordingly, the CTE of the first insulating layer 141a may be less than that of the second insulating layer 141 b. The first insulating layer 141a including a relatively larger amount of the inorganic filler to have a relatively smaller CTE is advantageous to suppress warpage such as small thermosetting shrinkage. As described above, problems such as undulation or crack can be effectively solved, and the electrode opening defects of the passive components 125a1 and 125a2 can also be effectively solved.

The third insulating layer 141c is an insulating layer provided on the lowermost surface of the semiconductor package 100A to function as a passivation layer or a solder resist layer. The third insulating layer 141c includes an insulating resin and an inorganic filler, but may not include glass fiber. For example, the third insulating layer 141c may be ABF, but is not limited thereto.

The first redistribution layer 142a may redistribute the electrodes of the passive components 125a1 and 125a2 so that the electrodes are electrically connected to the connection pads 122 of the semiconductor chip 120. For example, first redistribution layer 142a may function as a redistribution layer (RDL). The material for forming the first redistribution layer 142a may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. First redistribution layer 142a may perform various functions depending on the design. For example, the first redistribution layer 142a may include a Ground (GND) pattern, a Power (PWR) pattern, a signal (S) pattern, and the like. The signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) other than the GND pattern, the PWR pattern, etc. In addition, the first redistribution layer 142a may include a via pad or the like. The second via hole 110HB provided with the semiconductor chip 120 also penetrates the first insulating layer 141 a. The bottom surface of the first redistribution layer 142a may be disposed at substantially the same height as the active surface of the semiconductor chip 120. For example, a bottom surface of the first redistribution layer may be coplanar with an active surface of the semiconductor chip 120.

The second redistribution layer 142b may redistribute the connection pads 122 of the semiconductor chip 120 so that the connection pads 122 are electrically connected to the electrical connection metal bumps 170. For example, second redistribution layer 142b may function as a redistribution layer (RDL). The material for forming the second redistribution layer 142b may also be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. The second redistribution layer 142b may perform various functions according to design. For example, the second redistribution layer 142b may include a Ground (GND) pattern, a Power (PWR) pattern, a signal (S) pattern, and the like. The signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) other than the GND pattern, the PWR pattern, etc. In addition, the second redistribution layer 142b may include a via pad or the like.

The first connection vias 143a electrically connect the passive components 125a1 and 125a2 to the first redistribution layer 142 a. The first connection through hole 143a may be in physical contact with an electrode of each of the passive components 125a1 and 125a 2. For example, the passive components 125a1 and 125a2 may be in direct contact with the first connection via hole 143a in an embedded type, rather than a surface-mounted type, using solder bumps or the like. The material for forming the first connection via hole 143a may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. The first connection via hole 143a may be completely filled with a conductive material, or a conductive material may be provided along the via hole wall. The first connection through hole 143a may have a tapered shape.

The second connection via 143b electrically connects the first and second redistribution layers 142a and 142b disposed on different layers to each other and also electrically connects the connection pad 122 of the semiconductor chip 120 and the second redistribution layer 142b to each other. The second connection via 143b may physically contact the connection pad 122 of the semiconductor chip 120. For example, the semiconductor chip 120 may be directly connected to the second connection via 143b of the connection member 140 in the form of a bare chip without a separate bump or the like. Similar to the first connection via 143a, a material for forming the second connection via 143b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. The second connection via 143b may be completely filled with a conductive material, or a conductive material may be disposed along the via wall. The second connection via 143b may have a tapered shape.

The depth db of the second through hole 110HB may be greater than the depths da1 and da2 of the first through holes 110HA1 and 110HA 2. The bottom surface of the second via 110HB may be disposed lower than the bottom surfaces of the first vias 110HA1 and 110HA 2. This is because: the second via hole 110HB may also penetrate the first insulating layer 141 a. For example, the bottom surfaces may have steps. The bottom surface of the second via 110HB may be the top surface of the second insulating layer 141b, and the bottom surfaces of the first vias 110HA1 and 110HA2 may be the top surface of the first insulating layer 141 a. For example, the semiconductor chip 120 may have an active surface on which the connection pad 122 connected to the second connection via 143b is disposed and an inactive surface disposed opposite to the active surface. The active surface of the semiconductor chip 120 may be disposed lower than the bottom surfaces of the passive components 125a1 and 125a 2. For example, the active surface of the semiconductor chip 120 may be substantially coplanar with the bottom surface of the first redistribution layer 142 a.

Generally, the connection pads of the semiconductor chip are formed using aluminum (Al) and may be easily damaged during the laser via process. Thus, the connection pads are typically opened by a photolithographic via process rather than a laser via process. For this purpose, photosensitive dielectrics (PIDs) have been used as insulating layers arranged to form redistribution layers (RDLs). However, in the case where a photosensitive dielectric (PID) is laminated in the same manner to form a redistribution layer (RDL) on the bottom surface of the passive component, undulation may occur due to electrode protrusions of the passive component to deteriorate the flatness of the PID. Therefore, a photo dielectric (PID) having a large thickness should be used to improve flatness, which causes inconvenience. In this case, cracks are liable to occur due to the thickness of the PID.

In addition, in the case where an encapsulant is used to encapsulate a passive component, the encapsulant-forming material may permeate to the electrodes of the passive component. As described above, when a photosensitive dielectric (PID) is used to form a redistribution layer (RDL), a photolithographic via process is performed. In this case, it may be difficult to open the oozed encapsulant forming material using a photolithographic via process. Therefore, an electrode opening defect may be caused due to the oozed encapsulant forming material. As a result, the electrical characteristics may be deteriorated.

On the other hand, in the semiconductor package 100A according to the exemplary embodiment, after the first vias 110HA1 and 110HA2 in which the passive components 125a1 and 125a2 are disposed are formed and the passive components 125a1 and 125a2 are disposed, the first insulating layer 141a and the first redistribution layer 142a may be disposed to perform first redistribution of the passive components 125a1 and 125a 2. After the second via hole 110HB is formed to penetrate the first insulating layer 141a and dispose the semiconductor chip 120, the second insulating layer 141b and the second redistribution layer 142b may be disposed to perform the second redistribution of the semiconductor chip 120. For example, the second through hole 110HB provided with the semiconductor chip 120 may penetrate not only the frame 110 but also the first insulating layer 141a of the connection member 140. Accordingly, the effective surface of the semiconductor chip 120 may be disposed lower than the bottom surfaces of the passive components 125a1 and 125a 2. In this case, the material of the first insulating layer 141a may be selected without considering the semiconductor chip 120. For example, the material of the first insulating layer 141a may be a non-photosensitive dielectric including an inorganic filler instead of a photosensitive dielectric (PID) such as ABF (Ajinomoto build-up film). Since such a film-type non-photosensitive dielectric has excellent flatness, the above-described undulation and crack problems can be more effectively solved. In addition, since such a non-photosensitive dielectric has an opening formed as a via hole, even if the material of the first encapsulant 131 penetrates into the electrodes of the passive components 125a1 and 125a2, the electrodes of the passive components 125a1 and 125a2 can be effectively opened by the via hole formed by laser drilling. Therefore, the problems caused by the electrode open defect can be solved.

The material of the second insulating layer 141b may be a photosensitive dielectric (PID). In this case, a fine pitch can be introduced through the photosensitive vias. Therefore, tens to millions of connection pads 122 of the semiconductor chip 120 can be redistributed very efficiently. For example, the structure of the semiconductor package 100A according to an exemplary embodiment may allow selective control of a material of the first insulating layer 141a formed with the first redistribution layer 142a (for redistributing the passive components 125a1 and 125a 2) and the first connection via 143a and a material of the second insulating layer 141b formed with the second redistribution layer 142b (for redistributing the connection pads 122 of the semiconductor chip 120) and the second connection via 143b to have an excellent synergistic effect.

In addition to electrically connecting the metal bumps 170 and the shield members 175A and 175B, the third redistribution layer 142c and the third connection vias 143c may serve as an under-bump metal that is the lowermost electrical configuration of the semiconductor package 100A. The connection reliability of the electrically connecting metal bumps 170 and the shielding members 175A and 175B may be improved by the third redistribution layer 142c and the third connection vias 143 c. The third redistribution layer 142c may be mainly used as a pad electrically connecting the metal bump and the shield member. For example, the third redistribution layer 142c includes a plurality of first pads 142P1, second pads 142P2, and third pads 142P 3. The material for forming the third redistribution layer 142c may also be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. The third connecting via 143c electrically connects the second redistribution layer 142b and the third redistribution layer 142 c. Among the third connection vias 143c, the connection vias connected to the first pads 142P1 of the third redistribution layer 142c may be connected to the first pads 142P1 in a one-to-many manner. The material of the third connection via 143c may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. The third connecting via 143c may also be completely filled with a conductive material, or a conductive material may be provided along the via wall. The third connection via 143c may have a tapered shape.

The third redistribution layer 142c includes: a plurality of first pads 142P 1; a plurality of second pads 142P2 disposed to surround the plurality of first pads 142P1 along the outer circumference of the connection member 140; and a plurality of third pads 142P3 disposed to surround the plurality of second pads 142P2 along the outer circumference of the connection member 140. A shape of each of the plurality of second pads 142P2 and a shape of each of the plurality of third pads 142P3 may be set to be different from a shape of each of the plurality of first pads 142P 1. For example, each of the plurality of second pads 142P2 and each of the plurality of third pads 142P3 may have predetermined lengths l1 and l2, respectively, along the outer circumference of the connection member 140, and each of the plurality of first pads 142P1 may have a circular shape.

The third redistribution layer 142c and the third connecting via 143c may be omitted if necessary. In this case, the first pad 142P1 of the connection member 140 connected to the electrical connection metal bump 170 and the second pad 142P2 and the third pad 142P3 connected to the shield members 175A and 175B may be part of the second redistribution layer 142B. The electrically connecting metal bumps 170 and the shield members 175A and 175B may be directly disposed in the openings formed on the third insulating layer 143c, and the shapes of the openings may be changed to conform to the shapes of the electrically connecting metal bumps 170 and the shapes of the shield members 175A and 175B.

The backside metal layer 135, the backside metal via 133, and the first, second, third, and fourth metal layers 115a, 115b, 115c, and 115d may be electrically connected to Ground (GND) patterns in the redistribution layers 142a, 142b, and 142c of the connection member 140. Therefore, when the semiconductor package 100A is mounted on a motherboard or the like of an electronic device, electromagnetic waves can be emitted to the ground or the like of the motherboard through this path.

The electrical connection metal bumps 170 may be configured to physically and/or electrically connect the semiconductor package 100A to external components. For example, the semiconductor package 100A may be mounted on a motherboard of an electronic device by electrically connecting the metal bumps 170. The electrical connection metal bump 170 may include a low melting point metal (e.g., tin (Sn) or an alloy including tin). More specifically, the electrical connection metal bump 170 may be formed using solder or the like. However, these cases are merely examples and are not limited thereto. The electrically connecting metal bumps 170 may be pads, solder balls, pins, etc. The electrical connection metal bump 170 may have a multi-layer structure or a single-layer structure. In the case where the electrical connection metal bump 170 is formed in a single layer structure, the electrical connection metal bump 170 may include tin-silver solder or copper. However, this case is also merely an example and the material of the electrical connection metal bump 170 is not limited thereto. The number, pitch, arrangement shape, etc. of the electrical connection metal bumps 170 are not limited and may be changed according to design consideration of those of ordinary skill in the art. For example, the number of the electrical connection metal bumps 170 may be several tens to several thousands according to the number of the connection pads 122, but is not limited thereto.

At least one of the electrical connection metal bumps 170 may be disposed in the fan-out region. The term "fan-out region" refers to a region other than the region where the semiconductor chip 120 is disposed. The fan-out type package has excellent reliability compared to a fan-in type package, allows a plurality of I/O terminals to be implemented, and allows 3D interconnection to be easily implemented. Further, the fan-out type package may be manufactured to have a small thickness and have excellent price competitiveness as compared to a Ball Grid Array (BGA), a grid array (LGA), or the like.

When the semiconductor package 100A is printed on a printed circuit board or the like by the electrically connecting metal bumps 170, the shielding members 175A and 175B are configured to shield electromagnetic waves E radiated through a space between the semiconductor chip and the printed circuit board. In addition, as described above, board-level reliability can be improved by the shield members 175A and 175B. The shielding members 175A and 175B include at least one shielding dam 175A having a predetermined distance L1 along the outer circumference of the connection member 140 and at least one shielding dam 175B having a predetermined distance L2 along the outer circumference of the connection member 140, respectively. For example, the shielding member 175A may discontinuously surround the plurality of electrical connection metal bumps 170 along the outer circumference of the connection member 140, and the shielding member 175B may discontinuously surround the first shielding member 175A along the outer circumference of the connection member 140. More specifically, the shielding member 175A may have a plurality of shielding dams 175A and a plurality of gaps 175ah formed between the plurality of shielding dams 175A, and the shielding member 175B may have a plurality of shielding dams 175B and a plurality of gaps 175bh formed between the plurality of shielding dams 175B. Due to the presence of the gaps 175ah and 175bh (e.g., spaced dots), the shield dams 175a and 175b are prevented from being disconnected due to stress. In addition, various gases generated during the process may be exhausted to further improve reliability.

The gaps 175ah of the shield member 175A and the gaps 175bh (e.g., spaced points) of the shield member 175B may be disposed so as not to intersect. Therefore, the electromagnetic wave E can be effectively shielded while passing through the curved path. The electromagnetic wave E can be shielded regardless of the presence or absence of the gaps 175ah and 175 bh. The second shield member 175B may have a gap at least one corner of the electrically connecting metal bumps 170, for example, a gap 175bh at a corner of an outer edge of the lower side of the semiconductor package 100A. In addition, the first shield member 175A may cover a corner of the electrical connection metal bump 170 (e.g., a corner of an outer edge of the lower side of the semiconductor package 100A) where the gap 175bh of the second shield member 175B is formed in a circular form without having the gap 175ah at the corner of the lower outer edge of the semiconductor package 100A. In this case, as described above, the electromagnetic wave E can be effectively shielded and the reliability can be further improved. To this end, the gaps 142P2h between the plurality of second pads 142P2 connected to the first shield dam 175A of the first shield member 175A and the gaps 142P3h between the plurality of third pads 142P3 connected to the second shield dam 175B of the second shield member 175B may also be disposed not to cross each other, the plurality of third pads 142P3 may have at least one gap 142P3h at least one corner of the connection member 140, and at least one of the plurality of second pads 142P2 may be disposed at the corner of the connection member 140 (the gap 142P3h having the plurality of third pads 142P 3) to cover the corner in a circular form.

The shield dam 175A of the shield member 175A and the shield dam 175B of the shield member 175B may be formed using a low melting point metal, for example, tin (Si) or an alloy containing tin. In more detail, the shield dams 175a and 175b may be formed using solder or the like, but the material of the shield dams 175a and 175b is not limited thereto. The shield dam 175A of the shield member 175A may have a predetermined length L1 greater than a width W1 (e.g., a spacing between the shield dams 175A) of the gap 175ah of the shield member 175A, and the shield dam 175B of the shield member 175B may have a predetermined length L2 greater than a width W2 (e.g., a spacing between the shield dams 175B) of the gap 175bh of the shield member 175B. When the shielding dam 175A of the shielding member 175A and the shielding dam 175B of the shielding member 175B have lengths L1 and L2, respectively, an electromagnetic shielding effect and a reliability improvement effect can be achieved. The number of shield dams 175a and 175b, the number of gaps 175ah and 175bh, and the like are not limited thereto. To this end, the length l1 of each of the plurality of second pads 142P2 and the length l2 of each of the plurality of third pads 142P3 may be greater than the width w1 of the gap 142P2h and the width w2 of the gap 142P3h, respectively.

Each of the at least one or more shield dams 175A of the shield member 175A and each of the at least one or more shield dams 175B of the shield member 175B may be electrically connected to the at least two connection pads 122. For example, the shield dams 175a and 175b may be electrically connected to the connection pads 122 in a one-to-many manner. In this case, the shield dam 175A of the shield member 175A and the shield dam 175B of the shield member 175B may be electrically connected to the Ground (GND) pattern in the redistribution layers 142a, 142B, and 142c of the connection member 140, and the at least two connection pads 122 electrically connected to each of the at least one or more shield dams 175A of the shield member 175A and each of the at least one or more shield dams 175B of the shield member 175B may be the Ground (GND) connection pads 122 electrically connected to the Ground (GND) pattern of the redistribution layers 142a, 142B, and 142c of the connection member 140. To this end, each of the plurality of second pads 142P2 and each of the plurality of third pads 142P3 may be electrically connected to the ground connection pad 122 among the connection pads 122. Each of the plurality of second pads 142P2 and each of the plurality of third pads 142P3 may be connected to the Ground (GND) connection pad 122 in a one-to-many manner (e.g., a single pad may be electrically connected to a plurality of connection pads).

If necessary, a cover layer 180 may be further disposed on the first encapsulant 131 and/or the second encapsulant 132 to cover the backside metal layer 135. The cover layer 180 may include an insulating resin and an inorganic filler, but may not include glass fiber. For example, the cover layer 180 may be ABF, but is not limited thereto.

Although the semiconductor package 100A according to the exemplary embodiment has been described as the semiconductor package 100A including the semiconductor chip 120, the semiconductor package 100A may include only the passive components 125a1 and 125a2 other than the semiconductor chip 120. For example, the description of the semiconductor package 100A according to the exemplary embodiment may be understood to extend to the electronic component package 100A. For example, the electronic component package 100A according to an exemplary embodiment may include: a plurality of electrically connecting metal bumps 170 disposed at one side of the electronic component package 100A; a plurality of first shielding dams 175a spaced apart from each other along the outer circumference of one side of the electronic component package 100A to surround the plurality of electrical connection metal bumps 170; and a plurality of second shielding dams 175b spaced apart from each other along an outer circumference of one side of the electronic component package 100A to surround the plurality of first shielding dams 175 a. The first and second shielding dams 175a and 175b may have predetermined lengths L1 and L2 along the outer circumference of one side of the electronic component package 100A, respectively.

Fig. 14 is a schematic cross-sectional view showing an example of a panel for manufacturing the semiconductor package in fig. 9.

Referring to fig. 14, a semiconductor package 100A according to an exemplary embodiment may be manufactured using a large-sized panel 500. The size of the panel 500 may be two to four times the size of a wafer of the prior art. Accordingly, more semiconductor packages 100A may be manufactured through a single process. For example, the yield can be very high. In detail, the larger the size of each semiconductor package 100A, the higher the relative yield compared to the case of using a wafer. The unit portion of each panel 500 may be the frame 110 first prepared in a manufacturing method that will be described later. After a plurality of semiconductor packages 100A are simultaneously manufactured by a single process using such a panel 500, the plurality of semiconductor packages 100A may be diced using a well-known dicing process (such as a dicing process or the like) to obtain individual semiconductor packages 100A.

Fig. 15A to 15E are process diagrams illustrating an exemplary example of manufacturing the semiconductor package in fig. 9.

Referring to fig. 15A, the frame 110 is first prepared. After the Copper Clad Laminate (CCL) is prepared using the panel 500 described above, the metal layers 115a, 115b, 115c, and 115d may be formed using copper foils of the Copper Clad Laminate (CCL) through a well-known plating process, such as SAP or MSAP. For example, each of the metal layers 115a, 115b, 115c, and 115d may include a seed layer and a conductive layer formed on the seed layer to have a greater thickness. The first through holes 110HA1 and 110HA2 and the preliminary second through hole 110 HB' may be formed using laser drilling and/or mechanical drilling, sand blasting, or the like according to the material of the core insulating layer 111. Next, the first adhesive film 210 may be attached to the lower side of the frame 110, and the passive components 125a1 and 125a2 are disposed in the first through holes 110HA1 and 110HA2, respectively. The first adhesive film 210 may be a known tape, but is not limited thereto.

Referring to fig. 15B, the frame 110 and the passive components 125a1 and 125a2 are encapsulated using a first encapsulant 131. The first encapsulant 131 may be formed by laminating uncured insulating films and curing the laminated insulating films, or the first encapsulant 131 may be formed by coating a liquid insulating film and curing the coated insulating film. Next, the first adhesive film 210 is removed. The first adhesive film 210 may be separated using a mechanical method. After the first insulating layer 141a is formed at the portion of the first adhesive film 210 removed using the ABF lamination method and the via hole is formed as the laser via hole, the first redistribution layer 142a and the first connection via hole 143a are formed using a well-known plating process, such as SAP or MSAP. For example, the first redistribution layer 142a and the first connection via 143a may each include a seed layer and a conductor layer having a thickness greater than that of the seed layer. The second via hole 110HB is formed to penetrate the first encapsulant 131 and the first insulating layer 141a using laser drilling and/or mechanical drilling, sandblasting, or the like. In this case, the side surface of the second metal layer 115b and the wall surface of the first encapsulant 131 forming the second via hole 110HB may be substantially coplanar with each other.

Referring to fig. 15C, a second adhesive film 220 is attached to the lower side of the first insulating layer 141a, and the semiconductor chip 120 is attached in an effective surface-down form on a surface of the second adhesive film 220 exposed through the second through hole 110 HB. The first encapsulant 131 and the semiconductor chip 120 are encapsulated by the second encapsulant 132. Similar to the first encapsulant 131, the second encapsulant 132 may be formed by laminating uncured insulating films and curing the laminated insulating films, or the second encapsulant 132 may be formed by coating a liquid insulating film and curing the coated insulating film. Carrier film 230 is attached to second encapsulant 132. In particular instances, the second encapsulant 132 may be formed on the carrier film 230 and then laminated. To perform the process, the manufactured unfinished module is vertically turned over, and the second adhesive film 220 is separated using a mechanical method or the like to be removed.

Referring to fig. 15D, after a second insulating layer 141b is formed by laminating a photosensitive dielectric (PID) on the first insulating layer 141a and the active surface of the semiconductor chip 120 and a via hole is formed as a photosensitive via hole, a second redistribution layer 142b and a second connection via hole 143b are formed using a well-known plating process. The second redistribution layer 142b and the second connection via 143b may further each include a seed layer and a conductor layer. The third insulating layer 141c is formed on the second insulating layer 141b using a known lamination method or coating method. Carrier film 230 is separated to remove carrier film 230. The unfinished module is then turned vertically.

Referring to fig. 15E, a via hole 133v is formed to penetrate the first and second encapsulants 131 and 132 using laser drilling or the like. An opening is formed on the third insulating layer 141c using laser drilling or the like to expose at least a portion of the second redistribution layer 142 b. The backside metal vias 133 and backside metal layer 135 are formed using a well-known plating process. The backside metal via 133 and the backside metal layer 135 may each include a seed layer and a conductor layer. A capping layer 180 is formed on the second encapsulant 132. When the electrically connecting metal bumps 170 are formed on the plurality of first pads 142P1 and the shielding members 175A and 175B are formed on the plurality of second pads 142P2 and the plurality of third pads 142P3, the semiconductor package 100A according to the exemplary embodiment described above is manufactured. Due to the reflow process, the shield dam 175A of the shield member 175A and the shield dam 175B of the shield member 175B may be formed by connecting a plurality of adjacent solder balls to each other.

In the case of using the panel 500 or the like in fig. 14, a plurality of semiconductor packages 100A may be manufactured by a single process using the above-described series of steps. Then, a single semiconductor package 100A may be obtained using a dicing process or the like.

Fig. 16A and 16B are schematic plan views illustrating various examples when the semiconductor package in fig. 9 is viewed along the direction "a".

Referring to fig. 16A and 16B, in plan views a' and a ″ according to another exemplary embodiment, the electrical connection metal bump 170 may be of a Land Grid Array (LGA) type. For example, the above-described semiconductor package 100A according to an exemplary embodiment may be a Ball Grid Array (BGA) type as well as an LGA type. In the case where the semiconductor package 100A is of the LGA type, a shielding member 175A having a shielding dam 175A and a gap 175ah and a shielding member 175B having a shielding dam 175B and a gap 175bh may be introduced to effectively shield the electromagnetic waves E, and the design may also be improved to prevent cracks C of a reliability weak point.

Fig. 17 schematically shows another example of a semiconductor package.

Referring to fig. 17, a semiconductor package 100B according to another exemplary embodiment includes a frame 110, the frame 110 including first and second wiring layers 112a and 112B disposed on bottom and top surfaces of a core insulating layer 111, respectively, and a wiring via 113 penetrating the core insulating layer 111 to electrically connect the first and second wiring layers 112a and 112B to each other. First and second routing layers 112a and 112b may be electrically connected to connection pads 122 of semiconductor chip 120 and/or passive components 125a1 and 125a2 through redistribution layers 142a, 142b, and 142c and connection vias 143a and 143 b. Due to the frame 110, the semiconductor package 100B has a vertical electrical connection path to be introduced to the package on package structure.

The wiring layers 112a and 112b are used to redistribute the connection pads 122 of the semiconductor chip 120. The material for forming the wiring layers 112a and 112b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The routing layers 112a and 112b may perform various functions depending on the design of their respective layers. For example, the wiring layers 112a and 112b may include a Ground (GND) pattern, a signal (S) pattern, and the like. The signal patterns may include various signal patterns such as a data signal pattern, etc., in addition to a Ground (GND) pattern, a Power (PWR) pattern, etc. In addition, the wiring layers 112a and 112b may include via pads, line pads, electrically connecting metal bump pads, and the like. The wiring layers 112a and 112b may also be formed using a well-known plating process, and may include a seed layer and a conductor layer, respectively. The thickness of each of the routing layers 112a and 112b may be greater than the thickness of each of the redistribution layers 142a, 142b, and 142 c.

The material of the core insulating layer 111 is not limited, and may be, for example, an insulating material. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin (e.g., prepreg, etc.) in which a core material such as glass fiber (or glass cloth) is mixed with or impregnated in the thermosetting resin or the thermoplastic resin together with an inorganic filler such as silica.

The wiring vias 113 electrically connect the wiring layers 112a and 112b formed on different layers, resulting in an electrical path formed in the frame 110. The material used to form the wire via 113 may also be a conductive material. The routing via 113 may be completely filled with a conductive material, or may be a via of a conductive material formed along a wall surface of the via hole. In addition, the routing via 113 may have an hourglass shape. The wiring vias 113 may also be formed using known plating processes and may include seed layers and conductor layers.

In addition to the backside metal layer 135, the semiconductor package 100B according to another exemplary embodiment may further provide a backside wiring layer 135s on the second encapsulant 132. The backside wiring layer 135s may be connected to the second wiring layer 112b of the frame 110 through backside wiring vias 133s penetrating the first encapsulant 131 and the second encapsulant 132. Openings 180v1 and 180v2 may be formed in the capping layer 180 to expose at least a portion of the backside metal layer 135 and at least a portion of the backside wiring layer 135s, respectively. The electrical connection metal bumps 190A and 190B may be disposed on the openings 180v1 and 180v2, respectively, to be connected to the backside metal layer 135 and the backside wiring layer 135s exposed through the openings 180v1 and 180v 2.

The backside metal layer 135 and backside metal vias 133 are formed for EMI shielding and heat dissipation purposes. When the backside metal layer 135 and the backside metal via 133 are connected to a printed circuit board such as a motherboard by the electrically connecting metal bump 190A, the EMI shielding effect and the heat dissipation effect can be further improved. As described above, the backside metal layer 135 and the backside metal via 133 may serve as a ground, and may be electrically connected to the ground of the redistribution layers 142a, 142b, and 142c of the connection member 140 through the metal layers 115a, 115b, 115c, and 115d of the frame 110.

The backside wiring layer 135s and the backside wiring via 133s may be electrically connected to the semiconductor chip 120 and/or the passive components 125a1 and 125a2 through the wiring layers 112a and 112b and the wiring via 113 of the frame 110, the redistribution layers 142a, 142b, and 142c of the connection member 140, and the connection vias 143a and 143 b. For example, the backside wiring layer 135s and the backside wiring via 133s are mainly used for signal connection. The backside wiring layer 135s may be electrically connected to a printed circuit board such as a motherboard by the electrical connection metal bumps 190B to provide an electrical path between the semiconductor package 100B and the printed circuit board. In this case, the semiconductor package 100B may have a back side portion mounted on the printed circuit board and a front surface portion connected to the antenna substrate or the like in a stacked package form through the electrically connecting metal bumps 170. For example, the semiconductor package 100B according to the exemplary embodiment may be easily applied to various types of module structures in the form of a package on package. The backside wiring layer 135s and the backside wiring via 133s may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

As described above, the backside metal layer 135 may cover most of the top surface of the second encapsulant 132, but may not cover the space where the backside wiring layer 135s is formed. In this case, the backside metal layer 135 and the backside wiring layer 135s may be physically spaced apart from each other by a predetermined distance. For example, the backside wiring layer 135s may be disposed in the form of an island based on the backside metal layer 135.

Each of the electrically connecting metal bumps 190A and 190B may include a low melting point metal (e.g., tin (Sn) or an alloy containing tin (Sn)). More specifically, each of the electrically connecting metal bumps 190A and 190B may be formed using solder or the like. However, this case is merely an example and the material of the electrically connecting metal bumps 190A and 190B is not limited thereto. Each of the electrically connecting metal bumps 190A and 190B may be a pad, a solder ball, a pin, or the like. Each of the electrical connection metal bumps 190A and 190B may be formed in a multi-layer structure and a single-layer structure. In the case where each of the electrical connection metal bumps 190A and 190B is formed in a single layer structure, each of the electrical connection metal bumps 190A and 190B may include tin-silver solder or copper. However, this case is also merely an example and the material of the electrically connecting metal bumps 190A and 190B is not limited thereto.

Since other components are substantially the same as those described above with reference to fig. 9 to 16B, descriptions of the other components will be omitted.

Fig. 18 schematically shows another example of a semiconductor package.

Referring to fig. 18, on the basis of the above-described semiconductor package 100B, a semiconductor package 100C according to another exemplary embodiment includes a frame 110, the frame 110 including: a first core insulating layer 111a in contact with the connection member 140; a first wiring layer 112a in contact with the connection member 140 and embedded in the first core insulating layer 111 a; a second wiring layer 112b provided on a surface of the core insulating layer 111a opposite to the surface of the core insulating layer 111a in which the first wiring layer 112a is embedded; a second core insulating layer 111b provided on the first core insulating layer 111a to cover at least part of the second wiring layer 112 b; and a third wiring layer 112c provided on the second core insulating layer 111 b. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c are electrically connected to the connection pads 122. The first and second wiring layers 112a and 112b and the second and third wiring layers 112b and 112c are electrically connected to each other through first and second wiring vias 113a and 113b penetrating the first and second core insulating layers 111a and 111b, respectively.

The first wiring layer 112a may be recessed inside the first core insulating layer 111 a. In the case where the first wiring layer 112a is recessed inside the first core insulating layer 111a to form a step between the bottom surface of the first core insulating layer 111a and the bottom surface of the first wiring layer 112a, the material for forming the first encapsulant 131 can be prevented from seeping out and contaminating the first wiring layer 112 a. The thickness of each of the wiring layers 112a, 112b, and 112c of the frame 110 may be greater than the thickness of each of the redistribution layers 142a, 142b, and 142c of the connection member 140.

The material of the core insulating layers 111a and 111b is not limited. For example, the material of the core insulating layers 111a and 111b may be an insulating material. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a core material such as glass fiber (or glass cloth) is impregnated in the thermosetting resin or the thermoplastic resin together with an inorganic filler such as silica (e.g., prepreg, ABF (Ajinomoto build-up film)). The material of the core insulating layers 111a and 111b may be a photosensitive dielectric (PID) resin, if necessary.

When forming the hole for the first wiring via 113a, some of the pads in the first wiring layer 112a may function as stoppers. Therefore, it may be advantageous for the process in which the first wire via 113a has a tapered shape in which the width of the top surface is greater than the width of the bottom surface. In this case, the first wiring via 113a may be integrated with the pad pattern of the second wiring layer 112 b.

Since other components are substantially the same as those described above with reference to fig. 9 to 17, descriptions of the other components will be omitted.

Fig. 19 schematically shows another example of a semiconductor package.

Referring to fig. 19, a semiconductor package 100D according to another exemplary embodiment includes a frame 110 on the basis of the above-described semiconductor package 100B, the frame 110 including: the first core insulating layer 111 a; a first wiring layer 112a and a second wiring layer 112b provided on the bottom surface and the top surface of the first core insulating layer 111a, respectively; a second core insulating layer 111b provided on the bottom surface of the first core insulating layer 112a to cover at least part of the first wiring layer 112 a; a third wiring layer 112c provided on the bottom surface of the second core insulating layer 111 b; a third core insulating layer 111c provided on the top surface of the first core insulating layer 111a to cover at least part of the second wiring layer 112 b; and a fourth wiring layer 112d provided on the top surface of the third core insulating layer 111 c. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d are electrically connected to the connection pads 122. Since the frame 110 includes a greater number of the wiring layers 112a, 112b, 112c, and 112d, the connection member 140 can be further simplified. Accordingly, a reduction in yield occurring during the formation of the connection member 140 can be prevented. The first, second, third, and fourth wiring layers 112a, 112b, 112c, and 112d may be electrically connected to each other through a first wiring via 113a penetrating the first core insulating layer 111a, a second wiring via 113b penetrating the second core insulating layer 111b, and a third wiring via 113c penetrating the third core insulating layer 111c, respectively.

The thickness of the first core insulation layer 111a may be greater than the thickness of the second core insulation layer 111b and the thickness of the third core insulation layer 111 c. The first core insulating layer 111a may basically have a relatively large thickness to maintain rigidity, and the second core insulating layer 111b and the third core insulating layer 111c may be introduced to form a larger number of wiring layers 112c and 112 d. The first core insulating layer 111a may include a material different from that of the second core insulating layer 111b and that of the third core insulating layer 111 c. The first core insulation layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulation resin, and each of the second and third core insulation layers 111b and 111c may be ABF or PID including an inorganic filler and an insulation resin, but the material of each of the first, second, and third core insulation layers 111a, 111b, and 111c is not limited thereto. In a similar point of view, the average diameter of the first wire via 113a penetrating the first core insulating layer 111a may be larger than the average diameter of the second wire via 113b penetrating the second core insulating layer 111b and the average diameter of the third wire via 113c penetrating the third core insulating layer 111 c. Similarly, the thickness of the routing layers 112a, 112b, 112c, and 112d of the frame 110 may be greater than the thickness of the redistribution layers 142a, 142b, and 142c of the connection members 140.

Since other components are substantially the same as those described above with reference to fig. 9 to 18, descriptions of the other components will be omitted.

Fig. 20 is a schematic sectional view illustrating an electromagnetic shielding effect in a case where the semiconductor package in fig. 9 is mounted on a printed circuit board.

Referring to fig. 20, the semiconductor package 100A according to an exemplary embodiment may be mounted on a printed circuit board 200, and the printed circuit board 200 may be a main board of an electronic device. The printed circuit board 200 may include a plurality of mounting pads 202P1, 202P2, and 202P3 to which the semiconductor package 100A is applied. For example, the printed circuit board 200 may include: a first mounting pad 202P1 connected to the electrical connection metal bump 170; a second mounting pad 202P2 connected to the first shield member 175A; and a third mounting pad 202P3 connected to the second shield member 175B. The shielding members 175A and 175B are designed to be located at outer edges of the lower side of the semiconductor package 100A to effectively prevent the electromagnetic wave E from being radiated through a space between the semiconductor package 100A and the printed circuit board 200 and to prevent cracks of a reliability weak point. This may be applicable to the semiconductor packages 100B, 100C, and 100D according to other exemplary embodiments.

Fig. 21 is a schematic plan view showing that a mounting area is significantly reduced in a case where the semiconductor package in fig. 9 is applied to an electronic device.

Referring to fig. 21, with the recent trend of mobile devices 1100A and 1100B toward large-sized displays, the demand for increasing battery capacity rises. Since the area occupied by the battery 1180 increases as the battery capacity increases, the size of the printed circuit board 1101 should be reduced. Accordingly, the component mounting area is reduced, resulting in a continuous reduction in the area that can be occupied by the module 1150 including passive components. In the case where the semiconductor package 100A according to an exemplary embodiment is applied to the module 1150, the size of the module 1150 may be significantly reduced. This may be applied to the semiconductor packages 100B, 100C, and 100D according to other exemplary embodiments.

Here, the lower side, lower surface, and the like in relation to the cross section of the drawing are used to refer to a direction toward the mounting surface of the fan-out type semiconductor package, while the upper side, upper surface, and the like are used to refer to a direction opposite to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.

In the specification, the meaning of "connected" of a component to another component includes indirect connection through an adhesive layer and direct connection between two components. Further, "electrically connected" is meant to include the concept of physically connected and physically disconnected. It will be understood that when reference is made to elements using "first" and "second," the elements are not so limited. They may be used only for the purpose of distinguishing elements from other elements, and may not limit the order or importance of the elements. In some instances, a first element may be termed a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

As described above, according to exemplary embodiments in the present disclosure, a structure for effectively shielding electromagnetic waves from being radiated through a space between a board and a package may be provided.

While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention as defined by the appended claims.