阅读说明：本技术 半导体结构和形成半导体结构的方法 (Semiconductor structure and method of forming a semiconductor structure ) 是由 陈明发 陈宪伟 余振华 于 2019-06-14 设计创作，主要内容包括：提供了集成电路封装件及其形成方法。方法包括形成第一管芯结构。第一管芯结构包括接合至载体的管芯堆叠件和堆叠的伪结构。形成第二管芯结构。第二管芯结构包括第一集成电路管芯。通过将管芯堆叠件的最顶集成电路管芯接合至第一集成电路管芯,将第一管芯结构接合至第二管芯结构。管芯堆叠件的最顶集成电路管芯是管芯堆叠件距离载体最远的集成电路管芯。对第一管芯结构实施分割工艺以形成多个单独的管芯结构。分割工艺将堆叠的伪结构分割成多个单独的堆叠的伪结构。本发明还涉及半导体结构和形成半导体结构的方法。(An integrated circuit package and a method of forming the same are provided. The method includes forming a first die structure. The first die structure includes a die stack bonded to a carrier and a stacked dummy structure. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is the integrated circuit die of the die stack that is furthest from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures. The invention also relates to a semiconductor structure and a method of forming a semiconductor structure.)

1. A method of forming a semiconductor structure, comprising:

forming a first die structure comprising a first die stack bonded to a carrier and a stacked dummy structure;

forming a second die structure, the second die structure comprising a first integrated circuit die;

bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the first die stack to the first integrated circuit die, the topmost integrated circuit die of the first die stack being the integrated circuit die of the first die stack that is furthest from the carrier; and

performing a singulation process on the first die structure to form a plurality of individual die structures, wherein the singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.

2. The method of claim 1, wherein forming the first die structure comprises:

bonding a front side of a second integrated circuit die to the carrier;

bonding a first dummy structure to the carrier adjacent the second integrated circuit die;

encapsulating the second integrated circuit die and the first dummy structure in a first encapsulant;

bonding a front side of a third integrated circuit die to a back side of the second integrated circuit die, the back side of the second integrated circuit die being opposite the front side of the second integrated circuit die;

bonding a second dummy structure to the first dummy structure; and

encapsulating the third integrated circuit die and the second dummy structure in a second encapsulant.

3. The method of claim 2, wherein the front side of the second integrated circuit die is bonded to the carrier using a fusion bonding process.

4. The method of claim 2, wherein a hybrid bonding method is used to bond the front side of the third integrated circuit die to the back side of the second integrated circuit die.

5. The method of claim 2, wherein the second dummy structure is bonded to the first dummy structure using a fusion bonding method.

6. The method of claim 1, wherein the topmost integrated circuit die of the first die stack is bonded to the first integrated circuit die using a hybrid bonding method.

7. The method of claim 1, wherein the stacked dummy structure is configured as a heat sink structure.

8. The method of claim 1, wherein the first die structure further comprises a second die stack bonded to the carrier, and wherein the stacked dummy structure is disposed over a scribe line of the carrier between the first die stack and the second die stack.

9. A method of forming a semiconductor structure, comprising:

forming a first die structure comprising a die stack bonded to a carrier;

forming a second die structure, the second die structure comprising a first integrated circuit die;

bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die, the topmost integrated circuit die of the die stack being the integrated circuit die of the die stack that is furthest from the carrier;

bonding a first dummy structure to the second die structure adjacent to the first die structure;

encapsulating the first die structure in a first encapsulant; and

performing a singulation process on the second die structure to form a plurality of individual die structures, wherein the singulation process singulates the first dummy structure into a plurality of individual dummy structures.

10. A semiconductor structure, comprising:

a die stack bonded to a base structure, the die stack including a first integrated circuit die, the first integrated circuit die being the integrated circuit die of the die stack that is furthest from the base structure;

a die structure bonded to the die stack, the die structure including a second integrated circuit die, a first side of the first integrated circuit die in physical contact with a second side of the second integrated circuit die;

a heat spreading structure bonded to the die structure adjacent to the die stack, sidewalls of the heat spreading structure being coplanar with sidewalls of the die structure; and

an encapsulant extending along sidewalls of the die stack.

Technical Field

Embodiments of the invention relate to semiconductor structures and methods of forming semiconductor structures.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following steps: depositing successively an insulating or dielectric layer, a conductive layer and a layer of semiconductor material over a semiconductor substrate; and patterning the plurality of material layers using photolithography to form circuit components and elements on the plurality of material layers. Typically tens or hundreds of integrated circuits are fabricated on a single semiconductor wafer. The individual die are cut by dicing the integrated circuit along a dicing saw. The individual dies are then packaged individually in a multi-chip module, or in other types of packages.

The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density stems from the ever-decreasing size of the smallest features (e.g., reducing the semiconductor process node to a sub-20 nm node), which allows more components to be integrated within a given area. Due to the demand for miniaturization, higher speeds and greater bandwidths, as well as lower power consumption and delay, have recently evolved, resulting in a need for smaller and more inventive semiconductor die packaging techniques.

With the further development of semiconductor technology, stacked semiconductor devices, such as three-dimensional integrated circuits (3 DICs), have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuitry, such as logic, memory, processor circuitry, etc., is fabricated on different semiconductor wafers. Two or more semiconductor wafers may be mounted or stacked on top of each other to further reduce the form factor of the semiconductor device. A Package On Package (POP) device is a type of 3DIC in which a die is packaged and then packaged with a die or dies of another package. A Package On Package (POP) device is another type of 3DIC in which a die is packaged and then packaged with another die or dies.

Disclosure of Invention

An embodiment of the present invention provides a method of forming a semiconductor structure, comprising: forming a first die structure comprising a first die stack bonded to a carrier and a stacked dummy structure; forming a second die structure, the second die structure comprising a first integrated circuit die; bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the first die stack to the first integrated circuit die, the topmost integrated circuit die of the first die stack being the integrated circuit die of the first die stack that is furthest from the carrier; and performing a singulation process on the first die structure to form a plurality of individual die structures, wherein the singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.

Another embodiment of the present invention provides a method of forming a semiconductor structure, comprising: forming a first die structure comprising a die stack bonded to a carrier; forming a second die structure, the second die structure comprising a first integrated circuit die; bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die, the topmost integrated circuit die of the die stack being the integrated circuit die of the die stack that is furthest from the carrier; bonding a first dummy structure to the second die structure adjacent to the first die structure; encapsulating the first die structure in a first encapsulant; and performing a singulation process on the second die structure to form a plurality of individual die structures, wherein the singulation process singulates the first dummy structure into a plurality of individual dummy structures.

Yet another embodiment of the present invention provides a semiconductor structure, including: a die stack bonded to a base structure, the die stack including a first integrated circuit die, the first integrated circuit die being the integrated circuit die of the die stack that is furthest from the base structure; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a first side of the first integrated circuit die in physical contact with a second side of the second integrated circuit die; a heat spreading structure bonded to the die structure adjacent to the die stack, sidewalls of the heat spreading structure being coplanar with sidewalls of the die structure; and an encapsulant extending along sidewalls of the die stack.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A and 1B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 2A and 2B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 3A and 3B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 4A and 4B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 5A and 5B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 6A and 6B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 7A and 7B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 8A and 8B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 9A and 9B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 10A and 10B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 11A and 11B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 12A and 12B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 13A and 13B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 14A and 14B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 15A and 15B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 16A and 16B illustrate top and cross-sectional views of an integrated circuit package according to some embodiments.

Fig. 17A-17C illustrate cross-sectional views of various process steps during fabrication of an integrated circuit die, according to some embodiments.

Fig. 18A and 18B illustrate cross-sectional views of various process steps during fabrication of an integrated circuit die, in accordance with some embodiments.

Fig. 19A-19G illustrate cross-sectional views of various process steps during fabrication of an integrated circuit die structure, according to some embodiments.

Fig. 20A and 20B illustrate cross-sectional views of various process steps during fabrication of an integrated circuit die structure, in accordance with some embodiments.

Figures 21A-21H illustrate top and cross-sectional views of various process steps during fabrication of an integrated circuit package, according to some embodiments.

Fig. 22A-22D illustrate cross-sectional views of various process steps during fabrication of an integrated circuit package, according to some embodiments.

Figures 23A-23F illustrate top and cross-sectional views of various process steps during fabrication of an integrated circuit package, according to some embodiments.

Fig. 24A-24C illustrate cross-sectional views of various process steps during fabrication of an integrated circuit package, according to some embodiments.

Figure 25 is a flow diagram illustrating a method of forming an integrated circuit package according to some embodiments.

Fig. 26 is a flow diagram illustrating a method of forming an integrated circuit package according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments, namely, integrated circuit packages such as 3DIC packages and methods of forming the same, will be described by way of example in the specific context. However, other embodiments may be applied to other electrically connected components, including (but not limited to): a stacked package assembly, a die-to-die assembly, a wafer-to-wafer assembly, a die-to-substrate assembly, an in-assembly package, a in-process substrate, an interposer, etc., or a combination of input assemblies, boards, dies, or other components, or any type of integrated circuit or electronic assembly for connecting packages or installations. Various embodiments described herein allow for the formation of integrated circuit packages by directly bonding integrated circuit dies to one another. Various embodiments described herein also allow for embedding the heat dissipation structure within the integrated circuit package and reducing the time to form the heat dissipation structure and the integrated circuit package. Accordingly, during production of integrated circuit packages, Wafer Per Hour (WPH) yield may be increased and production costs may be reduced.

Fig. 1A and 1B illustrate top and cross-sectional views of an Integrated Circuit (IC) package 100 according to some embodiments. Fig. 1A shows a top view, and fig. 1B shows a cross-sectional view along the line BB' in fig. 1A. In some embodiments, the IC package 100 includes a first IC die structure 101 bonded to a second IC die structure 103. In some embodiments, the first IC die structure 101 is electrically connected to the second IC die structure 103. First IC die structure 101 includes IC die 105 encapsulated in encapsulants 107 and 109. In some embodiments, IC die 105 may include a logic die, a memory die, a CPU, a GPU, an xPU, a MEMS die, an SoC die, and the like. In some embodiments, IC die 105 may be formed using the method described below with reference to fig. 17A-17C, and a detailed description of IC die 105 is then provided. The encapsulants 107 and 109 can comprise a suitable insulating material. In some embodiments, encapsulant 107 and 109 may comprise the same material. In other embodiments, encapsulant 107 and 109 may comprise different materials. In some embodiments, first IC die structure 101 also includes a plurality of connectors 111 on the front side of IC die 105, which may electrically connect IC package 100 to external components bonded to connectors 111. In some embodiments, the first IC die structure 101 may be formed using the method described below with reference to fig. 20A and 20B, and then a detailed description of the first IC die structure 101 is provided.

The second IC die structure 103 includes a die stack 113 bonded to a base structure 115. In some embodiments, die stack 113 includes IC dies 117 bonded to each other in a pair-wise fashion₁To 117₄Such that the back side of one IC die of a pair is bonded to the front side of the other die of the pair. In addition, IC die 117 of die stack 113₁Is bonded to the base structure 115, and an IC die 117₄Is bonded to the back side of IC die 105. In some embodiments, IC die 117₁To 117₄May include logic die, memory die, CPU, GPU, xPU, MEMS die, SoC die, etc. In some embodiments, IC die 117 may be formed using the methods described below with reference to fig. 17A-17C, 18A, and 18B₁To 117₄And then providing the IC die 117₁To 117₄Detailed description of the drawings. The base structure 115 may include a semiconductor material, an insulating material, combinations thereof, and the like. In some embodiments, base structure 115 may include and IC dies 105 and 117₁To 117₄The substrate of (a) is of the same material. In such an embodiment, base structure 115 and IC dies 105 and 117₁To 117₄May have substantially similar Coefficients of Thermal Expansion (CTE), which may prevent damage to IC package 100 due to CTE mismatch. In some embodiments, base structure 115 may not include active and/or passive devices located on or in base structure 115. In some embodiments, IC die 117₁To 117₄Are respectively sealed in the sealing agent 123₁To 123₄In (1). In some embodiments, encapsulant 123₁To 123₄May comprise a suitable insulating material. In some embodiments, encapsulant 123₁To 123₄May comprise the same material. In other embodiments, encapsulant 123₁To 123₄May comprise different materials. In some embodiments, die structure 103 further includes stacked dummy structures 119, such that die stack 113 is interposed between adjacent stacked dummy structures 119. In some embodiments, each stacked dummy structure 119 comprises a dummy structure stackPart 121₁To 121₄Thereby making the sealant 123₁To 123₄Respectively interposed between the dummy structures 121₁To 121₄And IC die 117₁To 117₄In the meantime. Dummy structure 121₁To 121₄May include semiconductor materials, insulating materials, combinations thereof, and the like. In some embodiments, dummy structures 121₁To 121₄May include and IC die 105 and 117₁To 117₄The substrate of (a) is of the same material. In such an embodiment, dummy structures 121₁To 121₄And IC dies 105 and 117₁To 117₄May have substantially similar CTEs, which may prevent damage to IC package 100 due to CTE mismatch. In some embodiments, dummy structures 121₁To 121₄Active and/or passive devices may not be included and no additional electrical functionality may be provided to IC package 100. In some embodiments, stacked active structure 119 may be configured as a heat dissipation structure that transfers heat from IC die 105 of first IC die structure 101. Accordingly, the stacked dummy structure 119 may also be referred to as a heat dissipation structure 119.

With further reference to fig. 1A and 1B, the stacked dummy structure 119 and base structure 115 may have a rectangular shape in a top view. In some embodiments, three sidewalls of each stacked dummy structure 119 are substantially coplanar with corresponding three sidewalls of the base structure 115 such that a first width of the stacked dummy structure 119 is substantially equal to the first width W1 of the base structure 115 and the second width W2 of the base structure 115 is greater than the second width W3 of the stacked dummy structure 119. In some embodiments, the width W1 may be between about 5mm and about 10 mm. In some embodiments, the width W2 may be between about 7mm and about 15 mm. In some embodiments, the width W3 may be between about 1mm and about 4 mm. In some embodiments, the ratio W1/W2 may be between about 0.6 and about 0.7. In some embodiments, the ratio W1/W3 may be between about 2.5 and about 5. In some embodiments, the ratio W2/W3 may be between about 3.75 and about 7.

In the embodiment shown in fig. 1A and 1B, the first IC die structure 101 includes a single IC die (such as an IC)Die 105), and the second IC die structure 103 includes a single die stack (such as die stack 113) including four IC dies (such as IC die 117) and two dummy structures (such as stacked dummy structure 119)₁To 117₄) And each dummy structure includes a stack of four dummy structures (such as dummy structure 121)₁To 121₄). In other embodiments, the first IC die structure 101 may include more than one IC die and the second IC die structure 103 may include more than one die stack including more or less than four IC dies and more or less than two dummy structures including more or less than four dummy structures, depending on the design requirements of the IC package 100. In some embodiments, the IC package 100 may be formed using the method described below with reference to fig. 21A through 21H, and then a detailed description of the IC package 100 is provided.

Fig. 2A and 2B illustrate top and cross-sectional views of an IC package 200 according to some embodiments. Fig. 2A shows a top view, and fig. 2B shows a cross-sectional view along the line BB' in fig. 2A. In order to highlight the difference between the IC package 200 and the IC package 100 (see fig. 1A and 1B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, the IC package 200 includes a first IC die structure 101 bonded to a second IC die structure 201. In some embodiments, the first IC die structure 101 is electrically connected to the second IC die structure 201. The second IC die structure 201 includes a die stack 113 bonded to a base structure 115. In some embodiments, die stack 113 includes encapsulant 123 respectively encapsulated therein₁To 123₄IC die 117 of (a)₁To 117₄. In some embodiments, the second die structure 201 further includes stacked dummy structures 203 such that the die stack 113 is interposed between adjacent stacked dummy structures 203. In some embodiments, each stacked dummy structure 203 includes a dummy structure 205₁To 205₄So that the sealant 123 is stacked₁To 123₄Respectively between dummy structures 205₁To 205₄And IC die 117₁To 117₄In the meantime. In some embodiments, dummy structures 121 similar to those described above with reference to fig. 1A and 1B may be used₁To 121₄Similar materials and methods are used to form dummy structure 205₁To 205₄And the description is not repeated here. In some embodiments, stacked dummy structure 203 may be configured as a heat dissipation structure that transfers heat from IC die 105 of first IC die structure 101. Accordingly, the stacked dummy structure 203 may also be referred to as a heat dissipation structure 203.

With further reference to fig. 2A and 2B, the stacked dummy structures 203 and base structures 115 may have a rectangular shape in a top view. In some embodiments, both sidewalls of each stacked dummy structure 203 are substantially coplanar with respective two sidewalls of base structure 115. In some embodiments, the first width W4 of the stacked dummy structure 203 is less than the first width W1 of the base structure 115, and the second width W5 of the stacked dummy structure 203 is less than the second width W2 of the base structure 115. In some embodiments, the width W4 may be between about 4.0mm and about 9.5 mm. In some embodiments, the width W5 may be between about 1mm and about 4 mm. In some embodiments, the ratio W1/W4 may be between about 1.05 and about 1.25. In some embodiments, the ratio W1/W5 may be between about 2.5 and about 5. In some embodiments, the ratio W2/W4 may be between about 1.5 and about 1.75. In some embodiments, the ratio W2/W5 may be between about 3.75 and about 7. In some embodiments, the ratio W4/W5 may be between about 2.5 and about 5. In some embodiments, the IC package 200 may be formed using the method described below with reference to fig. 21A to 21H, and then a detailed description of the IC package 200 is provided.

Fig. 3A and 3B illustrate top and cross-sectional views of an IC package 300 according to some embodiments. Fig. 3A shows a top view, and fig. 3B shows a cross-sectional view along the line BB' in fig. 3A. In order to highlight the difference between the IC package 300 and the IC package 100 (see fig. 1A and 1B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 300 includes a bond to a second IC dieA first IC die structure 101 of structure 301. In some embodiments, the first IC die structure 101 is electrically connected to the second IC die structure 301. The second IC die structure 301 includes a die stack 113 bonded to a base structure 115. In some embodiments, die stack 113 includes encapsulant 123 respectively encapsulated therein₁To 123₄IC die 117 of (a)₁To 117₄. In some embodiments, die structure 301 further includes stacked dummy structures 303, such that die stack 113 is interposed between adjacent stacked dummy structures 303. In some embodiments, each stacked dummy structure 303 includes a dummy structure 305₁To 305₄So that the sealant 123 is stacked₁To 123₄Respectively between dummy structures 305₁To 305₄And IC die 117₁To 117₄In the meantime. In some embodiments, dummy structures 121 similar to those described above with reference to fig. 1A and 1B may be used₁To 121₄Similar materials and methods are used to form dummy structure 305₁To 305₄And the description is not repeated here. In some embodiments, stacked dummy structures 303 may be configured as heat dissipation structures that transfer heat from IC dies 105 of first IC die structure 101. Accordingly, the stacked dummy structures 303 may also be referred to as heat dissipation structures 303.

With further reference to fig. 3A and 3B, the stacked dummy structures 303 and base structures 115 may have a rectangular shape in a top view. In some embodiments, the sidewalls of each stacked dummy structure 303 are substantially coplanar with the corresponding sidewalls of the base structure 115. In some embodiments, the first width W6 of the stacked dummy structure 303 is less than the first width W1 of the base structure 115, and the second width W7 of the stacked dummy structure 303 is less than the second width W2 of the base structure 115. In some embodiments, the width W6 may be between about 3mm and about 9 mm. In some embodiments, the width W7 may be between about 1mm and about 4 mm. In some embodiments, the ratio W1/W6 may be between about 1.1 and about 1.6. In some embodiments, the ratio W1/W7 may be between about 2.5 and about 5. In some embodiments, the ratio W2/W6 may be between about 1.6 and about 2.3. In some embodiments, the ratio W2/W7 may be between about 3.75 and about 7.0. In some embodiments, the ratio W6/W7 may be between about 2.25 and about 3. In some embodiments, the IC package 300 may be formed using the method described below with reference to fig. 21A through 21H, and then a detailed description of the IC package 300 is provided.

Fig. 4A and 4B illustrate top and cross-sectional views of an IC package 400 according to some embodiments. Fig. 4A shows a top view, and fig. 4B shows a cross-sectional view along the line BB' in fig. 4A. In order to highlight the difference between the IC package 400 and the IC package 100 (see fig. 1A and 1B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 400 includes first IC die structure 101 bonded to second IC die structure 401. In some embodiments, the first IC die structure 101 is electrically connected to the second IC die structure 401. The second IC die structure 401 includes a die stack 113 bonded to a base structure 115. In some embodiments, die stack 113 includes encapsulant 123 respectively encapsulated therein₁To 123₄IC die 117 of (a)₁To 117₄. In some embodiments, the second IC die structure 401 further includes stacked dummy structures 403 such that the die stack 113 is interposed between adjacent stacked dummy structures 403. In some embodiments, each stacked dummy structure 403 includes a dummy structure 405₁To 405₄So that the sealant 123 is stacked₁To 123₄Respectively interposed between dummy structures 405₁To 405₄And IC die 117₁To 117₄In the meantime. In some embodiments, dummy structures 121 similar to those described above with reference to fig. 1A and 1B may be used₁To 121₄Similar materials and methods are used to form dummy structure 405₁To 405₄And the description is not repeated here. In some embodiments, stacked dummy structures 403 may be configured as heat dissipation structures that transfer heat from IC die 105 of first IC die structure 101. Accordingly, the stacked dummy structures 403 may also be referred to as heat dissipation structures 403.

With further reference to fig. 4A and 4B, the stacked dummy structures 403 and base structure 115 may have a rectangular shape in a top viewAnd (4) shape. In some embodiments, both sidewalls of each stacked dummy structure 403 are substantially coplanar with respective two sidewalls of the base structure 115. In some embodiments, stacked dummy structures 403 (such as stacked dummy structures 403) disposed at opposite corners of base structure 115₁And 403₂) With different dimensions. In some embodiments, stacked dummy structures 403₁Is smaller than the first width W1 of the base structure 115. In some embodiments, stacked dummy structures 403₂First width W of₈Less than the first width W1 of the base structure 115. In some embodiments, width W8 is different from width W9. In other embodiments, the width W8 may be substantially equal to the width W9. In some embodiments, stacked dummy structures 403₁May be equal to the stacked dummy structures 403₂And may be equal to width W10. In some embodiments, the width W10 is less than the second width W2 of the base structure 115. In some embodiments, the sum of widths W8 and W9 is less than width W1. The width W8 may be between about 2mm and about 4.5 mm. In some embodiments, the width W9 may be between about 2mm and about 4.5 mm. In some embodiments, the width W10 may be between about 1mm and about 4 mm. In some embodiments, the ratio W1/W8 may be between about 2 and about 2.5. In some embodiments, the ratio W1/W9 may be between about 2 and about 2.5. In some embodiments, the ratio W1/W10 may be between about 2.5 and about 5. In some embodiments, the ratio W2/W8 may be between about 3 and about 3.5. In some embodiments, the ratio W2/W9 may be between about 3 and about 3.5. In some embodiments, the ratio W2/W10 may be between about 3.75 and about 7. In some embodiments, the ratio W8/W9 may be between about 1 and about 2.5. In some embodiments, the ratio W8/W10 may be between about 1 and about 2. In some embodiments, the ratio W9/W10 may be between about 1 and about 2. In some embodiments, the IC package 400 may be formed using the method described below with reference to fig. 21A through 21H, and a detailed description of the IC package 400 is provided at that time.

Fig. 5A and 5B illustrate top and cross-sectional views of an IC package 500 according to some embodiments. FIG. 5A showsA top view is shown and fig. 5B shows a cross-sectional view along line BB' in fig. 5A. In order to highlight the difference between the IC package 500 and the IC package 100 (see fig. 1A and 1B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, the IC package 500 includes a first IC die structure 501 bonded to a second IC die structure 503. In some embodiments, the first IC die structure 501 is electrically connected to the second IC die structure 503. In some embodiments, the first IC die structure 501 is similar to the first IC die structure 101 (see fig. 1A and 1B) except that the first IC die structure 501 and the first IC die structure 101 have different backside structures. In some embodiments, the IC die structure 501 may be formed using the method described below with reference to fig. 19A-19G, and a detailed description of the IC die 501 is then provided. In some embodiments, the second IC die structure 503 is similar to the second IC die structure 103 (see fig. 1A and 1B) except for including the die stack 113, the stacked dummy structure 119, and the encapsulant 123₁To 123₄Is vertically flipped so that IC die 117 of die stack 113 is formed₄Back side of (a) and dummy structures 121 of stacked dummy structures 119₄Are bonded to base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, the IC package 500 may be formed using the method described below with reference to fig. 22A-22D, and a detailed description of the IC package 500 is then provided.

Fig. 6A and 6B illustrate top and cross-sectional views of an IC package 600 according to some embodiments. Fig. 6A shows a top view, and fig. 6B shows a cross-sectional view along the line BB' in fig. 6A. In order to highlight the difference between the IC package 600 and the IC package 200 (see fig. 2A and 2B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, the IC package 600 includes a first IC die structure 501 bonded to a second IC die structure 601. In some embodiments, the first IC die structure 501 is electrically connected to the second IC die structure 601. In some embodiments, the first IC die structure 501 is in contact with the first IC dieThe IC die structure 101 (see fig. 2A and 2B) is similar, except that the first IC die structure 501 and the first IC die structure 101 have different backside structures. In some embodiments, the IC die structure 501 may be formed using the method described below with reference to fig. 19A-19G, and a detailed description of the IC die 501 is then provided. In some embodiments, the second IC die structure 601 is similar to the second IC die structure 201 (see fig. 2A and 2B) except for including the die stack 113, the stacked dummy structure 203, and the encapsulant 123₁To 123₄Is vertically flipped so that IC die 117 of die stack 113 is formed₄Back side of (a) and dummy structures 205 of stacked dummy structures 203₄Are bonded to base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, the IC package 600 may be formed using the method described below with reference to fig. 22A-22D, and a detailed description of the IC package 600 is then provided.

Fig. 7A and 7B illustrate top and cross-sectional views of an IC package 700 according to some embodiments. Fig. 7A shows a top view, and fig. 7B shows a cross-sectional view along the line BB' in fig. 7A. In order to highlight the differences between the IC package 700 and the IC package 300 (see fig. 3A and 3B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, the IC package 700 includes a first IC die structure 501 bonded to a second IC die structure 701. In some embodiments, the first IC die structure 501 is electrically connected to the second IC die structure 701. In some embodiments, the first IC die structure 501 is similar to the first IC die structure 101 (see fig. 3A and 3B) except that the first IC die structure 501 and the first IC die structure 101 have different backside structures. In some embodiments, the IC die structure 501 may be formed using the method described below with reference to fig. 19A-19G, and a detailed description of the IC die 501 is then provided. In some embodiments, second IC die structure 701 is similar to second IC die structure 301 (see fig. 3A and 3B) except for including die stack 113, stacked dummy structures 303, and encapsulant 123₁To 123₄Structural quiltVertically flipped over so that IC die 117 of die stack 113₄Back side of (3) and dummy structures 305 of stacked dummy structures 303₄Are bonded to base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, the IC package 700 may be formed using the method described below with reference to fig. 22A-22D, and a detailed description of the IC package 700 is then provided.

Fig. 8A and 8B illustrate top and cross-sectional views of an IC package 800 according to some embodiments. Fig. 8A shows a top view, and fig. 8B shows a cross-sectional view along the line BB' in fig. 8A. In order to highlight the differences between IC package 800 and IC package 400 (see fig. 4A and 4B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, the IC package 800 includes a first IC die structure 501 bonded to a second IC die structure 801. In some embodiments, the first IC die structure 501 is electrically connected to the second IC die structure 801. In some embodiments, the first IC die structure 501 is similar to the first IC die structure 101 (see fig. 4A and 4B) except that the first IC die structure 501 and the first IC die structure 101 have different backside structures. In some embodiments, the IC die structure 501 may be formed using the method described below with reference to fig. 19A-19G, and a detailed description of the IC die 501 is then provided. In some embodiments, the second IC die structure 801 is similar to the second IC die structure 401 (see fig. 4A and 4B) except for including the die stack 113, the stacked dummy structures 403, and the encapsulant 123₁To 123₄Is vertically flipped so that IC die 117 of die stack 113 is formed₄Back side of (1) and dummy structures 405 of stacked dummy structures 403₄Are bonded to base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, the IC package 800 may be formed using the methods described below with reference to fig. 22A-22D, and a detailed description of the IC package 800 is then provided.

Fig. 9A and 9B illustrate top and cross-sectional views of an IC package 900 according to some embodiments. Fig. 9A shows a top view, and fig. 9B shows a cross-sectional view along the line BB' in fig. 9A. In order to highlight the differences between the IC package 900 and the IC package 100 (see fig. 1A and 1B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 900 includes a first IC die structure 901 bonded to a second IC die structure 903. In some embodiments, first IC die structure 901 is electrically connected to second IC die structure 903. In some embodiments, first IC die structure 901 is similar to first IC die structure 101 (see fig. 1A and 1B) except that IC die 105 is encapsulated only in encapsulant 107 and encapsulant 109 is omitted. In some embodiments, IC die structure 901 may be formed using the method described below with reference to fig. 20A and 20B, and a detailed description of IC die structure 901 is then provided.

Second IC die structure 903 includes die stack 113 bonded to base structure 115. In some embodiments, die stack 113 includes encapsulant 123 respectively encapsulated therein₁To 123₄IC die 117 of (a)₁To 117₄. In some embodiments, second IC die structure 903 further includes encapsulant base structure 115, die stack 113, and encapsulant 123₁To 123₄The sealant 907. In some embodiments, encapsulant 907 may include a suitable insulating material. In some embodiments, encapsulant 907 and encapsulant 123₁To 123₄May comprise the same material. In other embodiments, encapsulant 907 and encapsulant 123₁To 123₄May comprise different materials. In some embodiments, second IC die structure 903 further includes dummy structures 905 such that die stack 113 is interposed between adjacent dummy structures 905. In some embodiments, the dummy structures 121 described above with reference to fig. 1A and 1B may be used₁To 121₄Similar materials and methods form dummy structure 905 and are not repeated here. In some embodiments, dummy structure 905 may be configured as a heat dissipation structure that transfers heat from IC die 105 of first IC die structure 901. Accordingly, the dummy structure 905 may also be referred to as a heat dissipation structure 905。

With further reference to fig. 9A and 9B, dummy structure 905 and second IC die structure 903 may have a rectangular shape in a top view. In some embodiments, three sidewalls of each dummy structure 905 are substantially coplanar with corresponding three sidewalls of the second IC die structure 903. In some embodiments, the first width of dummy structure 905 is substantially equal to first width W11 of second IC die structure 903, and the second width W13 of dummy structure 905 is less than second width W12 of second IC die structure 903. In some embodiments, the width W11 may be between about 5mm and about 10 mm. In some embodiments, the width W12 may be between about 7mm and about 15 mm. In some embodiments, the width W13 may be between about 1mm and about 4 mm. In some embodiments, the ratio W11/W12 may be between about 0.6 and about 0.7. In some embodiments, the ratio W11/W13 may be between about 2.5 and about 5. In some embodiments, the ratio W12/W13 may be between about 3.75 and about 7. In some embodiments, the IC package 900 may be formed using the method described below with reference to fig. 23A-23F, and a detailed description of the IC package 900 is then provided.

Fig. 10A and 10B illustrate top and cross-sectional views of an IC package 1000 according to some embodiments. Fig. 10A shows a top view, and fig. 10B shows a cross-sectional view along the line BB' in fig. 10A. In order to highlight the difference between the IC package 1000 and the IC package 900 (see fig. 9A and 9B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 1000 includes a first IC die structure 901 bonded to a second IC die structure 1001. In some embodiments, first IC die structure 901 is electrically connected to second IC die structure 1001.

In some embodiments, the second IC die structure 1001 includes a die stack 113 bonded to a base structure 115. In some embodiments, die stack 113 includes encapsulant 123 respectively encapsulated therein₁To 123₄IC die 117 of (a)₁To 117₄. In some embodiments, second IC die structure 1001 further includes encapsulation base structure 115, die stack 113, and encapsulant 123₁To 123₄The sealant 907. In some embodiments, the second IC die structure 1001 further includes dummy structures 1003 such that the die stack 113 is interposed between adjacent dummy structures 1003. In some embodiments, dummy structure 1003 may be formed using materials and methods similar to dummy structure 905 described above with reference to fig. 9A and 9B, and the description is not repeated here. In some embodiments, dummy structure 1003 may be configured as a heat dissipation structure that transfers heat from IC die 105 of first IC die structure 901. Accordingly, the dummy structure 1003 may also be referred to as a heat dissipation structure 1003.

With further reference to fig. 10A and 10B, the dummy structure 1003 and the second IC die structure 1001 may have a rectangular shape in a top view. In some embodiments, two sidewalls of each dummy structure 1003 are substantially coplanar with corresponding two sidewalls of the second IC die structure 1001. In some embodiments, the first width W14 of the dummy structure 1003 is less than the first width W11 of the second IC die structure 1001, and the second width W15 of the dummy structure 1003 is less than the second width W12 of the second IC die structure 1001. In some embodiments, the width W14 may be between about 4mm and about 9.5 mm. In some embodiments, the width W15 may be between about 1mm and about 4 mm. In some embodiments, the ratio W11/W14 may be between about 1.05 and about 1.25. In some embodiments, the ratio W11/W15 may be between about 2.5 and about 5. In some embodiments, the ratio W12/W14 may be between about 1.5 and about 1.75. In some embodiments, the ratio W12/W15 may be between about 3.75 and about 7. In some embodiments, the ratio W14/W15 may be between about 2.5 and about 5. In some embodiments, the IC package 1000 may be formed using the method described below with reference to fig. 23A through 23F, and a detailed description of the IC package 1000 is then provided.

Fig. 11A and 11B illustrate top and cross-sectional views of an IC package 1100 according to some embodiments. Fig. 11A shows a top view, and fig. 11B shows a cross-sectional view along the line BB' in fig. 11A. In order to highlight the differences between the IC package 1100 and the IC package 900 (see fig. 9A and 9B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 1100 includes a first IC die structure 901 bonded to a second IC die structure 1101. In some embodiments, first IC die structure 901 is electrically connected to second IC die structure 1101.

In some embodiments, second IC die structure 1101 includes a die stack 113 bonded to a base structure 115. In some embodiments, die stack 113 includes encapsulant 123 respectively encapsulated therein₁To 123₄IC die 117 of (a)₁To 117₄. In some embodiments, second IC die structure 1101 further includes an encapsulant base structure 115, a die stack 113, and an encapsulant 123₁To 123₄The sealant 907. In some embodiments, second IC die structure 1101 further includes dummy structures 1103, such that die stack 113 is interposed between adjacent dummy structures 1103. In some embodiments, dummy structure 1103 may be formed using materials and methods similar to dummy structure 905 described above with reference to fig. 9A and 9B, and the description is not repeated here. In some embodiments, dummy structure 1103 may be configured as a heat dissipation structure that transfers heat from IC die 105 of first IC die structure 901. Accordingly, the dummy structure 1103 may also be referred to as a heat dissipation structure 1103.

With further reference to fig. 11A and 11B, dummy structure 1103 and second IC die structure 1101 may have a rectangular shape in a top view. In some embodiments, the sidewalls of each dummy structure 1103 are substantially coplanar with the corresponding sidewalls of second IC die structure 1101. In some embodiments, first width W16 of dummy structure 1103 is less than first width W11 of second IC die structure 1101, and second width W17 of dummy structure 1103 is less than second width W12 of second IC die structure 1101. In some embodiments, the width W16 may be between about 3mm and about 9 mm. In some embodiments, the width W17 may be between about 1mm and about 4 mm. In some embodiments, the ratio W11/W16 may be between about 1.1 and about 1.6. In some embodiments, the ratio W11/W17 may be between about 2.5 and about 5. In some embodiments, the ratio W12/W16 may be between about 1.6 and about 2.3. In some embodiments, the ratio W12/W17 may be between about 3.75 and about 7. In some embodiments, the ratio W16/W17 may be between about 2.25 and about 3. In some embodiments, the IC package 1100 may be formed using the method described below with reference to fig. 23A-23F, and a detailed description of the IC package 1100 is then provided.

Fig. 12A and 12B illustrate top and cross-sectional views of an IC package 1200 according to some embodiments. Fig. 12A shows a top view, and fig. 12B shows a cross-sectional view along the line BB' in fig. 12A. In order to highlight the differences between the IC package 1200 and the IC package 900 (see fig. 9A and 9B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 1200 includes a first IC die structure 901 bonded to a second IC die structure 1201. In some embodiments, first IC die structure 901 is electrically connected to second IC die structure 1201.

In some embodiments, second IC die structure 1201 includes die stack 113 bonded to base structure 115. In some embodiments, die stack 113 includes encapsulant 123 respectively encapsulated therein₁To 123₄IC die 117 of (a)₁To 117₄. In some embodiments, second IC die structure 1201 further includes encapsulation base structure 115, die stack 113, and encapsulant 123₁To 123₄The sealant 907. In some embodiments, the second IC die structure 1201 also includes dummy structures 1203, such that the die stack 113 is interposed between adjacent dummy structures 1203. In some embodiments, dummy structure 1203 may be formed using materials and methods similar to dummy structure 905 described above with reference to fig. 9A and 9B, and the description is not repeated here. In some embodiments, dummy structure 1203 may be configured as a heat dissipation structure that transfers heat from IC die 105 of first IC die structure 901. Accordingly, the dummy structure 1203 may also be referred to as a heat dissipation structure 1203.

With further reference to fig. 12A and 12B, dummy structure 1203 and second IC die structure 1201 may have a rectangular shape in a top view. In some embodiments, two sidewalls of each dummy structure 1203 are substantially coplanar with respective two sidewalls of second IC die structure 1201. In some embodiments, disposed opposite second IC die 1201Dummy structures 1203 at corners (such as dummy structures 1203)₁And 1203₂) With different dimensions. In some embodiments, dummy structure 1203₁Is less than the first width W11 of the second IC die structure 1201. In some embodiments, dummy structure 1203₂Is less than the first width W11 of the second IC die structure 1201. In some embodiments, width W18 is different from width W19. In other embodiments, the width W18 may be substantially equal to the width W19. In some embodiments, dummy stack 1203₁May be equal to dummy stack 1203₂And may be equal to W20. In some embodiments, width W20 is less than second width W12 of second IC die structure 1201. In some embodiments, the sum of widths W18 and W19 is less than width W11. In some embodiments, the width W18 may be between about 2mm and about 4.5 mm. In some embodiments, the width W19 may be between about 2mm and about 4.5 mm. In some embodiments, the width W20 may be between about 1mm and about 4 mm. In some embodiments, the ratio W11/W18 may be between about 2 and about 2.5. In some embodiments, the ratio W11/W19 may be between about 2 and about 2.5. In some embodiments, the ratio W11/W20 may be between about 2.5 and about 5. In some embodiments, the ratio W12/W18 may be between about 3 and about 3.5. In some embodiments, the ratio W12/W19 may be between about 3 and about 3.5. In some embodiments, the ratio W12/W20 may be between about 3.75 and about 7. In some embodiments, the ratio W18/W19 may be between about 1 and about 2.5. In some embodiments, the ratio W18/W20 may be between about 1 and about 2. In some embodiments, the ratio W19/W20 may be between about 1 and about 2. In some embodiments, the IC package 1200 may be formed using the method described below with reference to fig. 23A-23F, and a detailed description of the IC package 1200 is provided at that time.

Fig. 13A and 13B illustrate top and cross-sectional views of an IC package 1300 according to some embodiments. Fig. 13A shows a top view, and fig. 13B shows a cross-sectional view along the line BB' in fig. 13A. To highlight the differences between IC package 1300 and IC package 900 (see fig. 9A and 9B), theseCommon parts of the package are denoted by the same reference numerals and their description is not repeated here. In some embodiments, IC package 1300 includes a first IC die structure 1301 bonded to a second IC die structure 1303. In some embodiments, first IC die structure 1301 is electrically connected to second IC die structure 1303. In some embodiments, first IC die structure 1301 is similar to first IC die structure 901 (see fig. 9A and 9B), except that first IC die structure 1301 and first IC die structure 901 have different backside structures. In some embodiments, the first IC die structure 1301 may be formed using the methods described below with reference to fig. 19A-19G, and a detailed description of the first IC die 1301 is provided at that time. In some embodiments, second IC die structure 1303 is similar to second IC die structure 903 (see fig. 9A and 9B) except for including die stack 113 and encapsulant 123₁To 123₄Is vertically flipped so that IC die 117 of die stack 113 is formed₄Is bonded to the base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, the IC package 1300 may be formed using the method described below with reference to fig. 24A-24C, and a detailed description of the IC package 1300 is then provided.

Fig. 14A and 14B illustrate top and cross-sectional views of an IC package 1400 according to some embodiments. Fig. 14A shows a top view, and fig. 14B shows a cross-sectional view along the line BB' in fig. 14A. In order to highlight the difference between the IC package 1400 and the IC package 1000 (see fig. 10A and 10B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, the IC package 1400 includes a first IC die structure 1301 bonded to a second IC die structure 1401. In some embodiments, the first IC die structure 1301 is electrically connected to the second IC die structure 1401. In some embodiments, first IC die structure 1301 is similar to first IC die structure 901 (see fig. 10A and 10B), except that first IC die structure 1301 and first IC die structure 901 have different backside structures. In some embodiments, the following may be used with reference to fig. 19A-1919G forms a first IC die structure 1301 and at that time provides a detailed description of the first IC die 1301. In some embodiments, second IC die structure 1401 is similar to second IC die structure 1001 (see fig. 10A and 10B) except for including die stack 113 and encapsulant 123₁To 123₄Is vertically flipped so that IC die 117 of die stack 113 is formed₄Is bonded to the base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, the IC package 1400 may be formed using the method described below with reference to fig. 24A-24C, and a detailed description of the IC package 1400 is provided at that time.

Fig. 15A and 15B illustrate top and cross-sectional views of an IC package 1500 according to some embodiments. Fig. 15A shows a top view, and fig. 15B shows a cross-sectional view along the line BB' in fig. 15A. In order to highlight the difference between the IC package 1500 and the IC package 1100 (see fig. 11A and 11B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 1500 includes a first IC die structure 1301 bonded to a second IC die structure 1501. In some embodiments, first IC die structure 1301 is electrically connected to second IC die structure 1501. In some embodiments, first IC die structure 1301 is similar to first IC die structure 901 (see fig. 11A and 11B), except that first IC die structure 1301 and first IC die structure 901 have different backside structures. In some embodiments, the first IC die structure 1301 may be formed using the methods described below with reference to fig. 19A-19G, and a detailed description of the first IC die 1301 is provided at that time. In some embodiments, second IC die structure 1501 is similar to second IC die structure 1101 (see fig. 11A and 11B) except that it includes die stack 113 and encapsulant 123₁To 123₄Is vertically flipped so that IC die 117 of die stack 113 is formed₄Is bonded to the base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, a combination of the above methods may be usedThe method described below with reference to fig. 24A to 24C forms the IC package 1500, and then a detailed description of the IC package 1500 is provided.

Fig. 16A and 16B illustrate top and cross-sectional views of an IC package 1600 according to some embodiments. Fig. 16A shows a top view, and fig. 16B shows a cross-sectional view along the line BB' in fig. 16A. In order to highlight the differences between the IC package 1600 and the IC package 1200 (see fig. 12A and 12B), common components of these packages are denoted by the same reference numerals, and their descriptions are not repeated here. In some embodiments, IC package 1600 includes a first IC die structure 1301 bonded to a second IC die structure 1601. In some embodiments, first IC die structure 1301 is electrically connected to second IC die structure 1601. In some embodiments, first IC die structure 1301 is similar to first IC die structure 901 (see fig. 12A and 12B), except that first IC die structure 1301 and first IC die structure 901 have different backside structures. In some embodiments, the first IC die structure 1301 may be formed using the methods described below with reference to fig. 19A-19G, and a detailed description of the first IC die 1301 is provided at that time. In some embodiments, second IC die structure 1601 is similar to second IC die structure 1201 (see fig. 12A and 12B) except that it includes die stack 113 and encapsulant 123₁To 123₄Is vertically flipped so that IC die 117 of die stack 113 is formed₄Is bonded to the base structure 115. In addition, IC die 117 of die stack 113₁Is bonded to the back side of IC die 105. In some embodiments, the IC package 1600 may be formed using the methods described below with reference to fig. 24A-24C, and a detailed description of the IC package 1600 is then provided.

Fig. 17A-17C illustrate integrated circuit dies (such as, for example, IC dies 105 and 117 illustrated in fig. 1B-16B) in accordance with some embodiments₁) Cross-sectional views of various process steps during fabrication. Referring to fig. 17A, a portion of a wafer 1700 is shown with die regions 1701 separated by scribe lines 1703 (also referred to as scribe lines or streets). As described in more detail below, the wafer 1700 will be cut along scribe lines 1703 toA separate integrated circuit die (such as IC die 1719 shown in fig. 17C) is formed. In some embodiments, wafer 1700 includes a substrate 1705, one or more active and/or passive devices (not shown) located on substrate 1705, and an interconnect structure 1707 located over substrate 1705 and the one or more active and/or passive devices. In some embodiments, the substrate 1705 may be formed of silicon, but it may also be formed of other group III, group IV, and/or group V elements (such as silicon, germanium, gallium, arsenic, and combinations thereof). The substrate 1705 may also be in the form of a silicon-on-insulator (SOI). An SOI substrate may include a layer of semiconductor material (e.g., silicon, germanium, etc.) formed over an insulating layer (e.g., buried oxide, etc.) formed on a silicon substrate. In addition, other substrates that may be used include multilayer substrates, gradient substrates, hybrid orientation substrates, any combination thereof, and the like.

In some embodiments, the substrate 1705 may include a via (TV)1709 extending from the front side of the substrate 1705 towards the back side of the substrate 1705. In some embodiments, the TV 1709 may be formed by forming an opening in the substrate 1705 and filling the opening with a suitable conductive material. In some embodiments, the openings may be formed using suitable photolithography and etching processes. In some embodiments, the openings can be filled with copper, copper alloys, silver, gold, tungsten, tantalum, aluminum, combinations thereof, or the like using Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electrochemical plating, electroless plating, combinations thereof, or the like. In some embodiments, a liner layer and/or an adhesion/barrier layer may be formed in the opening prior to filling the opening with a suitable conductive material. In some embodiments, a planarization process may be performed on the conductive material of the TV 1709 such that the topmost surface of the TV 1709 is substantially flush or coplanar with the front surface of the substrate 1705. The planarization process may include a CMP process, a grinding process, an etching process, combinations thereof, and the like.

In some embodiments, the one or more active and/or passive devices may include respective n-type metal oxide semiconductor (NMOS) and/or p-type metal oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like.

The interconnect structure 1707 may include a plurality of dielectric layers 1711, such as inter-layer dielectric (ILD)/inter-metal dielectric (IMD), and interconnects 1713, such as conductive lines and vias, within the dielectric layers 1711. For example, the dielectric layer 1711 may be formed from a low-K dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), FSG, SiOxCy, spin-on glass, spin-on polymers, silicon carbon materials, compounds thereof, composites thereof, combinations thereof, and the like, by any suitable method known in the art, such as spin-on methods, Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), combinations thereof, and the like. In some embodiments, the interconnects 1713 may be formed in the dielectric layer 1711 using, for example, a damascene process, a dual damascene process, combinations thereof, and the like. In some embodiments, the interconnects 1713 may include copper, copper alloys, silver, gold, tungsten, tantalum, aluminum, combinations thereof, and the like. In some embodiments, the interconnects 1713 may provide electrical connections between one or more active and/or passive devices formed on the substrate 1705.

With further reference to fig. 17A, contact pads 1715 are formed over the interconnect structure 1707. The contact pads 1715 may be electrically connected to one or more active and/or passive devices through interconnects 1713. In some embodiments, the contact pads 1715 may include a conductive material, such as aluminum, copper, tungsten, silver, gold, combinations thereof, and the like. In some embodiments, a conductive material may be formed over the interconnect structure 1707 using, for example, PVD, ALD, electrochemical plating, electroless plating, combinations thereof, and the like. Subsequently, the conductive material is patterned to form contact pads 1715. In some embodiments, the conductive material may be patterned using suitable photolithography and etching methods.

Referring to fig. 17B, an insulating layer 1717 is formed over the interconnect structure 1707 and the contact pad 1715. In some embodiments, insulating layer 1717 may include one or more layers of non-photopatternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), combinations thereof, and the like, and may be formed using CVD, PVD, ALD, spin-on processes, combinations thereof, and the like. In other embodiments, the insulating layer 1717 may include one or more layers of a photo-patternable insulating material such as Polybenzoxazole (PBO), Polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, and may be formed using a spin coating process or the like. Such photo-patternable insulating material can be patterned using a similar photolithographic method as the photoresist material. In some embodiments, the insulating layer 1717 is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like.

Referring to fig. 17C, the wafer 1700 is singulated along scribe lines 1703 (see fig. 17B) to form individual IC dies 1719. In some embodiments, the wafer 1700 may be singulated into individual IC die 1719, for example, by sawing, laser ablation, etching, combinations thereof, and the like.

Fig. 18A-18B illustrate an IC die (such as, for example, IC die 117 shown in fig. 1B-16B) in accordance with some embodiments₂To 117₄) Cross-sectional views of various process steps during fabrication. Fig. 18A illustrates wafer 1800 after various process steps are performed on wafer 1700, shown in fig. 17B, in accordance with some embodiments. In some embodiments, an insulating layer 1801 is formed over the insulating layer 1717. In some embodiments, the insulating layer 1801 can be formed using materials and methods similar to the insulating layer 1717 described above with reference to fig. 17B, and the description is not repeated here. In some embodiments, the insulating layer 1801 is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, the insulating layer 1801 and the insulating layer 1717 can comprise the same material. In other embodiments, the insulating layer 1801 and the insulating layer 1717 can comprise different materials.

With further reference to fig. 18A, bond pads 1805 and corresponding vias 1803 are formed in insulating layers 1717 and 1801. In some embodiments, bond pads 1805 are formed in insulating layer 1801 and vias 1803 are formed in insulating layer 1717. In some embodiments, the bond pads 1805 and vias 1803 may be formed using similar materials and methods as the interconnects 1713 described above with reference to fig. 17A, and the description is not repeated here. In some embodiments, the bond pad 1805 and insulating layer 1801 are planarized such that a topmost surface of the bond pad 1805 is substantially flush or coplanar with a topmost surface of the insulating layer 1801. In some embodiments, the vias 1803 are in direct electrical contact with the interconnects 1713. In other embodiments, the vias 1803 may be in direct electrical contact with the contact pads 1715 and may be electrically connected to the interconnects 1713 through the contact pads 1715.

Referring to fig. 18B, the wafer 1800 is singulated along scribe lines 1703 (see fig. 18A) to form individual IC dies 1807. In some embodiments, wafer 1800 may be singulated into individual IC dies 1807, for example, by sawing, laser ablation, etching, combinations thereof, and the like.

Fig. 19A-19G illustrate cross-sectional views of various process steps during fabrication of an integrated circuit die structure, such as, for example, IC die structures 501 and 1301 illustrated in fig. 5B-8B and 13B-16B, respectively, in accordance with some embodiments. Referring to fig. 19A, IC die 105 is bonded to carrier 1901 to begin forming wafer level die structure 1900. In some embodiments, carrier 1901 may comprise a material similar to substrate 1705 described above with reference to fig. 17A, and will not be described again here. In other embodiments, carrier 1901 may comprise a suitable insulating material. In some embodiments, IC die 105 may be similar to IC die 1719 and may be formed using the methods described above with reference to fig. 17A-17C, where like components of IC die 1719 and 105 are denoted with like reference numerals.

With further reference to fig. 19A, an insulating layer 1903 is formed over carrier 1901. In some embodiments, the insulating layer 1903 can be formed using materials and methods similar to the insulating layer 1717 described above with reference to fig. 17B, and the description is not repeated here. In some embodiments, the insulating layer 1903 is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, IC die 105 is bonded to carrier 1901 by bonding insulating layer 1717 of IC die 105 to insulating layer 1903. In some embodiments, the insulating layer 1717 can be bonded to the insulating layer 1903 using a direct bonding method, such as a fusion bonding method. In some embodiments, a surface treatment process can be performed on the insulating layer 1717 and the insulating layer 1903 before bonding the insulating layer 1717 to the insulating layer 1903. In other embodiments, the insulating layer 1717 can be bonded to the insulating layer 1903 using other suitable bonding methods or using an adhesive. In some embodiments, an annealing process may be performed after bonding IC die 105 to carrier 1901 to enhance bonding.

Referring to fig. 19B, an encapsulant 107 is formed over IC die 105 and around IC die 105. In some embodiments, the encapsulant 107 may be formed using materials and methods similar to the insulating layer 1717 described above with reference to fig. 17B, and the description is not repeated here. In other embodiments, encapsulant 107 may include a molding compound, such as an epoxy, a resin, a moldable polymer, combinations thereof, and the like. A substantially liquid molding compound may be applied and then cured by chemical reaction in, for example, an epoxy or resin. In other embodiments, the molding compound may be an Ultraviolet (UV) or thermally curable polymer applied as a gel or moldable solid that can be disposed around and between IC die 105.

Referring to fig. 19C, encapsulant 107 and IC die 105 are planarized such that back surface 105b of IC die 105 is substantially flush or coplanar with a topmost surface of encapsulant 107. In some embodiments, the planarization process may include a CMP process, a grinding process, an etching process, combinations thereof, and the like. In some embodiments, the planarization process exposes TV 1709 of IC die 105 such that the exposed surface of TV 1709 is substantially flush or coplanar with backside 105b of IC die 105 and the topmost surface of encapsulant 107.

Referring to fig. 19D, back side 105b of IC die 105 is recessed below the topmost surface of encapsulant 107 to form recess 1905. In some embodiments, back side 105b of IC die 105 may be recessed using a suitable etching process, such as a selective dry or wet etching process that is selective to the material of substrate 1705 of IC die 105. In some embodiments, sidewalls of TV 1709 of IC die 105 are exposed within recess 1905.

Referring to fig. 19E, an insulating layer 1907 is formed in the groove 1905 (see fig. 19D). In some embodiments, the insulating layer 1907 can be formed using materials and methods similar to the insulating layer 1717 described above with reference to fig. 17B, and the description is not repeated here. In some embodiments, the insulating material of insulating layer 1907 is deposited in recess 1905 and over encapsulant 107. Subsequently, portions of the insulating material overfilling the recesses 1905 are removed to form insulating layer 1907 such that the topmost surface of insulating layer 1907 is substantially flush or coplanar with the topmost surface of encapsulant 107. In some embodiments, a CMP process, a grinding process, an etching process, combinations thereof, and the like may be used to remove portions of the over-filled recess 1905 of the insulating material. In some embodiments, the removal process exposes TV 1709 of IC die 105 such that the exposed surface of TV 1709 is substantially flush or coplanar with the topmost surface of insulating layer 1907 and the topmost surface of encapsulant 107.

Referring to fig. 19F and 19G, wafer-level die structure 1900 is singulated to form individual (chip-level or die-level) IC die structures 1911, which are intermediate structures that form IC die structures 501 and 1301 (see fig. 5B-8B and 13B-16B, respectively), according to some embodiments. Referring first to fig. 19F, the encapsulant 107, insulating layer 1903, and carrier 1901 are patterned to form a recess 1909. Recesses 1909 are between adjacent IC dies 105 and extend partially into carrier 1901 such that recesses 1909 partially singulate carrier 1901. In some embodiments, the patterning process used to form the recess 1909 may include suitable photolithography and etching methods.

Referring to fig. 19G, carrier 1901 is thinned to remove the undivided portion of carrier 1901, thereby completely singulating carrier 1901 and forming individual IC die structures 1911. In some embodiments, carrier 1901 may be thinned using a CMP process, a grinding process, an etching process, combinations thereof, and the like. In other embodiments, the singulation process may include sawing, laser ablation, etching, combinations thereof, and the like.

Fig. 20A and 20B illustrate cross-sectional views of various process steps during fabrication of an integrated circuit die structure, such as, for example, IC die structures 101 and 901 illustrated in fig. 1B-4B and 9B-12B, respectively, in accordance with some embodiments. Fig. 20A illustrates the wafer-level die structure 2000 after various process steps are performed on the wafer-level die structure 1900 illustrated in fig. 19E, in accordance with some embodiments. In some embodiments, insulating layer 2001 is formed over IC die 105 and encapsulant 107. In some embodiments, the insulating layer 2001 can be formed using materials and methods similar to the insulating layer 1717 described above with reference to fig. 17B, and the description is not repeated here. In some embodiments, insulating layer 2001 and insulating layer 1907 can comprise the same material. In other embodiments, insulating layer 2001 and insulating layer 1907 can comprise different materials. In some embodiments, bond pads 2003 are formed in insulating layer 2001 in electrical contact with corresponding TVs 1709 of IC die 105. In some embodiments, the bond pads 2003 may be formed using similar materials and methods as the interconnects 1713 described above with reference to fig. 17A, and will not be described again here. In some embodiments, the bond pad 2003 is planarized such that the topmost surface of the bond pad 2003 is substantially flush or coplanar with the topmost surface of the insulating layer 2001. In some embodiments, the planarization process may include a CMP process, a grinding process, an etching process, combinations thereof, and the like.

Referring to fig. 20B, wafer-level die structure 2000 is singulated to form individual (chip-level or wafer-level) IC die structures 2005, which are intermediate structures in forming IC die structures 101 and 901 (see fig. 1B-4B and 9B-12B, respectively) according to some embodiments. In some embodiments, the wafer level die structure 2000 may be singulated using methods similar to those described above with reference to fig. 19F and 19G, and the description is not repeated here.

Fig. 21A-21H illustrate cross-sectional views of various process steps during fabrication of an integrated circuit die structure, such as, for example, the IC packages 100-400 illustrated in fig. 1A and 1B, fig. 2A and 2B, fig. 3A and 3B, and fig. 4A and 4B, respectively, according to some embodiments. Referring to fig. 21A, a method of forming a wafer-level die structure 2100 begins by forming an insulating layer 2103 over a carrier 2101. In some embodiments, carrier 2101 may be formed using materials and methods similar to carrier 1901 described above with reference to fig. 19A, and the description is not repeated here. In some embodiments, the insulating layer 2103 can be formed using similar materials and methods as the insulating layer 1903 described above with reference to fig. 19A, and hereThe description will not be repeated. In some embodiments, IC die 117₁Bonded to the insulating layer 2103. In some embodiments, IC die 117₁May be similar to IC die 1719 and may be formed using the methods described above with reference to fig. 17A-17C, where IC die 117₁Like components to 1719 are denoted by the same reference numerals.

In some embodiments, by bonding IC die 117₁Insulating layer 1717 to insulating layer 2103, bonding IC die 117 to₁Bonded to the insulating layer 2103. In some embodiments, the insulating layer 1717 can be bonded to the insulating layer 2103 using a direct bonding method, such as a fusion bonding method. In some embodiments, a surface treatment process can be performed on the insulating layer 1717 and the insulating layer 2103 before bonding the insulating layer 1717 to the insulating layer 2103. In other embodiments, the insulating layer 1717 can be bonded to the insulating layer 2103 with other suitable bonding methods or using an adhesive. In some embodiments, IC die 117 may be used in a semiconductor manufacturing process₁An annealing process is performed after bonding to the carrier 2101 to strengthen the bonding. In some embodiments, insulating layer 1717 and insulating layer 2103 can be the same material. In other embodiments, the insulating layer 1717 and the insulating layer 2103 can comprise different materials.

With further reference to FIG. 21A, a dummy structure 2105 is formed₁Bonded to insulating layer 2103 such that each IC die 117 is₁Dummy structures 2105 inserted adjacent to each other₁In the meantime. In some embodiments, dummy structure 2105₁May include an IC die 117₁The substrate 1705 of (a) is of the same material. In some embodiments, dummy structure 2105₁Active and/or passive devices may not be included and no additional electrical functionality may be provided to the resulting IC package. In some embodiments, each dummy structure 2105₁May include an insulating layer 2107₁. In some embodiments, the insulating layer 2107 can be formed using materials and methods similar to the insulating layer 1717 described above with reference to fig. 17B₁And the description is not repeated here. In some embodiments, insulating layer 2107₁And the insulating layer 2103 may comprise the same material. In other embodiments, the insulationLayer 2107₁And insulating layer 2103 may comprise different materials.

In some embodiments, by coupling dummy structure 2105₁Insulating layer 2107 of₁Bonding the dummy structure 2105 to the insulating layer 2103₁Bonded to the insulating layer 2103. In some embodiments, the insulating layer 2107 may be bonded using a direct bonding method, such as a fusion bonding method₁Bonded to the insulating layer 2103. In some embodiments, insulating layer 2107 is formed₁Insulating layer 2107 may be applied prior to bonding to insulating layer 2103₁And the insulating layer 2103 is subjected to a surface treatment process. In other embodiments, insulating layer 2107 may be bonded using other suitable bonding methods or using adhesives₁Bonded to the insulating layer 2103. In some embodiments, dummy structure 2105 may be used in the process₁An annealing process is performed after bonding to the carrier 2101 to strengthen the bonding.

Fig. 21B illustrates a top view of the wafer level die structure 2100 illustrated in fig. 21A, in accordance with some embodiments. In some embodiments, carrier 2101 is divided into die areas 2113 by scribe lines 2109 and 2111_i(where i 1.., N, where N is the total number of die regions). In some embodiments, score line 2109 is perpendicular to score line 2111. In such an embodiment, the die region 2113_i(where i ═ 1.., N) has a rectangular shape in a top view. In other embodiments, score line 2109 and score line 2111 form an angle other than 90 degrees. In such an embodiment, the die region 2113_i(where i ═ 1.., N) has the shape of a parallelogram in a top view. In some embodiments, dummy structure 2105₁Having a rectangular shape in top view. In some embodiments, dummy structure 2105₁Overlaps with the corresponding scribe line 2111, and thus the dummy structure 2105₁In die regions 2113 separated by respective scribe lines 2111_i(where i 1.., N) are shared between subsets. In some embodiments, dummy structure 2105₁Can be formed along the entire usable portion of carrier 2101 (such as including die area 2113)_iPortions of) such that each scribe 2111 is associated with a respective single continuous dummy structure 2105₁And (4) overlapping.As described in more detail below, the wafer-level die structure 2100 is singulated along scribe lines 2109 and 2111 to form individual packages. This segmentation process also segments the dummy structures 2105₁And form individual (chip-level or die-level) dummy structures for respective individual packages. In some embodiments, dummy structure 2105 is formed by overlapping scribe 2111₁The time for forming individual IC packages can be reduced. For example, the time to form individual IC packages prior to performing the singulation process may reduce the time required to place and bond individual (chip-level or die-level) dummy structures within each die region of carrier 2101. Accordingly, during the production of the IC package, a Wafer Per Hour (WPH) yield may be increased and production costs may be reduced.

Fig. 21C illustrates a top view of the wafer level die structure 2100 illustrated in fig. 21A, in accordance with an alternative embodiment. The embodiment shown in fig. 21C is similar to the embodiment shown in fig. 21B, wherein like elements are denoted by like reference numerals and detailed description is not repeated here. In the embodiment shown in FIG. 21C, dummy structure 2105₁Not as a continuous structure extending along the entire usable portion of carrier 2101. Also, each scribe 2111 is associated with a plurality of disconnected dummy structures 2105 of different lengths₁And (4) overlapping.

Referring to fig. 21D, IC die 117₁And dummy structure 2105₁Is sealed in the sealing agent 123₁In (1). Then, at IC die 117₁An insulating layer 2115 is formed thereover₁And in dummy structure 2105₁An insulating layer 2117 is formed thereover₁. In some embodiments, insulating layer 2115₁And an insulating layer 2117₁And encapsulant 123₁Are substantially flush or coplanar. In some embodiments, encapsulant 123₁May be formed using materials and methods similar to the encapsulant 107 described above with reference to fig. 19B and 19C, and will not be described again here. In some embodiments, insulating layer 2115₁And an insulating layer 2117₁May be formed using similar materials and methods as insulating layer 1907 described above with reference to fig. 19D and 19E, and is not described hereThe description is repeated. In some embodiments, insulating layer 2115₁And an insulating layer 2117₁May comprise the same material. In other embodiments, insulating layer 2115₁And an insulating layer 2117₁May comprise different materials. With a corresponding insulating layer 2115₁IC die 117₁With a corresponding insulating layer 2107₁And 2117₁Of (3) dummy structure 2105₁And a sealant 123₁Forming a first layer structure 2119 over carrier 2101₁。

Referring to fig. 21E, IC die 117₂Bonded to IC die 117₁. In some embodiments, IC die 117₂May be similar to IC die 1807 and may be formed using methods as described above with reference to fig. 18A and 18B, where IC die 117₂Like components to IC die 1807 are denoted by like reference numerals. In some embodiments, IC die 117 is bonded using a direct bonding method, such as a hybrid bonding method₂Bonded to IC die 117₁. In such an embodiment, IC die 117₂Is directly bonded to IC die 117₂And IC die 117, and a bond pad 1805₁Insulating layer 2115₁Direct bonding to IC die 117₂Insulating layer 1801. In some embodiments, IC die 117 is being tested₂Bonded to IC die 117₁Thereafter, an annealing process may be performed to strengthen the IC die 117₁And IC die 117₂To be joined. IC die 117₁TV 1709 and IC die 117₂Bonding between the bond pads 1805 provides the IC die 117₁And IC die 117₂To be electrically connected therebetween. In some embodiments, IC die 117₁TV 1709 and IC die 117₂The bond pads 1805 may comprise the same material. In other embodiments, IC die 117₁TV 1709 and IC die 117₂The bond pads 1805 may comprise different materials. In some embodiments, IC die 117₁Insulating layer 2115₁And IC die 117₂May comprise the same material. In other embodiments, IC die 117₁Insulating layer 2115₁And ICDie 117₂The insulating layer 1801 may comprise different materials.

In some embodiments, dummy structure 2105₂Bonded to dummy structure 2105₁. In some embodiments, dummy structure 2105₂The dummy structure 2105 described above with reference to figure 21D may be used₁Similar materials and methods are formed and will not be repeated here. In some embodiments, by coupling dummy structure 2105₂Insulating layer 2107 of₂Bonded to dummy structure 2105₁Insulating layer 2117₁Dummy structure 2105 may be formed₂Bonded to dummy structure 2105₁. In some embodiments, the insulating layer 2107 may be bonded using a direct bonding method, such as a fusion bonding method₂Bonded to the insulating layer 2117₁. In some embodiments, insulating layer 2107 is formed₂Bonded to the insulating layer 2117₁Previously, the insulating layer 2107 may be etched₂And an insulating layer 2117₁A surface treatment process is performed. Subsequently, an annealing process may be performed to strengthen the dummy structure 2105₂And dummy structure 2105₁To be joined. In some embodiments, insulating layer 2107₂And an insulating layer 2117₁May comprise the same material. In other embodiments, insulating layer 2107₂And an insulating layer 2117₁May comprise different materials. In some embodiments, dummy structure 2105₂May have dummy structures 2105 in top view similar to those shown in fig. 21B and 21C₁The same shape and the description will not be repeated here.

Subsequently, the IC die 117 is mounted₂And dummy structure 2105₂Is sealed in the sealing agent 123₂In IC die 117₂An insulating layer 2115 is formed thereover₂And in dummy structure 2105₂An insulating layer 2117 is formed thereover₂. In some embodiments, encapsulant 123₂The same sealant 123 as described above with reference to fig. 21D may be used₁Similar materials and methods are formed and will not be repeated here. In some embodiments, insulating layer 2115₂And an insulating layer 2117₂The insulating layers 2115 described above with reference to fig. 21D may be used separately₁Andinsulating layer 2117₁Similar materials and methods are formed and will not be repeated here. In some embodiments, insulating layer 2115₂And an insulating layer 2117₂May comprise the same material. In other embodiments, insulating layer 2115₂And an insulating layer 2117₂May comprise different materials. With a corresponding insulating layer 2115₂IC die 117₂With a corresponding insulating layer 2107₂And 2117₂Of (3) dummy structure 2105₂And a sealant 123₂In the first layer structure 2119₁A second layer structure 2119 is formed thereon₂。

With further reference to FIG. 21E, in a second layer structure 2119₂Formed over including having a corresponding insulating layer 2115₃IC die 117₃With a corresponding insulating layer 2107₃And 2117₃Of (3) dummy structure 2105₃And a sealant 123₃Third layer structure 2119₃. In some embodiments, IC die 117₃May be similar to IC die 1807 and may be formed using the method described above with reference to fig. 18A and 18B, where IC die 117₃Like components to IC die 1807 are denoted by like reference numerals. In some embodiments, a dummy structure 2105 similar to that described above with reference to figure 21D may be used₁Similar materials and methods are used to form dummy structure 2105₃And the description is not repeated here. In some embodiments, the second layer structure 2119 described above may be used₂Similar method forms the third layer structure 2119₃And the description is not repeated here. Subsequently, in the third layer structure 2119₃Formed over including having a corresponding insulating layer 2115₄IC die 117₄With a corresponding insulating layer 2107₄And 2117₄Of (3) dummy structure 2105₄And a sealant 123₄Of the fourth layer structure 2119₄. In some embodiments, IC die 117₄May be similar to IC die 1807 and may be formed using methods as described above with reference to fig. 18A-18B, where IC die 117₄Like components to IC die 1807 are denoted by like reference numerals. In some embodiments, mayTo use dummy die 2105 as described above with reference to figure 21D₁Similar materials and methods are used to form dummy structure 2105₄And the description is not repeated here. In some embodiments, the fourth layer structure 2119₄The second layer structure 2119 described above may be used₂Similar methods are formed and will not be repeated here. In some embodiments, dummy structure 2105₃And 2105₄There may be dummy structures 2105 in top view corresponding to those shown in fig. 21B and 21C₁The same shape and the description will not be repeated here. Formed dummy structure 2105₁To 2105₄May also be referred to as a stacked dummy structure 2121, and IC die 117₁To 117₄May also be referred to as die stack 113.

Referring to fig. 21F, IC die structure 2005 (see fig. 20B) is bonded to IC die 117 of die stack 113₄. In some embodiments, IC die structure 2005 is bonded to IC die 117 using a direct bonding method, such as a hybrid bonding method₄. In such an embodiment, IC die 117₄Is directly bonded to the bond pad 2003 of the IC die structure 2005 and the IC die 117₄Insulating layer 2115₄Directly to the insulating layer 2001 of the IC die structure 2005. Furthermore, the insulating layer 2001 of the IC die structure 2005 may be bonded directly to the dummy structure 2105 formed on the substrate₄Overlying insulating layer 2117₄. In some embodiments, IC die structure 2005 is bonded to IC die 117₄And dummy structure 2105₄Thereafter, an annealing process may be performed to enhance the bonding. IC die 117₄Provide the IC die structure 2005 and the IC die 117₄To be electrically connected therebetween. In some embodiments, IC die 117₄The TV 1709 and the bond pad 2003 of the IC die structure 2005 may comprise the same material. In other embodiments, IC die 117₄The TV 1709 and the bond pad 2003 of the IC die structure 2005 may comprise different materials. In some embodiments, insulating layer 2001 and IC die 117 of IC die structure 2005₄Insulating layer 2115₄Can be used forIncluding the same materials. In other embodiments, insulating layer 2001 and IC die 117 of IC die structure 2005₄Insulating layer 2115₄May comprise different materials. In some embodiments, insulating layer 2001 and insulating layer 2117₄May comprise the same material. In other embodiments, insulating layer 2001 and insulating layer 2117₄May comprise different materials.

Referring to fig. 21G, an encapsulant 109 is formed over and between IC die structures 2005. In some embodiments, encapsulant 109 may be formed using similar materials and methods as encapsulant 107 described above with reference to fig. 19B, and the description is not repeated here. In some embodiments, portions of carrier 1901 and insulating layer 1903 (see fig. 21F) of IC die structure 2005 and encapsulant 109 are removed to expose insulating layer 1717 of IC die 105 such that the exposed surface of insulating layer 1717 is flush or coplanar with the topmost surface of encapsulant 109. In some embodiments, portions of the carrier 1901, insulating layer 1903, and encapsulant 109 may be removed using a CMP process, a grinding process, an etching process, combinations thereof, and the like.

Referring to fig. 21H, connections 111 are formed over respective contact pads 1715 of IC die 105 that are electrically connected to respective contact pads 1715 of IC die 105. In some embodiments, each connection 111 can include a conductive pillar bump 2123 and a solder element 2127 located over the conductive pillar bump 2123. In some embodiments, the conductive pillar bumps 2123 can comprise a conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. In some embodiments, the solder element 2127 can include a lead-based solder, such as a PbSn composition, a lead-free solder including InSb, a tin, silver, and copper ("SAC") composition; and other eutectic materials that have a common melting point and form conductive solder connections in electronic applications. For lead-free solders, SAC solders of different compositions may be used, such as SAC 105(Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC 305, and SAC 405. The lead-free solder also includes SnCu compounds without using silver (Ag) and SnAg compounds without using copper (Cu).

In some embodiments, the method of forming the conductive pillar bumps 2123 can include forming openings in the insulating layer 1717 to expose respective contact pads 1715, forming a conductive seed layer over the insulating layer 1717 and in the openings of the insulating layer 1717, forming a sacrificial material (such as a photoresist material) over the conductive seed layer, patterning the sacrificial material to form openings in the sacrificial layer such that the openings of the sacrificial layer are aligned with the respective openings of the insulating layer 1717 and form combined openings, depositing the conductive material in the combined openings using an electrochemical plating process, an electroless plating process, ALD, PVD, combinations thereof, or the like to form the conductive pillar bumps 2123, removing the sacrificial layer, and removing the exposed portions of the conductive seed layer. In some embodiments, prior to removing the sacrificial layer, a solder material is formed over the conductive material of the conductive post bumps 2123 in the combined openings using evaporation, an electrochemical plating process, an electroless plating process, printing, solder transfer, combinations thereof, or the like to form solder elements 2127. In other embodiments, the connection 111 may be solder balls, controlled collapse chip connection (C4) bumps, Ball Grid Array (BGA) balls, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG), or the like. In some embodiments where the connection 111 comprises a solder material, a reflow process may be performed to shape the solder material into a desired bump shape.

With further reference to fig. 21H, after forming connectors 111, wafer-level die structure 2100 is singulated along scribe lines 2109 and 2111 (see fig. 21B and 21C) into individual IC packages 2125 such that each IC package 2125 includes an IC die 105 having a corresponding die stack 113 and partially stacked dummy structures 2121. In some embodiments, the singulation process may include sawing, laser ablation, etching, combinations thereof, and the like. In some embodiments, corresponding die region 2113₁The IC package 2125 (see fig. 21B and 21C) forms the IC package 200 (see fig. 2A and 2B). In some embodiments, corresponding die region 2113₂The IC package 2125 (see fig. 21B and 21C) forms the IC package 100 (see fig. 1A and 1B). In some embodiments, corresponding die region 2113₃The IC package 2125 (see fig. 21C) forms the IC package 400 (see fig. 4A and 4B). In some embodiments, corresponding die region 2113₄(see fig. 21C) IC package 2125An IC package 300 is formed (see fig. 3A and 3B).

Fig. 22A-22D illustrate cross-sectional views of various process steps during fabrication of an integrated circuit package, such as, for example, the IC packages 500-800 illustrated in fig. 5A and 5B, 6A and 6B, 7A and 7B, respectively, in accordance with some embodiments. In order to highlight the differences between the embodiment shown in fig. 22A to 22D and the embodiment shown in fig. 21A to 21H, common parts of these embodiments are denoted by the same reference numerals. Further, detailed description of common components (described above with reference to fig. 21A to 21H) will not be repeated here.

Referring to fig. 22A, an insulating layer 2115 is formed₄And 2117₄Wafer-level die structure 2100 shown in fig. 21E was previously bonded to carrier 2201 to begin forming wafer-level die structure 2200. In some embodiments, for example, an insulation layer 2203 is formed over carrier 2201 and wafer-level die structure 2100 is bonded to insulation layer 2203 using a direct bonding method, such as a fusion bonding method. In other embodiments, for example, insulating layer 2203 may be omitted and wafer-level die structure 2100 may be bonded to carrier 2201 using a direct bonding method, such as a fusion bonding method. In some embodiments, carrier 2201 may be formed using materials and methods similar to carrier 2101 described above with reference to fig. 21A, and the description is not repeated here. In some embodiments, the insulating layer 2203 can be formed using similar materials and methods as the insulating layer 2103 described above with reference to fig. 21A, and the description is not repeated here.

Referring to FIG. 22B, carrier 2101 and insulating layer 2103 are removed to expose IC die 117₁The insulating layer 1717. In some embodiments, the carrier 2101 and the insulating layer 2103 may be removed using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, an insulating layer 2205 is formed over die stack 113 and stacked dummy structures 2121, and bond pads 2209 and corresponding vias 2207 are formed in insulating layers 1717 and 2205. In some embodiments, bond pads 2209 are formed in insulating layer 2205 and vias 2207 are formed in insulating layer 1717. In some embodiments, the method can be usedThe insulating layer 2205 is formed using a material and a method similar to those of the insulating layer 1801 described above with reference to fig. 18A, and description thereof will not be repeated here. In some embodiments, bond pad 2209 and via 2207 may be formed using similar materials and methods as bond pad 1805 and via 1803, respectively, described above with reference to fig. 18A, and will not be repeated here. In some embodiments, via 2207 is in communication with IC die 117₁Are in direct electrical contact with corresponding interconnects 1713. In other embodiments, via 2207 may be in communication with IC die 117₁And may make direct electrical contact with and may pass through IC die 117₁Is electrically connected to IC die 117₁A respective interconnect 1713.

Referring to fig. 22C, IC die 117 with IC die structure 1911 (see fig. 19G) bonded to die stack 113₁. In some embodiments, IC die structures 1911 are bonded to respective IC dies 117 using a direct bonding method, such as a hybrid bonding method₁. In such an embodiment, bond pads 2209 are bonded directly to respective TVs 1709 of IC die 105 of IC die structure 1911, and insulation layer 2205 is bonded directly to insulation layer 1907 of IC die 105 of IC die structure 1911. In some embodiments, after bonding the IC die structures 1911 to the respective die stacks 113, an annealing process may be performed to strengthen the bonding. The bond between TV 1709 of IC die 105 and bond pad 2009 provides an electrical connection between IC die structure 1911 and die stack 113. In some embodiments, TV 1709 and bond pad 2209 of IC die 105 may comprise the same material. In other embodiments, TV 1709 and bond pad 2209 of IC die 105 may comprise different materials. In some embodiments, insulating layer 2205 and insulating layer 1907 of IC die structure 1911 may comprise the same material. In other embodiments, insulating layer 2205 and insulating layer 1907 of IC die structure 1911 may comprise different materials.

Referring to fig. 22D, an encapsulant 109 is formed over and between IC die structures 1911. In some embodiments, encapsulant 109 may be formed using similar materials and methods as encapsulant 107 described above with reference to fig. 19B, and the description is not repeated here. In some embodiments, portions of carrier 1901 and insulating layer 1903 (see fig. 22C) and encapsulant 109 of IC die structure 1911 are removed to expose insulating layer 1717 of IC die 105 such that an exposed surface of insulating layer 1717 is substantially flush or coplanar with a topmost surface of encapsulant 109. In some embodiments, portions of the carrier 1901, insulating layer 1903, and encapsulant 109 may be removed using a CMP process, a grinding process, an etching process, combinations thereof, and the like.

In some embodiments, after removing carrier 1901 and insulating layer 1903, connectors 111 are formed over respective contact pads 1715 of IC die 105 that are electrically connected to respective contact pads 1715 of IC die 105, as described above with reference to fig. 21H, and the description is not repeated here. In some embodiments, after forming connections 111, wafer-level die structures 2200 are singulated along scribe lines 2109 and 2111 (see fig. 21B and 21C) into individual IC packages 2211 such that each IC package 2211 includes an IC die 105 having a corresponding die stack 113 and a portion of stacked dummy structures 2121. In some embodiments, the singulation process may include sawing, laser ablation, etching, combinations thereof, and the like. In some embodiments, corresponding die region 2113₁The IC package 2211 (see fig. 21B and 21C) forms an IC package 600 (see fig. 6A and 6B). In some embodiments, corresponding die region 2113₂The IC package 2211 (see fig. 21B and 21C) of (a) forms an IC package 500 (see fig. 5A and 5B). In some embodiments, corresponding die region 2113₃The IC package 2211 (see fig. 21C) forms an IC package 800 (see fig. 8A and 8B). In some embodiments, corresponding die region 2113₄The IC package 2211 (see fig. 21C) forms an IC package 700 (see fig. 7A and 7B).

Fig. 23A-23F illustrate top and cross-sectional views of various process steps during fabrication of an integrated circuit package, such as, for example, the IC packages 900-1200 illustrated in fig. 9A and 9B, 10A and 10B, 11A and 11B, and 12A and 12B, respectively, in accordance with some embodiments. In order to highlight the differences between the embodiment shown in fig. 23A to 23F and the embodiment shown in fig. 21A to 21H, common parts of these embodiments are denoted by the same reference numerals. Further, detailed descriptions of common components (described above with reference to fig. 21A to 21H) will not be repeated here. In the embodiment shown in fig. 21A-21H, IC die 105 are bonded to respective die stacks 113 such that die stacks 113 are part of an unsingulated wafer-level die structure 2100 (see, e.g., fig. 21F) and IC die 105 is part of a singulated IC die structure 2005 (see, e.g., fig. 21F). As described in more detail below, in the embodiment shown in fig. 23A-23F, IC die 105 is bonded to die stack 113 such that die stack 113 is part of a singulated die structure (see, e.g., fig. 23B) and IC die 105 is part of an unsingulated wafer-level die structure (see, e.g., fig. 23B).

Referring to fig. 23A, a wafer level die structure 2300 is shown. In some embodiments, the wafer-level die structure 2300 is similar to the wafer-level die structure 2100 illustrated in fig. 21E, wherein like components are denoted with like reference numerals, and with the difference that the stacked dummy structure 2121 is omitted. In some embodiments, the wafer-level die structure 2300 may be formed as described above with reference to fig. 21A-21E without forming stacked dummy structures 2121 and will not be described again here. In some embodiments, the wafer level die structure 2300 is singulated into individual (chip-level or die-level) IC die structures 2301. In some embodiments, the singulation process may include sawing, laser ablation, etching, combinations thereof, and the like.

Referring to fig. 23B, in some embodiments, the IC die structures 2301 are bonded to respective IC dies 105, while the IC dies 105 are still part of the unsegmented wafer-level die structure 2000 (see fig. 20A) to begin forming the wafer-level die structures 2307. In some embodiments, IC die structures 2301 are bonded to respective IC dies 105 as described above with reference to fig. 21F, and the description is not repeated here. In some embodiments, the dummy structures 2303 are bonded to the insulating layer 2001 of the wafer level die structure 2000 such that each IC die structure 2301 is between adjacent dummy structures 2303. In some embodiments, a dummy structure 2105 similar to that described above with reference to figure 21A may be used₁Similar materialsAnd the method forms the dummy structure 2303, and the description is not repeated here. In some embodiments, each dummy structure 2303 can include an insulating layer 2305 on one side. In some embodiments, an insulating layer 2107 similar to that described above with reference to fig. 21A may be used₁Similar materials and methods form the insulating layer 2305, and a description thereof will not be repeated. In some embodiments, insulating layer 2305 and insulating layer 2001 can comprise the same material. In other embodiments, insulating layer 2305 and insulating layer 2001 can comprise different materials. In some embodiments, the dummy structure 2303 may be bonded to the insulating layer 2001 by bonding the insulating layer 2305 of the dummy structure 2303 to the insulating layer 2001. In some embodiments, insulating layer 2305 can be bonded to insulating layer 2001 using a direct bonding method, such as a fusion bonding method. In some embodiments, a surface treatment process may be performed on insulating layer 2305 and insulating layer 2001 before bonding insulating layer 2305 to insulating layer 2001. Subsequently, an annealing process may be performed to strengthen the bond between the dummy structure 2303 and the wafer-level die structure 2000.

Figure 23C illustrates a top view of the wafer level die structure 2307 shown in figure 23B, in accordance with some embodiments. In some embodiments, wafer level die structure 2000 is divided into die regions 2313 by scribe lines 2309 and 2311_i(where i 1.., N, where N is the total number of die regions). In some embodiments, scribe 2309 is perpendicular to scribe 2311. In such an embodiment, die area 2313_i(where i ═ 1.., N) has a rectangular shape in a top view. In other embodiments, score lines 2309 and score lines 2311 may form angles other than 90 degrees. In such an embodiment, die area 2313_i(where i ═ 1.., N) has the shape of a parallelogram in a top view. In some embodiments, the dummy structures 2303 have a rectangular shape in a top view. In some embodiments, dummy structures 2303 overlap respective scribe lines 2311 such that dummy structures 2303 are in regions 2113 separated by respective scribe lines 2311_iIs shared between subsets of (where i 1.·, N). In some embodiments, the dummy structures 2303 may be formed along the entire usable portion of the wafer-level die structure 2000 (such as a package)Including die region 2113_iPortions of) of the dummy structures such that each scribe line 2311 overlaps a respective single continuous dummy structure 2303. As described in more detail below, wafer level die structures 2307 are singulated along scribe lines 2309 and 2311 to form individual IC packages. This singulation process also singulates the dummy structures 2303 and forms individual (chip-level or die-level) dummy structures for respective individual IC packages. In some embodiments, by forming dummy structures 2303 that overlap scribe lines 2311, the time for forming a single IC package may be reduced. For example, the time to form a single IC package may reduce the time required to place and bond a single (chip-level or die-level) dummy structure within each die region of wafer-level die structure 2000 prior to the singulation process. Accordingly, during the production of the IC package, a Wafer Per Hour (WPH) yield may be increased and production costs may be reduced.

Fig. 23D illustrates a top view of the wafer level die structure 2307 shown in fig. 23B in accordance with an alternative embodiment. The embodiment shown in fig. 23D is similar to the embodiment shown in fig. 23C, wherein like elements are denoted by like reference numerals and detailed description is not repeated here. In the embodiment shown in fig. 23D, the dummy structures 2303 do not form a continuous structure extending along the entire usable portion of the wafer-level die structure 2000. Also, each scribe line 2311 overlaps a plurality of disconnected dummy structures 2303 of different lengths.

Referring to fig. 23E, an encapsulant 907 is formed over and around IC die structure 2301 and dummy structure 2303. In some embodiments, encapsulant 907 may be formed using a material method similar to encapsulant 107 described above with reference to fig. 19B, and the description is not repeated here. Subsequently, encapsulant 907, IC die structure 2301, and dummy structure 2303 are planarized such that a topmost surface of IC die structure 2301 is substantially flush or coplanar with a topmost surface of dummy structure 2303 and a topmost surface of encapsulant 907. In some embodiments, the planarization process may include a CMP process, a grinding process, an etching process, combinations thereof, and the like.

Referring to fig. 23F, in some embodiments, carrier 1901 and insulating layer 1903 (see fig. 23E) are removed from wafer level die structure 2000 to expose insulating layer 1717 and encapsulant 107 of IC die 105. As such, the exposed surface of the insulating layer 1717 is substantially flush or coplanar with the exposed surface of the encapsulant 107. In some embodiments, carrier 1901 and insulating layer 1903 may be removed using a CMP process, a grinding process, an etching process, combinations thereof, and the like.

With further reference to fig. 23F, connections 111 are formed over respective contact pads 1715 of IC die 105 as described above with reference to fig. 21H, electrically connected to respective contact pads 1715, and the description is not repeated here. After forming the connections 111, the wafer-level die structures 2307 are singulated along scribe lines 2309 and 2311 (see fig. 23C and 23D) into individual IC packages 2315 such that each IC package 2315 includes an IC die 105 and a respective die stack 113 and a portion of a respective dummy structure 2303. In some embodiments, the singulation process may include sawing, laser ablation, etching, combinations thereof, and the like. In some embodiments, corresponding to die area 2313₁The IC package 2315 (see fig. 23C and 23D) forms an IC package 1000 (see fig. 10A and 10B). In some embodiments, corresponding to die area 2313₂The IC package 2315 (see fig. 23C and 23D) forms an IC package 900 (see fig. 9A and 9B). In some embodiments, corresponding to die area 2313₃The IC package 2315 (see fig. 23D) forms an IC package 1200 (see fig. 12A and 12B). In some embodiments, corresponding to die area 2313₄The IC package 2315 (see fig. 23D) forms an IC package 1100 (see fig. 11A and 11B).

Fig. 24A-24C illustrate cross-sectional views of various process steps during fabrication of an integrated circuit package, such as, for example, the IC packages 1300-1600 illustrated in fig. 13A and 13B, 14A and 14B, 15A and 15B, in accordance with some embodiments. In order to highlight the differences between the embodiment shown in fig. 24A to 24C and the embodiment shown in fig. 23A to 23F, common parts of these embodiments are denoted by the same reference numerals. Further, detailed description of common components (described above with reference to fig. 23A to 23F) will not be repeated here.

Referring to fig. 24A, a wafer level die structure 2400 is shown. In some embodiments, the wafer-level die structure 2400 is similar to the wafer-level die structure 2200 shown in fig. 22B, wherein like parts are denoted with like reference numerals, and with the difference that the stacked dummy structure 2121 is omitted. In some embodiments, the wafer-level die structure 2400 may be formed as described above with reference to fig. 22A and 22B without forming stacked dummy structures 2121, and the description is not repeated here. In some embodiments, the wafer-level die structure 2400 is singulated into individual (chip-level or die-level) IC die structures 2401. In some embodiments, the singulation process may include sawing, laser ablation, etching, combinations thereof, and the like.

Referring to fig. 24B, in some embodiments, IC die structures 2401 are bonded to respective IC dies 105 while IC dies 105 are still part of unsingulated wafer-level die structure 1900 (see fig. 19E) to begin forming wafer-level die structures 2403. In some embodiments, IC die structure 2401 is bonded to a respective IC die 105 of wafer level die structure 1900 as described above with reference to fig. 19E, and the description is not repeated here. In some embodiments, the dummy structures 2303 are bonded to the wafer level die structures 1900 such that each IC die structure 2401 is between adjacent dummy structures 2303. In some embodiments, the dummy structure 2303 may be bonded to the wafer-level die structure 1900 by bonding the insulating layer 2305 of the dummy structure 2303 to the wafer-level die structure 1900. In some embodiments, the insulating layer 2305 may be bonded to the wafer-level die structure 1900 using a direct bonding method, such as a fusion bonding method. Subsequently, an annealing process may be performed to strengthen the bond between the dummy structure 2303 and the wafer-level die structure 1900.

With further reference to fig. 24B, an encapsulant 907 is formed over and around IC die structure 2401 and dummy structure 2303. Subsequently, encapsulant 907, IC die structure 2401 and dummy structure 2303 are planarized such that a topmost surface of IC die structure 2401 is substantially flush or coplanar with a topmost surface of dummy structure 2303 and a topmost surface of encapsulant 907. In some embodiments, the planarization process may include a CMP process, a grinding process, an etching process, combinations thereof, and the like.

Referring to fig. 24C, carrier 1901 and insulating layer 1903 (see fig. 24B) of wafer level die structure 1900 are removed to expose insulating layer 1717 of IC die 105 and encapsulant 107 such that the exposed surface of insulating layer 1717 is substantially flush or coplanar with the exposed surface of encapsulant 107. In some embodiments, the carrier 1901 and insulating layer 1903 may be removed using a CMP process, a lapping process, an etching process, combinations thereof, and the like.

With further reference to fig. 24C, connections 111 are formed over respective contact pads 1715 of IC die 105 as described above with reference to fig. 21H, electrically connected to respective contact pads 1715, and the description is not repeated here. After forming the connectors 111, the wafer-level die structures 2403 are singulated along scribe lines 2309 and 2311 (see fig. 23C and 23D) into individual IC packages 2405 such that each IC package 2405 includes an IC die 105 and a corresponding die stack 113 and a portion of a corresponding dummy structure 2303. In some embodiments, the singulation process may include sawing, laser ablation, etching, combinations thereof, and the like. In some embodiments, corresponding to die area 2313₁The IC package 2405 (see fig. 23C and 23D) forms an IC package 1400 (see fig. 14A and 14B). In some embodiments, corresponding to die area 2313₂The IC package 2405 (see fig. 23C and 23D) forms an IC package 1300 (see fig. 13A and 13B). In some embodiments, corresponding to die area 2313₃The IC package 2405 (see fig. 23D) forms an IC package 1600 (see fig. 16A and 16B). In some embodiments, corresponding to die area 2313₄The IC package 2405 (see fig. 23D) forms an IC package 1500 (see fig. 15A and 15B).

Fig. 25 is a flow diagram illustrating a method 2500 of forming an integrated circuit package, such as, for example, the IC packages 100-800 illustrated in fig. 1A and 1B, fig. 2A and 2B, fig. 3A and 3B, fig. 4A and 4B, fig. 5A and 5B, fig. 6A and 6B, fig. 7A and 7B, fig. 8A and 8B, respectively, in accordance with some embodiments. The method begins at step 2501, where a first die structure (such as, for example, IC die structure 103 in fig. 1A and 1B) is formed as described above with reference to fig. 21A-21E. In the step of2521, a second die structure (such as, for example, IC die structure 101 in fig. 1A and 1B) is formed as described above with reference to fig. 20A and 20B. In step 2523, the first die structure is bonded to the second die structure as described above with reference to fig. 21F. The method of forming the first die structure begins at step 2503, where a first IC die (such as, for example, IC die 117 shown in fig. 21A) is formed as described above with reference to fig. 21A₁) Is joined to a carrier (such as, for example, carrier 2101 shown in fig. 21A). In step 2505, a first dummy structure (such as, for example, dummy structure 2105 shown in fig. 21A) is formed as described above with reference to fig. 21A₁) Is bonded to the carrier. In step 2507, a first encapsulant (such as, for example, encapsulant 123 shown in fig. 21D) is formed around the first IC die and the first dummy structure, as described above with reference to fig. 21D₁). In step 2509, a second IC die (such as, for example, IC die 117 shown in fig. 21E) is formed as described above with reference to fig. 21E₂) Bonded to the first IC die. In step 2511, a second dummy structure (such as, for example, dummy structure 2105 shown in fig. 21E) is formed as described above with reference to fig. 21E₂) Bonded to the first dummy structure. In step 2513, a second encapsulant (such as, for example, encapsulant 123 shown in fig. 21E) is formed around the second IC die and the second dummy structure, as described above with reference to fig. 21E₂). In some embodiments, the stacking process may continue until a desired number of IC dies and a desired number of dummy structures are bonded to the carrier. In step 2515, the topmost IC die (such as, for example, IC die 117 shown in fig. 21E) is tested as described above with reference to fig. 21E₄) Bonded to a previous IC die (such as, for example, IC die 117 shown in FIG. 21E)₃). In step 2517, the topmost dummy structure (such as, for example, dummy die 2105 shown in fig. 21E) is tested as described above with reference to fig. 21E₄) Bonding to a previous dummy structure (such as, for example, dummy structure 2105 shown in FIG. 21E)₃). In step 2519, a topmost encapsulant (such as, for example, encapsulant 123 shown in fig. 21E) is formed around the topmost die IC die and the topmost dummy structure, as described above with reference to fig. 21E₄)。

FIG. 26 is a block diagram according to some embodimentsA flow diagram of a method 2600 of forming an integrated circuit package, such as, for example, IC packages 900-1600 shown in fig. 9A and 9B, 10A and 10B, 11A and 11B, 12A and 12B, 13A and 13B, 14A and 14B, 15A and 15B, 16A and 16B, respectively, is shown. The method begins at step 2601, where a first die structure (such as, for example, IC die structure 2301 shown in fig. 23A) is formed as described above with reference to fig. 23A. In step 2615, a second die structure (such as, for example, the wafer-level die structure 2000 shown in fig. 23B) is formed as described above with reference to fig. 20A and 20B. In step 2617, the first die structure is bonded to the second die structure as described above with reference to fig. 23B. In step 2619, a dummy structure (such as, for example, dummy structure 2303 shown in fig. 23B) is bonded to the second die structure as described above with reference to fig. 23B. In step 2621, a first encapsulant (such as, for example, encapsulant 907 shown in fig. 23E) is formed around the first dummy structures and the dummy structures, as described above with reference to fig. 23E. The method of forming the first die structure begins at step 2603, where a first IC die (such as, for example, IC die 117 shown in fig. 23A) is formed as described above with reference to fig. 23A₁) Is joined to a carrier (such as, for example, carrier 2101 shown in fig. 23A). In step 2605, a second encapsulant (such as, for example, encapsulant 123 shown in fig. 23A) is formed around the first IC die as described above with reference to fig. 23A₁). In step 2607, a second IC die (such as, for example, IC die 117 shown in fig. 23A) is formed as described above with reference to fig. 23A₂) Bonded to the first IC die. In step 2609, a third encapsulant (such as, for example, encapsulant 123 shown in fig. 23A) is formed around the second IC die as described above with reference to fig. 23A₂). In some embodiments, the stacking process may continue until a desired number of IC dies are bonded to the carrier. In step 2611, the topmost IC die (such as, for example, IC die 117 shown in fig. 23A) is tested as described above with reference to fig. 23A₄) Bonded to a previous IC die (such as, for example, IC die 117 shown in FIG. 23A)₃). In step 2613, a topmost encapsulant (such as, for example, an encapsulant) is formed around the topmost die IC die as described above with reference to fig. 23AThe sealant 123 as shown in fig. 23A₄)。

According to an embodiment, a method comprises: forming a first die structure comprising a first die stack bonded to a carrier and a stacked dummy structure; forming a second die structure, the second die structure comprising a first integrated circuit die; bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the first die stack to the first integrated circuit die, the topmost integrated circuit die of the first die stack being the integrated circuit die of the first die stack that is furthest from the carrier; and performing a singulation process on the first die structure to form a plurality of individual die structures, wherein the singulation process singulates the stacked dummy structure into a plurality of individually stacked dummy structures. In an embodiment, forming the first die structure includes: bonding a front side of the second integrated circuit die to the carrier; bonding the first dummy structure to a carrier adjacent to the second integrated circuit die; encapsulating the second integrated circuit die and the first dummy structure in a first encapsulant; bonding a front side of a third integrated circuit die to a back side of a second integrated circuit die, the back side of the second integrated circuit die being opposite the front side of the second integrated circuit die; bonding a second dummy structure to the first dummy structure; and encapsulating the third integrated circuit die and the second dummy structure in a second encapsulant. In an embodiment, the front side of the second integrated circuit die is bonded to the carrier using a fusion bonding method. In an embodiment, a hybrid bonding method is used to bond the front side of the third integrated circuit die to the back side of the second integrated circuit die. In an embodiment, the second dummy structure is bonded to the first dummy structure using a fusion bonding method. In an embodiment, a hybrid bonding method is used to bond a topmost integrated circuit die of the first die stack to the first integrated circuit die. In an embodiment, the stacked dummy structure is configured as a heat dissipation structure. In an embodiment, the first die structure further includes a second die stack bonded to the carrier, and the stacked dummy structure is disposed over the scribe line of the carrier between the first die stack and the second die stack.

According to another embodiment, a method comprises: forming a first die structure comprising a die stack bonded to a carrier; forming a second die structure, the second die structure comprising a first integrated circuit die; bonding the first die structure to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die, the topmost integrated circuit die of the die stack being the integrated circuit die of the die stack that is farthest from the carrier; bonding the first dummy structure to a second die structure adjacent to the first die structure; encapsulating the first die structure in a first encapsulant; and performing a singulation process on the second die structure to form a plurality of individual die structures, wherein the singulation process separates the first dummy structure into the plurality of individual dummy structures. In an embodiment, forming the first die structure includes: bonding a front side of the second integrated circuit die to the carrier; encapsulating the second integrated circuit die in a second encapsulant; bonding a front side of a third integrated circuit die to a back side of a second integrated circuit die, the back side of the second integrated circuit die being opposite the front side of the second integrated circuit die; and encapsulating the third integrated circuit die in a third encapsulant. In an embodiment, a hybrid bonding method is used to bond a topmost integrated circuit die of the die stack to the first integrated circuit die. In an embodiment, the first dummy structure is bonded to the second die structure using a fusion bonding method. In an embodiment, forming the second die structure includes encapsulating the first integrated circuit die in a second encapsulant. In an embodiment, the first dummy structure is configured as a heat dissipation structure. In an embodiment, the method further includes bonding the second dummy structure to a second die structure, the first die structure interposed between the first dummy structure and the second dummy structure.

According to yet another embodiment, a semiconductor structure includes: a die stack bonded to the base structure, the die stack including a first integrated circuit die, the first integrated circuit die being the integrated circuit die of the die stack that is furthest from the base structure; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a first side of the first integrated circuit die in physical contact with a second side of the second integrated circuit die; a heat spreading structure bonded to the die structure adjacent the die stack, a sidewall of the heat spreading structure being substantially coplanar with a sidewall of the die structure; and an encapsulant extending along sidewalls of the die stack. In an embodiment, the heat dissipation structure comprises a stack of dummy structures. In an embodiment, the heat dissipation structure is free of encapsulant. In an embodiment, a topmost surface of the base structure is substantially flush with a topmost surface of the heat dissipation structure, the topmost surface of the base structure being a surface of the base structure furthest from the die structure, the topmost surface of the heat dissipation structure being a surface of the heat dissipation structure furthest from the die structure. In an embodiment, a topmost surface of the heat dissipation structure is substantially flush with a topmost surface of the encapsulant, the topmost surface of the heat dissipation structure being a surface of the heat dissipation structure furthest from the die structure, and the topmost surface of the encapsulant being a surface of the encapsulant furthest from the die structure.

Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate to allow testing of the 3D package or the 3DIC, use of probes and/or probe cards, and the like. Verification tests may be performed on the intermediate structure as well as the final structure. Further, the structures and methods disclosed herein may be used in conjunction with testing methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.