阅读说明：本技术 半导体装置组合件和其制造方法 (Semiconductor device assembly and method of manufacturing the same ) 是由 罗时剑 于 2019-05-31 设计创作，主要内容包括：本申请设计一种半导体装置组合件和其制造方法。一种半导体装置组合件,其包含连接所述半导体装置组合件的两个组件的热响应材料的第一元件。所述第一元件经配置以在第一确定的温度下向邻近组件施加力,以减少所述邻近组件中的一或两个的翘曲。所述第一元件可膨胀或收缩以施加所述力。所述半导体装置可包含连接两个组件的热响应材料的第二元件。所述第二元件可经配置以在第二预先确定的温度下膨胀或收缩。所述第二元件可经配置以施加与所述第一元件相比不同量的力。所述第二元件可经配置以施加与所述第一元件相比相反方向的力。所述第一元件和所述第二元件可经组合配置,以减少所述半导体装置组合件中一或多个组件的翘曲。(The present application relates to a semiconductor device assembly and a method of manufacturing the same. A semiconductor device assembly includes a first element of thermally responsive material connecting two components of the semiconductor device assembly. The first element is configured to apply a force to adjacent components at a first determined temperature to reduce warpage of one or both of the adjacent components. The first element may expand or contract to apply the force. The semiconductor device may include a second element of thermally responsive material connecting two components. The second element may be configured to expand or contract at a second predetermined temperature. The second element may be configured to apply a different amount of force than the first element. The second element may be configured to apply a force in an opposite direction as compared to the first element. The first element and the second element may be configured in combination to reduce warpage of one or more components in the semiconductor device assembly.)

1. A semiconductor device assembly, comprising:

a first semiconductor device;

a substrate;

a first element comprising a thermally responsive material connected between the substrate and the first semiconductor device;

wherein the first element is configured to apply a force to the first semiconductor device at a first predetermined temperature.

2. The assembly of claim 1, wherein the first element is configured to apply the force to reduce warpage of the first semiconductor device at the first predetermined temperature.

3. The assembly of claim 1, wherein the first element is configured to apply the force to the first semiconductor device by shrinking the first element at the first predetermined temperature.

4. The assembly of claim 1, wherein the first element is configured to apply the force to the first semiconductor device by expanding the first element at the first predetermined temperature.

5. The assembly of claim 1, further comprising at least one electrical interconnect between the first semiconductor device and the substrate.

6. The assembly of claim 5, further comprising a second element comprising a thermally responsive material connected between the substrate and the first semiconductor device, wherein the second element is configured to apply a force to the first semiconductor device at the predetermined temperature.

7. The assembly of claim 6, wherein the second element is configured to apply the force at the first predetermined temperature.

8. The assembly of claim 6, wherein the second element is configured to apply the force at a second predetermined temperature different from the first predetermined temperature.

9. The assembly of claim 7, wherein the first element is configured to apply the force to the first semiconductor device by shrinking the first element at the first predetermined temperature, and wherein the second element is configured to apply the force to the first semiconductor device by shrinking the second element at the first predetermined temperature.

10. The assembly of claim 7, wherein the first element is configured to apply the force to the first semiconductor device by contracting the first element at the first predetermined temperature, and wherein the second element is configured to apply the force to the first semiconductor device by expanding the second element at the first predetermined temperature.

11. The assembly of claim 8, wherein the first element is configured to apply the force to the first semiconductor device by shrinking the first element at the first predetermined temperature, and wherein the second element is configured to apply the force to the first semiconductor device by shrinking the second element at the second predetermined temperature.

12. The assembly of claim 8, wherein the first element is configured to apply the force to the first semiconductor device by contracting the first element at the first predetermined temperature, and wherein the second element is configured to apply the force to the first semiconductor device by expanding the second element at the second predetermined temperature.

13. The assembly of claim 9, wherein the first element is positioned along a perimeter of the first semiconductor device and wherein the second element is positioned at a central region of the first semiconductor device.

14. The assembly of claim 1, further comprising:

a second semiconductor device;

a second element comprising a thermally responsive material connected between the first semiconductor device and the second semiconductor device;

wherein the second element is configured to apply a force to the first semiconductor device and the second semiconductor device at the first predetermined temperature.

15. A semiconductor device assembly, comprising:

a first semiconductor device;

a second semiconductor device;

a plurality of interconnects electrically connecting the first semiconductor device and the second semiconductor device; and

a first plurality of elements comprising a thermally responsive material connecting the first semiconductor device and the second semiconductor device, wherein the first plurality of elements are configured to exert a force at a predetermined temperature to reduce warpage of the first semiconductor device at the predetermined temperature or to reduce warpage of the second semiconductor device at the predetermined temperature.

16. The assembly of claim 15, the first semiconductor device and the second semiconductor device each being rectangular in shape having four corners, wherein the first plurality of elements are positioned adjacent to each of the four corners of the first semiconductor device and the second semiconductor device.

17. The assembly of claim 15, comprising a second plurality of elements comprising a thermally responsive material connecting the first semiconductor device and the second semiconductor device, wherein the second plurality of elements are configured to exert a force at a predetermined temperature to reduce the warpage of the first semiconductor device at the predetermined temperature or to reduce the warpage of the second semiconductor device at the predetermined temperature.

18. The assembly of claim 15, wherein the first plurality of elements is configured to apply the force by contracting each of the first plurality of elements at the predetermined temperature, and wherein the second plurality of elements is configured to apply the force by expanding each of the second plurality of elements at the predetermined temperature.

19. A method of fabricating a semiconductor device assembly, comprising:

providing a substrate;

providing a first semiconductor device;

connecting the first semiconductor device to the substrate with at least one first element comprising a thermally responsive material; and

heating the semiconductor device assembly to a first predetermined temperature, wherein the at least one first element applies a force to reduce warpage of the first semiconductor device at the first predetermined temperature.

20. The method of claim 19, comprising determining the warpage of the first semiconductor device at the first predetermined temperature and positioning the at least one first element based on the warpage determination to reduce the warpage of the first semiconductor, then connecting the first semiconductor device to the substrate with at least one first element.

21. The method of claim 20, further comprising:

positioning at least one second element comprising a thermally responsive material to reduce the warpage of the first semiconductor based on determining the warpage; and

connecting the first semiconductor arrangement to the substrate with at least one second element.

22. The method of claim 21, wherein the at least one second element applies the force to reduce the warpage of the first semiconductor device at the predetermined temperature.

23. The method of claim 21, comprising heating the semiconductor device assembly to a second predetermined temperature, wherein the at least one second element applies a force to reduce the warpage of the first semiconductor device at the second predetermined temperature.

Technical Field

Embodiments described herein relate to thermally responsive materials that can reduce or minimize warpage of semiconductor devices during processing, and methods of reducing or minimizing warpage of semiconductor devices using such thermally responsive materials.

Background

Semiconductor processing and packaging technologies continue to evolve to meet industry demands for increased performance and reduced size. Electronic products, such as cell phones, smart phones, tablet computers, personal digital assistants, notebook computers, and other electronic devices, require packaged semiconductor assemblies having a high density of devices while having a relatively small footprint. For example, the space available for memory devices, processors, and other devices in electronic products continues to decrease, requiring an increase in the density of semiconductor devices. The thickness of semiconductor devices is continuously decreasing to reduce the size of semiconductor device packages. One approach to increasing the density of semiconductor devices is to stack the semiconductor devices to form a semiconductor device assembly.

During the process of forming a semiconductor device assembly, the components may undergo various processes with elevated temperatures. For example, the temperature at which solder joints or interconnects are created between semiconductor devices during a reflow process may reach an elevated temperature, such as 260 degrees celsius. As will be appreciated by those skilled in the art, the elevated temperature may vary depending on the components of the semiconductor device assembly and the process used to form the assembly. As another example, during a Thermal Compression Bonding (TCB) process, the semiconductor device assembly is subjected to elevated temperatures, which may result in undesirable warpage of the semiconductor device components in the assembly.

The semiconductor device assembly may include various components such as, but not limited to, a substrate, a semiconductor device, and a molding compound. Each of the components may have different Coefficients of Thermal Expansion (CTE), which may create potential problems. When a semiconductor device assembly is subjected to high temperatures, the semiconductor device assembly may experience warpage due to the different CTEs of the individual components of the assembly. Warping can place a significant amount of stress on the components of the assembly. If the warpage is too great, the warpage may create reliability issues for interconnects within the semiconductor device assembly. For example, warpage of greater than, but not limited to, 50 microns can cause solder joint reliability problems.

Warpage due to CTE mismatch can create problems when connecting the semiconductor device assembly to a board or substrate. Likewise, CTE mismatch may also create problems when connecting a first semiconductor device to a second semiconductor device. The first semiconductor device may have a first warpage at an expected reflow temperature, and the second semiconductor device may have a second warpage different from the first warpage at the expected reflow temperature. The difference between the first warpage and the second warpage may make it very difficult to connect the first semiconductor device to the second semiconductor device. For example, if the warpage increases the distance between two semiconductor devices, the warpage may cause breakage of interconnects between the two semiconductor devices. Conversely, if the warpage reduces the distance between two semiconductor devices, the warpage may cause a short between two adjacent interconnects. As will be appreciated by those skilled in the art having the benefit of this disclosure, the reduction in distance may cause the interconnect material, which may be solder, to expand laterally toward adjacent interconnects.

Additional drawbacks and disadvantages may exist.

Disclosure of Invention

In one aspect, the present invention provides a semiconductor device assembly comprising: a first semiconductor device; a substrate; a first element comprising a thermally responsive material connected between the substrate and the first semiconductor device; wherein the first element is configured to apply a force to the first semiconductor device at a first predetermined temperature.

In another aspect, the present invention provides a semiconductor device assembly comprising: a first semiconductor device; a second semiconductor device; a plurality of interconnects electrically connecting the first semiconductor device and the second semiconductor device; and a first plurality of elements comprising a thermally responsive material connecting the first semiconductor device and the second semiconductor device, wherein the first plurality of elements are configured to exert a force at a predetermined temperature to reduce warpage of the first semiconductor device at the predetermined temperature or to reduce warpage of the second semiconductor device at the predetermined temperature.

In yet another aspect, the present invention provides a method of fabricating a semiconductor device assembly, comprising: providing a substrate; providing a first semiconductor device; connecting the first semiconductor device to the substrate with at least one first element comprising a thermally responsive material; and heating the semiconductor device assembly to a first predetermined temperature, wherein the at least one first element applies a force to reduce warpage of the first semiconductor device at the first predetermined temperature.

Drawings

Fig. 1 is a schematic diagram of an embodiment of a semiconductor device assembly including a semiconductor device connected to a substrate via a plurality of interconnects.

Fig. 2 is a schematic diagram of an embodiment of a semiconductor device assembly including a semiconductor device connected to a substrate via a plurality of interconnects and thermally responsive elements.

Fig. 3 is a schematic diagram of an embodiment of a semiconductor device assembly including a semiconductor device connected to a substrate via a plurality of interconnects and thermally responsive elements.

Fig. 4 is a schematic diagram of an embodiment of a semiconductor device assembly including two semiconductor devices and a substrate connected to each other via a plurality of interconnects and thermally responsive elements.

Fig. 5 is a schematic diagram of an embodiment of a thermally responsive element in a pattern on a semiconductor device.

Fig. 6 is a schematic diagram of an embodiment of a thermally responsive element in a pattern on a semiconductor device.

Fig. 7 is a schematic diagram of an embodiment of a thermally responsive element in a pattern on a semiconductor device.

Fig. 8 is a flow chart of an embodiment of a method of manufacturing a semiconductor device assembly.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure as defined by the appended claims.

Detailed Description

In the present disclosure, numerous specific details are discussed to provide a thorough and instructive description of embodiments of the present disclosure. One skilled in the art will recognize that the present disclosure may be practiced without one or more of the specific details. Well-known structures and/or operations often associated with semiconductor devices and semiconductor device packages may not be shown and/or may not be described in detail to avoid obscuring other aspects of the disclosure. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present disclosure.

The term "semiconductor device assembly" may refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates, which may include interposers, supports, and/or other suitable substrates. The semiconductor device assembly may be fabricated in, but not limited to, discrete package form, strip or matrix form, and/or wafer panel form. The term "semiconductor device" generally refers to a solid state device comprising a semiconductor material. The semiconductor device may include a semiconductor substrate, such as from a wafer or substrate, a wafer, a panel, or a single die. A semiconductor device may refer herein to a semiconductor die, but the semiconductor device is not limited to semiconductor dies.

As used herein, the terms "vertical," "lateral," "upper," and "lower" may refer to the relative directions or positions of features shown in the drawings in a semiconductor device and/or semiconductor device assembly. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be broadly construed to include semiconductor devices and/or semiconductor device assemblies having other orientations, such as upside down or tilted orientations, where top/bottom, above/below, up/down, and left/right may be interchanged depending on the orientation.

Various embodiments of the present disclosure relate to semiconductor devices, semiconductor device assemblies, semiconductor packages, semiconductor device packages, and methods of manufacturing and/or operating semiconductor devices.

Embodiments of the present disclosure are semiconductor device assemblies that include a first semiconductor device, a substrate, and a first element including a thermally responsive material connected between the substrate and the first semiconductor device. The first element is configured to apply a force to the first semiconductor device at a first determined temperature. The first semiconductor device may have warpage at a first determined temperature and the first element may be configured to reduce the warpage at the first determined temperature by applying a force to the first semiconductor device.

Embodiments of the present disclosure are semiconductor device assemblies including a first semiconductor device, a second semiconductor device, and a plurality of interconnects electrically connecting the first semiconductor device and the second semiconductor device. The semiconductor device assembly includes a first plurality of elements including a thermally responsive material connecting a first semiconductor device and a second semiconductor device. The first plurality of elements is configured to apply a force at a predetermined temperature to reduce warpage of the first semiconductor device at the predetermined temperature or to reduce warpage of the second semiconductor device at the predetermined temperature.

An embodiment of the present disclosure is a method of manufacturing a semiconductor device assembly, the method comprising providing a substrate and providing a first semiconductor device. The method includes connecting a first semiconductor device to a substrate with at least one first element comprising a thermally responsive material, and heating a semiconductor device assembly to a first predetermined temperature, wherein the at least one first element exerts a force to reduce warpage of the first semiconductor device at the first predetermined temperature.

Fig. 1 is a schematic diagram of a semiconductor device assembly 100. The semiconductor device assembly 100 includes a first semiconductor device 120 connected to a substrate 110 via a plurality of interconnects 130A, 130B, 130C. As will be appreciated by those skilled in the art having the benefit of this disclosure, the substrate 110 may be a semiconductor device. As shown in fig. 1, the first semiconductor device 120 may have warpage at a predetermined temperature. The predetermined temperature may be a temperature applied to the semiconductor device assembly 100 during processing. For example, the predetermined temperature may be, but is not limited to, the temperature to which the assembly is heated during the TCB process or during the reflow process.

The warpage of the first semiconductor device 120 at the predetermined temperature may stretch some of the interconnects 130A between the first semiconductor device 120 and the substrate 110. As will be appreciated by those skilled in the art having the benefit of this disclosure, stretching of the interconnect 130A may result in fracture of the interconnect 130A. As will be appreciated by those skilled in the art having the benefit of the present disclosure, warping of the first semiconductor device 120 at a predetermined temperature may also compress some of the interconnects 130C, causing the interconnects 130C to expand laterally, which may short between the interconnects 130C. As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the number, shape, size, and/or location of the interconnects 130A, 130B, 130C are shown for illustrative purposes and may vary. Likewise, the warpage of the first semiconductor device 120 is shown for illustrative purposes and may vary depending on the application, as will be appreciated by those skilled in the art having the benefit of the present disclosure.

Fig. 2 is a schematic diagram of a semiconductor device assembly 100. The semiconductor device assembly 100 includes a first semiconductor device 120 connected to a substrate 110 via a plurality of interconnects 130. As will be appreciated by those skilled in the art having the benefit of this disclosure, the substrate 110 may be a semiconductor device. As discussed herein, the first semiconductor device 120 and/or the substrate 110 may have warpage at a predetermined temperature that may be applied to the semiconductor device assembly 100 during processing. Warpage of the semiconductor device 120 and/or the substrate 110 can create improper interconnects 130 within the semiconductor device assembly 100. The semiconductor device assembly 100 includes a plurality of elements 140 connecting the first semiconductor device 120 and the substrate 110. The element 140 is configured to reduce warpage of the first semiconductor device 120 and/or the substrate 110. For example, the element 140 comprises a thermally responsive material that applies a force shown as arrow F1 to the first semiconductor device 120 and the substrate 110 at a predetermined temperature.

As will be appreciated by those skilled in the art having the benefit of this disclosure, the element 140 may comprise a variety of materials. For example, the element 140 may include, but is not limited to, a polymer or polymer mixture that undergoes further polymerization at certain temperatures to reduce the volume, causing the element 140 to shrink. Polyesters, polyimides, polyetherimides, polyacrylates, and polyphenols are examples of such polymers. Other polymers or polymer mixtures may be used to form the element 140, as will be appreciated by those skilled in the art having the benefit of this disclosure. The element 140 may comprise a thermally responsive material that contracts at or substantially near a predetermined temperature. The contraction of the elements 140 may exert a force, shown as arrow F1, that pulls the first semiconductor device 120 and the substrate 110 together at the location where the elements 140 are located. Alternatively, the element 140 may be configured to push the first semiconductor device 120 and the substrate 110 away from each other at a location where the element 140 is located as discussed herein.

As will be appreciated by those skilled in the art, the warpage of the first semiconductor device 120 and/or the substrate 110 at a predetermined temperature may be predetermined by various mechanisms. For example, the warpage of each element of the semiconductor device assembly 100 may be simulated using thermal shadow ripples (TSMs). The TSM may be used to determine potential locations of elements 140 comprising thermally responsive material to provide forces to one or more components of the semiconductor device assembly 100 to reduce or minimize warpage, thereby reducing interconnect 130 defects. Other mechanisms may be used to determine the potential location of the thermally responsive element 140 to reduce or minimize warpage.

Various patterns may be used to reduce warpage of the semiconductor device 120 and/or the substrate 110 as part of the semiconductor device assembly 100. Fig. 5 shows a schematic diagram of an embodiment of a thermally responsive element 140 in a pattern on a semiconductor device 120. The thermally responsive element 140 may be positioned in each corner of the semiconductor device 120. The thermally responsive element 140 is connected to another element in the semiconductor device assembly 100 and is configured to exert a force by expanding or contracting to reduce or minimize warpage of the semiconductor device 120 and/or adjacent components of the semiconductor device assembly 100. As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the size, shape, location, and/or number of thermally responsive elements 140 are shown for illustrative purposes and may vary depending on the application.

Fig. 6 shows a schematic diagram of an embodiment of a thermally responsive element 140 in a pattern on a semiconductor device 120. The thermally responsive element 140 may include a longitudinal element 140 positioned along an edge of the semiconductor device 120. The thermally responsive element 140 is connected to another component in the semiconductor device assembly 100, such as the substrate 110 or another semiconductor device, and is configured to exert a force by expanding or contracting to reduce or minimize warpage of the semiconductor device 120 and/or adjacent components of the semiconductor device assembly 100. As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the size, shape, location, and/or number of thermally responsive elements 140 are shown for illustrative purposes and may vary depending on the application.

Fig. 3 is a schematic diagram of a semiconductor device assembly 100. The semiconductor device assembly 100 includes a first semiconductor device 120 connected to a substrate 110 via a plurality of interconnects 130. As will be appreciated by those skilled in the art having the benefit of this disclosure, the substrate 110 may be a semiconductor device. As discussed herein, the first semiconductor device 120 and/or the substrate 110 may have warpage at a predetermined temperature that may be applied to the semiconductor device assembly 100 during processing. The semiconductor device assembly 100 includes a first plurality of elements 140 connecting the first semiconductor device 120 with the substrate 110 and a second plurality of elements 150 connecting the first semiconductor device 120 with the substrate 110.

The first plurality of elements 140 and the second plurality of elements 150 are configured to reduce warpage of the first semiconductor device 120 and/or the substrate 110. For example, the first plurality of elements 140 comprises a thermally responsive material configured to apply a force, shown as arrow F1, to the first semiconductor device 120 and the substrate 110 at a first predetermined temperature. Likewise, the second plurality of elements 150 may comprise a thermally responsive material configured to apply a force, shown as arrow F2, to the first semiconductor device 120 and the substrate 110 at a first predetermined temperature. Alternatively, the second plurality of elements 150 may comprise a thermally responsive material configured to apply a force, shown as arrow F2, to the first semiconductor device 120 and the substrate 110 at a second predetermined temperature.

As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the first and second plurality of elements 140, 150 may comprise a variety of materials. For example, the contracting elements 140 may comprise a polymer or polymer mixture that is further polymerized at certain temperatures to reduce the volume, as discussed above. Element 150 may include a polymer blend with thermally labile particles. Thermally unstable particles, which may be liquid or solid, may undergo a phase change (i.e., change from solid or liquid to gas) or degradation to create voids at certain elevated temperatures, which causes the element 150 to expand. The first plurality of elements 140 may comprise a thermally responsive material configured to contract at or substantially near a predetermined temperature. The contraction of the elements 140 may exert a force, shown as arrow F1, that pulls the first semiconductor device 120 and the substrate 110 together at the location where the elements 140 are located. The second plurality of elements 150 may comprise a thermally responsive material configured to expand at or substantially near a first predetermined temperature. Alternatively, the second plurality of elements 150 may comprise a thermally responsive material configured to expand at or substantially near a second predetermined temperature. The expansion of the element 150 may exert a force, shown as arrow F2, that pushes the first semiconductor device 120 and the substrate 110 away from each other at the location where the element 150 is located.

As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the number, size, shape, location, and/or configuration of the first and second pluralities of elements 140, 150 may vary depending on the application. For example, the first plurality of elements 140 and the second plurality of elements 150 may apply forces in the same direction, i.e., two contractions or two expansions, to reduce or minimize warpage of the semiconductor device 120 and/or adjacent components, but may be configured to apply such forces at different temperatures. The first plurality of elements may contract or expand at or substantially near a first predetermined temperature, and the second plurality of elements may contract or expand at or substantially near a second predetermined temperature. Likewise, the first and second plurality of elements may be configured to apply different amounts of force than each other.

The combination of the two thermally responsive elements 140, 150 may be used to reduce or minimize warpage of the semiconductor device 120 and/or adjacent components in the semiconductor device assembly 100. The first plurality of thermally responsive elements 140 and the second thermally responsive element 150 may be positioned in various configurations and/or patterns depending on the desired result and/or application. Fig. 7 shows a schematic diagram of an embodiment of a first plurality 140 and a second plurality 150 of thermally responsive elements on a semiconductor device 120. The first plurality of thermally responsive elements 140 may each be positioned in a corner of the semiconductor device 120, while the second plurality of thermally responsive elements 150 are positioned between corners of the semiconductor device 120. The first and second pluralities of thermally responsive elements 140, 150 are connected to another component in the semiconductor device assembly 100 and are configured to exert a force by expanding or contracting to reduce or minimize warpage of the semiconductor device 120 and/or adjacent components of the semiconductor device assembly 100. As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the size, shape, location, and/or number of thermally responsive elements 140, 150 are shown for illustrative purposes and may vary depending on the application.

Fig. 4 is a schematic diagram of a semiconductor device assembly 100. The semiconductor device assembly 100 includes a first semiconductor device 120A connected to a substrate 110 via a plurality of interconnects 130. As discussed herein, the first semiconductor device 120 may have warpage at a predetermined temperature that may be applied to the semiconductor device assembly 100 during processing. The semiconductor device assembly 100 also includes a second semiconductor device 120B connected to the first semiconductor device 120A via a plurality of interconnects 130.

The semiconductor device assembly 100 includes a first plurality of elements 140A and a second plurality of elements 160 connecting the first semiconductor device 120A with the substrate 110. The semiconductor device assembly 100 includes a third plurality of elements 140B and a fourth plurality of elements 150 connecting the first semiconductor device 120A and the second semiconductor device 120B. As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the number, size, shape, and/or configuration of semiconductor devices 120A, 120B are shown for illustrative purposes and may vary depending on the application. For example, the semiconductor device assembly 100 may include more than two semiconductor devices 120A, 120B.

The first plurality of elements 140A, the second plurality of elements 160, the third plurality of elements 140B, and the fourth plurality of elements 150 are individually or in combination configured to reduce warpage of the first semiconductor device 120A, the second semiconductor device 120B, and/or the substrate 110. As will be appreciated by those skilled in the art having the benefit of this disclosure, the substrate 110 may be a semiconductor device.

The first plurality of elements 140A comprises a thermally responsive material configured to apply a force, shown as arrow F1, to the first semiconductor device 120A and the substrate 110 at a first predetermined temperature. Due to the contraction of the elements 140, the force F1 may pull the first semiconductor device 120A and the substrate 110 together at the location of each of the first plurality of elements 140A. The second plurality of elements 160 comprises a thermally responsive material configured to apply a force, shown as arrow F3, to the first semiconductor device 120A and the substrate 110 at a second predetermined temperature. Due to the contraction of the elements 160, the force F3 may pull the first semiconductor device 120A and the substrate 110 together at the location of each of the second plurality of elements 160

The third plurality of elements 140B may be identical to the first plurality of elements 140A. Thus, the third plurality of elements 140 may comprise a thermally responsive material configured to apply a force shown as arrow F1 to the first and second semiconductor devices 120A and 120B. The fourth plurality of elements 150 comprises a thermally responsive material configured to apply a force, shown as arrow F2, to the first semiconductor device 120A and the second semiconductor device 120B at a predetermined temperature. The predetermined temperature may be a first predetermined temperature, a second predetermined temperature, or a third predetermined temperature. Due to the expansion of the elements 150, the force F2 may push the first semiconductor device 120A and the second semiconductor device 120B away from each other at the location of each of the fourth plurality of elements 150.

As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the number, size, location, and configuration of the thermally responsive elements 140A, 140B, 150, 160 to minimize or reduce warpage of the components of the semiconductor device assembly 100 are shown for illustrative purposes and may vary. For example, a thermally responsive element between two adjacent components of the semiconductor device assembly 100 may contract, expand, or multiple components may be used with some expansion and some contraction. The thermally responsive elements may be configured to exert the force at a single predetermined temperature or may be configured such that portions of the thermally responsive elements exert the force at or substantially near the first temperature, while other thermally responsive elements exert the force at or substantially near the second or even third temperature. Additionally, due to the rate of expansion, rate of contraction, and/or amount of material comprising the thermally responsive elements, individual thermally responsive elements in the semiconductor device assembly 100 can be configured to apply different amounts of force to adjacent components. Other variations may exist as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure.

Fig. 8 is a flow chart of an embodiment of a method 200 of manufacturing a semiconductor device assembly. The method 200 includes providing a substrate at 210. The substrate may be a semiconductor device as discussed herein. The method 200 includes providing a first semiconductor device at 220, and connecting the first semiconductor device to a substrate with at least one first element comprising a thermally responsive material at 230. The method 200 includes heating the semiconductor device assembly to a first predetermined temperature at 240, wherein the at least one first element applies a force to reduce warpage of the first semiconductor device at the first predetermined temperature.

The method 200 may include determining a warpage of the first semiconductor device at a first predetermined temperature at 245. At 250, the method 200 may include positioning at least one element to reduce warpage of the first semiconductor device based on determining the warpage. The method 200 may include positioning at 255 at least one second element including a thermally responsive material to reduce warpage based on determining the warpage, and connecting 260 the first semiconductor device to the substrate with the at least one second element. The method 200 may include heating the semiconductor device assembly to a second predetermined temperature at 265, wherein the at least one second element applies a force to reduce warpage of the first semiconductor device at the second predetermined temperature.

The thermally responsive element can retain portions of the semiconductor device assembly after reducing or minimizing warpage. Alternatively, the thermally responsive element may be removed from the semiconductor device assembly after the temperature of the semiconductor device assembly has been reduced below the first predetermined temperature. The method 200 may include reducing the temperature below a first predetermined temperature and removing at least one first element from the semiconductor device assembly at 270. For example, a solvent may be used to dissolve the thermally responsive elements from the semiconductor device assembly. As another example, the thermally responsive element may be mechanically removed from between components of the semiconductor device assembly. As will be appreciated by those skilled in the art having the benefit of the present disclosure, various mechanisms may be used as desired to remove the thermally responsive element from the semiconductor device assembly.

Although the present disclosure has been described with respect to certain embodiments, other embodiments apparent to those skilled in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of the present disclosure. The disclosure may encompass other embodiments not explicitly shown or described herein. Accordingly, the scope of the disclosure is to be defined only by reference to the following claims and their equivalents.