阅读说明：本技术 半导体分隔装置 (Semiconductor separating device ) 是由 I·D·裘兰德 D·里奇 G·哈里斯 于 2019-06-24 设计创作，主要内容包括：本文描述一种半导体基板堆,其包括：在堆中布置的多个半导体基板,其中半导体基板包括多个相对的面对表面,其中相邻的半导体基板的所述面对表面由间隙隔开,每个半导体基板在所述堆的暴露边缘处具有边缘表面。间隔件附接到至少一个半导体基板中的每一者的多个面对表面中的一者上,并在相邻的半导体基板之间延伸以限定所述间隙并掩蔽每个各自半导体基板的中心部分。(Described herein is a semiconductor substrate stack comprising: a plurality of semiconductor substrates arranged in a stack, wherein a semiconductor substrate comprises a plurality of opposing facing surfaces, wherein the facing surfaces of adjacent semiconductor substrates are separated by a gap, each semiconductor substrate having an edge surface at an exposed edge of the stack. Spacers are attached to one of the plurality of facing surfaces of each of the at least one semiconductor substrate and extend between adjacent semiconductor substrates to define the gap and mask a central portion of each respective semiconductor substrate.)

1. A semiconductor substrate stack comprising:

a plurality of semiconductor substrates arranged in a stack, wherein opposing facing surfaces of adjacent semiconductor substrates are separated by a gap, each semiconductor substrate having an edge surface at an exposed edge of the stack;

a spacer attached to one of the facing surfaces of each of the plurality of semiconductor substrates and extending between adjacent semiconductor substrates to define the gap and mask a central portion of each respective semiconductor substrate.

2. The semiconductor substrate stack of claim 1, wherein the spacer is separated from the exposed edge.

3. The semiconductor die stack of claim 1, wherein the spacer is bonded to the opposing surface of each semiconductor substrate.

4. The semiconductor substrate stack of claim 1, wherein the spacer is a photoresist.

5. The semiconductor substrate stack of claim 1, wherein the spacer has a thickness greater than 5 microns.

6. The semiconductor substrate stack of claim 1, wherein the spacer has a thickness of less than 100 microns.

7. The semiconductor substrate stack of claim 1, wherein one or both of the exposed edge and the upper facing surface and the lower opposing surface of each semiconductor substrate comprise a coating.

8. The semiconductor substrate stack of claim 7, wherein the coating is anti-reflective.

9. A semiconductor substrate having a plurality of molds arranged across the facing surface of the semiconductor substrate and defined by parting lines, each of the plurality of molds including at least one semiconductor device and a spacer.

10. The semiconductor substrate of claim 9, wherein each spacer comprises an elongated body having a longitudinal axis.

11. The semiconductor substrate of claim 9, wherein each spacer is attached to at least one of the plurality of dies.

12. The semiconductor substrate of claim 11, wherein the spacer extends over more than one of the plurality of dies.

13. The semiconductor substrate according to claim 9, wherein each spacer is included in a range of one of the plurality of the molds and does not cross one of the plurality of the parting lines.

14. A semiconductor device substrate, comprising:

a substrate including at least one semiconductor device,

wherein the edge region of the substrate may comprise at least one layer of deposition material defined by wall structures located on the surface of the substrate.

15. The semiconductor device substrate of claim 14, comprising a package in which the semiconductor is housed for use.

16. The semiconductor device substrate of claim 15, wherein the edge region comprises an edge and/or a facing surface of the substrate.

17. A method of coating an exposed edge of a semiconductor substrate, the method comprising:

fabricating at least one semiconductor device on a central portion of a semiconductor substrate;

positioning at least one spacer on at least one substrate;

arranging a plurality of substrates to provide a stack of substrates, wherein opposing surfaces of at least two adjacent semiconductor substrates are separated by a gap, each semiconductor substrate having an edge surface arranged at an exposed edge of the stack, wherein the spacer defines the gap and masks the central portion; and

depositing material on the exposed edge.

18. The coating method according to claim 17, wherein the deposition of the material on the exposed edge is achieved by evaporation or sputtering.

19. The coating method of claim 17, further comprising:

separating the stack after depositing the material;

each mold is encapsulated within a device package without removing the spacers.

Technical Field

The invention relates to a semiconductor spacer and a method of providing a stack of semiconductor substrates using the semiconductor spacer. In particular, the invention provides one or more semiconductor spacers in the form of spacers on the surface of the substrate, which can be used to separate adjacent substrates.

Background

Some semiconductor devices require material to be deposited onto the edge surfaces. Such deposition may be achieved using a number of known techniques, such as evaporation or sputtering, in which the apparatus is loaded into a suitable apparatus and the material is deposited. The present invention seeks to provide an improved edge deposition process.

Disclosure of Invention

The present invention provides a stack of semiconductor substrates, a semiconductor device substrate, and a method of coating an edge of a semiconductor substrate according to the appended claims.

A semiconductor substrate stack is disclosed herein. The semiconductor substrate stack includes: a plurality of semiconductor substrates arranged in a stack in which opposing facing surfaces of adjacent semiconductor substrates are separated by a gap, each semiconductor substrate having an edge surface at an exposed edge of the stack. The spacer may be attached to one of the plurality of facing surfaces of each of the plurality of semiconductor substrates and extend between adjacent semiconductor substrates to define the gap and mask a central portion of each respective semiconductor substrate.

Providing spacers between adjacent substrates allows multiple substrates to be processed in a single stack. Such processing may include depositing material on the exposed edge surfaces.

The spacer may be fixedly attached. Fixedly attached spacers are provided to allow the substrates to be stacked in a more convenient manner. In addition, the fixedly attached spacers may also provide a mask for masking the central portion of the substrate and any devices located thereon from subsequent process steps, which may include depositing material on the exposed edge surfaces.

These substrates may be part of a complete semiconductor wafer and may include two or more dies. Each substrate may include a device surface on which one or more devices are fabricated; an opposing back surface and one or more exposed edge surfaces defining an edge of the substrate and extending between the device surface and the opposing back surface. The device surface and the back surface may be referred to as an upper surface and a lower surface, and vice versa. The spacer may be fixedly attached to the device surface, but may alternatively or additionally be attached to the opposite rear surface. The spacer may include a contact surface attached to the substrate and an opposing abutment surface abutting against a corresponding surface of an adjacent substrate.

The spacer may be separated from the exposed edge. Thus, the spacer may be placed at a distance from the exposed edge to provide a strip of semiconductor facing surface between the spacer and the exposed edge.

The spacer may be bonded to one of the facing surfaces of each semiconductor substrate. The bonding may be achieved directly between the substrate and the spacer. Alternatively, the substrate may include one or more intermediate layers to aid in adhesion.

The spacers may be photoresist. The spacers may be a negative photoresist. The spacer may be an epoxy. The spacer may be SU-8.

The spacer may have a thickness greater than 5 microns. The spacer may be less than 100 microns thick.

The exposed edge, and one or both of the device surface and the opposing surface of each semiconductor substrate may include a coating. For example, the coating may cover a facing surface adjacent to the exposed edge, or at least a portion of the spacer.

The coating may continuously traverse all of the exposed edges, spacers, and one or both of the device surface and the opposing surface of each semiconductor substrate. The spacers may be referred to as wall structures of the substrate. The wall structure may separate one or more surfaces of the substrate.

The coating may be antireflective. In some embodiments, the coating may be reflective.

Further described herein is a semiconductor substrate having a plurality of dies arranged across a surface semiconductor substrate. Each of the plurality of dies may be defined by a parting line. Each mold may include at least one semiconductor device and a spacer.

These spacers may pass through the parting line. Each substrate may have a plurality of spacers distributed across the substrate surface. The spacer may comprise a plurality of spacer pads. The plurality of spacers and/or the plurality of spacer pads may have a common height.

Each spacer may include an elongated body having a longitudinal axis. The elongated body may be spaced apart from the exposed edge along a length of the spacer. The spacing may be substantially uniform along the length of the spacer to provide an exposed substrate strip along the exposed edge.

Each spacer may be attached to at least one of the plurality of molds. The spacers may extend across a plurality of semiconductor dies. Each spacer may be separated from an adjacent spacer on all sides. Each mold may have a single spacer contained within the mold boundary. Each mold may have a plurality of spacers.

Further described herein is a semiconductor device comprising: a substrate comprising at least one semiconductor device. The edge region of the substrate may comprise at least one layer of deposition material, the deposition material being defined by wall structures. The wall structure may be provided by spacers as described herein and have all of these features, alone or in combination.

The semiconductor device may include a package in which a substrate is accommodated for use.

The edge region may comprise an exposed edge and/or a facing surface of the substrate.

Further described herein is a method of coating an exposed edge of a semiconductor die, the method comprising: fabricating at least one semiconductor device on a central portion of a semiconductor substrate; positioning at least one spacer on at least one mold; stacking the individual molds to provide a stack of molds with facing surfaces of at least two adjacent semiconductor molds separated by a gap, each semiconductor mold having an edge surface disposed at an exposed edge of the stack, wherein the spacer defines the gap and masks the central portion; depositing material on the exposed edge.

The deposition of the material on the exposed edge may be achieved by evaporation or sputtering.

The method may further comprise: the stack is separated after depositing the material and each mold is encapsulated within a device package without removing the spacers. The method may further include cutting the substrate to provide a plurality of dies.

It will be understood by those skilled in the art that, unless mutually exclusive, features described herein in relation to any one of the above aspects may be applied to any other aspect, mutatis mutandis. Furthermore, any feature described herein may be applied to any aspect and/or in combination with any other feature described herein, unless mutually exclusive.

Drawings

Various embodiments of semiconductor substrates, corresponding substrate stacks and related fabrication processes will now be described with reference to the accompanying drawings, in which:

fig. 1 shows a semiconductor substrate stack with a plurality of semiconductor substrates, which are separated by spacers;

FIG. 2 shows a single layer of the stack shown in FIG. 1;

FIG. 3 shows another arrangement of spacers;

FIG. 4 shows the individual molds after disassembly of the stack and rupture of one of the stack substrates; and the number of the first and second groups,

fig. 5 provides a flow chart illustrating the main method steps for depositing material on exposed edge regions of a plurality of semiconductor substrates.

Detailed Description

Fig. 1 shows a schematic view of a semiconductor substrate stack 10, said semiconductor substrate stack 10 comprising: a plurality of semiconductor substrates 12 arranged in a stack 10, wherein facing surfaces of adjacent semiconductor substrates 12 are separated by a gap 14. Each semiconductor substrate 12 has an edge surface 22 disposed at an exposed surface of the stack 10. The plurality of semiconductor substrates 12 have spacers 16 on their surfaces. The spacers 16 define the gaps 14 and may mask a central portion of each respective semiconductor substrate 12. It should be understood that the uppermost layer of the stack has been removed in the representation of fig. 1 to more clearly show the spacers 16. It should also be understood that the representations provided by the figures are schematic and that the dimensional proportions of the respective components relative to each other are not necessarily correctly scaled.

Each spacer 16 may be fixedly attached to a surface 18 of the substrate 12. Thus, the spacers 16 are attached to the surface 18, and the attachment will not become detached during normal processing of the substrate 12 or during removal of the mold from the substrate 12, and will resist subsequent processing steps. To provide the attachment, the spacer 16 may be adhered to the surface 18 by means of an adhesive bond formed between the spacer 16 and the surface 18.

In some embodiments, the spacer 16 may be a surface feature of the substrate 12 and/or integrally formed with the substrate 12. The materials of the spacer 16 and the semiconductor substrate 12 may have suitable properties that allow direct bonding. Alternatively or additionally, one or more intermediate layers or coatings may be provided on the semiconductor substrate before the spacers are applied.

The stack 10 shown in fig. 1 includes a plurality of stacked substrates 12 with a separate substrate 12 in each layer of the stack 10. The substrate 12 may have a predetermined parting line 28(die lines) that defines each of the plurality of dies. The parting line 28 may be marked on the substrate 12 in some way or may simply explain the layout of the devices fabricated on the mold. In the latter case, the split line may be defined by a virtual/imaginary split line. The parting line 28 defines a cut line along which the substrate is diced to provide individual dies 26. The cutting is typically performed after the stack is disassembled, but this may not be the case. Thus, the individual layers of the stack may comprise a single sheet of semiconductor substrate 26, or individual substrate portions or molds 12.

Each mold 12 may include a spacer surface 18, with the spacers 16 disposed on the spacer surface 18. The spacer surface 18 may be a device surface on which one or more devices (not shown) are fabricated. Each mold will also include an opposing back surface, which is obscured in these figures. The spacer surface 18 and the opposing back surface provide flat major surfaces of the substrate 12 and are separated by the thickness of the substrate 12. The perimeter of the substrate has one or more exposed edge surfaces 22 that extend between the device surface 18 and the opposing back surface 20. The device surface and the opposing back surface may be referred to as the planar or facing surfaces of the substrate. Further, the spacer surface and/or the device surface and the opposing back surface may be referred to as an upper surface or a lower surface, or vice versa.

Each spacer 16 includes a contact surface attached to the spacer surface 18 of the substrate 12 and an opposing abutment surface 24, the opposing abutment surface 24 abutting against a corresponding opposing surface of an adjacent substrate 12. Thus, the spacers 16 are sandwiched between the opposing surfaces of adjacent substrates 12 and separate the adjacent substrates 12 by the thickness of the spacers 16.

Each spacer 16 extends across the surface of the respective substrate 12 and has a contact surface area x, y and a thickness z according to the directions shown in fig. 1. The size of the contact surface area will be sufficient to provide the required adhesion and structural integrity for the spacer 16 to withstand subsequent processing steps without separating from the substrate 12. For example, the subsequent processing steps may include device fabrication steps or one or more edge deposition processes. The general dimensions of the spacer 16 should also be sufficient to withstand any compressive forces applied when assembling the stack. Of course, this will depend on the material from which the spacer 16 is made and the compressive force applied, as well as other variables that will be apparent to those skilled in the art.

The thickness of the spacer 16 will determine the spacing between the layers of the stack 10. In some embodiments, the contact and abutment surfaces 24 of the spacer will be evenly spaced, i.e., the spacer 16 may have a uniform thickness. Providing a uniform thickness (within ordinary tolerances) helps to achieve a uniform abutment between the surfaces of the opposing molds or substrates, which may improve the masking function of these spacers. Typically, the thickness of the spacer will be less than the width or length of the spacer.

These spacers may have a thickness of between 5 and 100 microns. The spacing from the exposed edge of the substrate may be up to 100 microns. The spacer may be flush with (or may overhang) the edge of the exposed edge. The lateral dimension of the spacers extending from the exposed edge in the x-direction may be between 20 and 200 microns. As mentioned above, the length of the spacer extending in the y-direction parallel to the exposed edge may extend the full length of the substrate or a mold portion thereof. The full length may be between 13mm and 17 mm. For example, for a segmented spacer comprising a plurality of spacers, the y-dimension (y-dimension) may extend between 0.25mm and 9 mm.

In the embodiment shown in fig. 1, there are a plurality of spacers distributed across the surface of the substrate 12 to allow the substrate to be properly supported. In the embodiment shown in fig. 1, there are two spacers 16 placed near the exposed edges on opposite sides of the substrate. The spacing of each spacer 16 may be equal to the distance between the respective exposed edges 22. It should be understood that other arrangements of the spacers 16 may be provided as desired.

These spacers 16 may be placed similarly to each substrate 12 within the stack 10 such that they are vertically aligned to provide a continuous support structure throughout the entire stack 10.

Some of these spacers 16 may be arranged to provide a masking function to protect the central portion of the substrate from material being deposited on the central portion during the edge deposition process. Some of the spacers 16 may not require a masking function, but they are necessary to provide evenly distributed support for the substrates 12 within the stack.

As shown in fig. 3, the spacers 16 may be provided by a single structure that extends across the surface of the substrate and traverses parting lines and respective molds 26, as shown on the right hand side of fig. 3. Alternatively or additionally, the spacers 16 may be provided by a distributed array of spacer pads 16a, 16b, 16c, wherein each mold 12 has one or more individual spacers 16 that are spaced apart from adjacent spacers 16 on the same or adjacent molds 12. The spacing between the spacers 16a, 16b, 16c may be such that the parting line 28 defining the mold 26 is not traversed by the spacers 16. Providing separate spacers in this manner may help simplify the cutting process, as these spacers 16 would not need to be cut.

The parting line shown in the drawings provides a plurality of molds that are elongated with major sides abutting adjacent molds. The minor sides or ends of the mold may provide exposed edge surfaces of the substrate on which material may be deposited.

The distributed array of spacers 16 or spacers 16a, 16b, 16c may be arranged in a linear array, with the spacers 16 and/or spacers 16a, 16b, 16c disposed in end-to-end relationship with one another. The spacers 16 and/or spacer pads 16a, 16b, 16c may be arranged in rows with one another or staggered along the linear array to offset the exposed edge 22 by different amounts.

It should be appreciated that the spacer 16 may be any suitable shape to perform the necessary functions described herein. For example, the spacer 16 may have a footprint that is polygonal or circular. The peripheral wall of the spacer 16 defining the thickness may be perpendicular or oblique to the planar surface of the substrate.

The size of the spacers 16 may be predetermined based on one or more of the following factors: the available area on which they can sit; they will exert parasitic effects (parasiticetffect) on any device properties and mechanical properties of the materials used. For example, providing larger sized spacers may be preferable from a protection and robustness (robustness) point of view, but this may increase stress and parasitic capacitance on the substrate, both of which may have a detrimental effect on device performance.

Fig. 4 shows the substrate 12 of fig. 3 after cutting. Thus, fig. 3 shows a single mold 26 with a plurality of spacers on the surface of the mold. The spacer 16 on the right has been cut from the substrate 12, and the spacer 16a on the left is separated from the parting line 28 and does not pass through the parting line 28, so no cutting is required.

Also shown in fig. 4 is material 32 that has been deposited on exposed edge 22. The deposition is schematically illustrated in fig. 1 by arrows 30 and may be achieved by any suitable means, such as evaporation. The deposition may be directional and the direction of deposition may be such that one or more surfaces along the exposed edge are coated. Thus, after deposition, one or more of the exposed edge and the facing surface, the opposite rear surface and the outwardly facing surface of the wall structure provided by the spacer may have material deposited thereon. The deposited layer may be continuous such that it extends uninterrupted from one surface to the next.

The material for deposition on the edge of the stack may be any desired material. The edge material may be a dielectric material (single layer or combination of multiple layers) with a thickness designed to produce reflective or anti-reflective properties (typically tens to hundreds of nanometers thick). Some examples of deposition materials may include: TiO 2₂、SiO₂、Ta₂O₅、Si、SiON、Si₃N₄。

The spacer 16 shown in the drawings is a generally elongated structure having a longitudinal axis. The longitudinal axes may be parallel to the exposed edges of the respective mold or stack so that they are separated by a uniform gap that provides an exposed area of the substrate surface (typically a strip) along the length of the substrate 12 in the edge region. The size and shape of the exposed area may be predetermined to provide a suitable area for the edge material or coating.

The contact between the abutment surface 22 of the spacer 16 and the adjacent substrate 12 in the stack is sufficient to provide isolation between the adjacent substrates. In addition to this, the spacers 16 may provide a mask for masking the central portion of the substrate and/or stencil. The central portion may be considered to be any portion on the inside of the spacer 16, such as the footprint area of any device located on the mold 26.

The term "mask" as used herein does not mean that the spacer 16 covers the device or another feature fabricated on the surface of the substrate 12 or mold 26. However, it will be understood from the description that in some instances there may be some coverage of one or more surface features or areas. That is, there may be partial or complete overlap of one or more device features. The term "mask" is primarily used to denote a wall structure located near an exposed edge in an assembled stack. Thus, the mask may mask the central portion by limiting or preventing line of sight from outside the stack on the exposed edge side from entering the central portion or one or more device features.

One reason for providing a mask in this way is to isolate the edge region for further processing steps. For example, it may be desirable to deposit material on a portion of the exposed edge region without contaminating the central portion of the mold, as described below.

To aid in the abutting and masking properties of the spacer 16, the spacer may include a compliant material that can be deformed under pressure within the stack.

It should be understood that the placement of the spacers 16 may be determined primarily based on masking requirements rather than spacing requirements. Therefore, the contact surface of the spacer 16 or the distribution of the spacer 16 may be affected by the masking property and the area of the region to be shielded. Furthermore, the thickness of the spacer may be determined by the necessary spacing necessary to allow for a suitable material thickness or coverage on the exposed edge. That is, if the substrates are too close together, shadows may be present on one or more layers, which may result in poor material deposition on the exposed edges.

The substrate/mold may be any substrate/mold known in the art for semiconductor devices. Thus, the substrate/mold may comprise, for example, silicon, gallium arsenide, or indium phosphide, among others. The substrate/mold may include one or more layers, features or doped regions arranged to provide one or more semiconductor devices as is known in the art. For purposes of description, these layers and features may be considered part of the substrate/mold. In addition, the substrate and the mold may be regarded as a substrate for carrying the spacer.

The substrate may be considered as a planar structure having X and Y dimensions on a planar surface, the Z dimension representing the height shown. The substrate typically has a thickness/height of less than 0.5 mm.

The substrates 12 within the stack 10 may be aligned in the Z-axis so as to directly overlie one another. Alternatively, these exposed edges may be staggered in the Z-axis to reveal more of the substrate edge area that needs to be coated. The staggered arrangement may provide a stepped configuration (cascade formation) for the stack.

Each substrate and/or mold may include a plurality of semiconductor devices. A plurality of semiconductor devices may be consistently fabricated on a substrate before the substrate is diced to provide individual semiconductor dies in a conventional manner. The semiconductor die can then be individually packaged for end use as is well known in the art. The spacers 16 may be added to the substrate before, during or after the manufacture of these devices.

The material used for the spacer 16 may be determined by the particular application and processing steps that the spacer 16 must undergo during device fabrication, as well as the post-processing steps that the spacer provides protection for the central portion of the mold. Typically, these spacers 16 will be made of the same material and assembled at the same time. The spacers 16 may be made of a low dielectric constant material to minimize the impact on RF characteristics (RF behaviour) where applicable, be thermally stable at typical processing temperatures (possibly up to 320 ℃) and provide good adhesion to the host material. A suitable material may be photoresist (photoresist). The photoresist may be an epoxy. For example, the photoresist may be SU-8 photoresist supplied by MicroChem corporation, see the website http:// www.microchem.com/Prod-SU8. htm.

These spacers 16 may be fabricated using standard techniques and materials known in the semiconductor manufacturing industry. The manufacturing point when introducing the spacer 16 may be application specific, but it is envisaged that the spacer may be held in place at the time of post-processing and may remain in the device during use. This is particularly true when using materials such as SU-8 photoresist, which are generally difficult to remove.

One or more adhesive coatings may be applied to the substrate prior to applying the spacer. The bond coat will depend on the materials of the spacer and substrate, but suitable combinations are generally known in the art.

Fig. 5 shows a flow chart illustrating the main steps in the manufacturing method of a semiconductor substrate stack. In step 501, a plurality of substrates having at least one semiconductor device are provided. The plurality of substrates may be an integral part of a semiconductor wafer, and the semiconductor devices may be any semiconductor devices known in the art. These substrates may have molds in multiple designs distributed across the surface of the substrate. At step 502, a plurality of spacers are provided on each substrate. These spacers may be similar to those described above, relating to fig. 1-4. These spacers may be provided by negative tone photoresist (negative photoresist) as is well known in the art. In step 503, the substrates are stacked together such that adjacent substrates are contacted by spacers that provide a separating gap between opposing surfaces of the substrates. The stack may be facilitated by a suitable mechanism (e.g., a clamp) in which the substrates may be loaded and/or clamped. At step 504, the stack may have one or more materials deposited to an exposed edge of the stack. The deposited material may be any desired material and may include, for example, a reflective coating or an anti-reflective coating. The material may be deposited using any known technique, such as evaporation or sputtering. By way of example, the direction of deposition is shown in fig. 1 as arrow 30.

It should be appreciated that first step 501 and second step 502 may be performed in any order of succession, and that providing the spacers may be performed before providing the one or more semiconductor devices, or as an intermediate step in providing the one or more semiconductor devices.

Subsequent processing steps may include removing a plurality of substrates from the stack. The substrates are cut into a plurality of dies according to a predetermined parting line. Once these substrates/dies are separated from the stack and cut (where appropriate), the individual substrates/dies can be encapsulated. These spacers may or may not be removed prior to encapsulation.

These substrates and devices may be semiconductor devices comprising: a substrate comprising at least one semiconductor device, wherein an edge region of the substrate comprises at least one layer of a deposition material, which deposition material is defined by wall structures in the form of spacers.

The semiconductor device may be housed in a package to allow its use in an electronic apparatus, as is well known in the art.

It is to be understood that the present invention is not limited to the above-described embodiments, and various modifications and improvements may be made without departing from the inventive concept described herein. Any feature may be used alone or in combination with any other feature or features unless mutually exclusive, and the disclosure herein extends to and includes all combinations and subcombinations of one or more features described herein.