阅读说明：本技术 一种半导体元件及其形成方法 (Semiconductor element and forming method thereof ) 是由 王茂盈 黄沛霖 于 2018-08-20 设计创作，主要内容包括：本公开提供一种半导体元件及其形成方法。该半导体元件包括一第一晶粒及一导电层。该第一晶粒经配置以在一方向上与该半导体元件外部的一第二晶粒接合。该导电层在该方向上位于该第一晶粒及该第二晶粒之间,经配置以实现一参考接地。(The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first die and a conductive layer. The first die is configured to bond in a direction with a second die external to the semiconductor device. The conductive layer is located between the first die and the second die in the direction and is configured to implement a ground reference.)

1. A semiconductor component, comprising:

a first die configured to be bonded in a direction to a second die outside the semiconductor device; and

a conductive layer disposed in the direction and between the first die and the second die, configured to implement a ground reference.

2. The semiconductor device of claim 1, wherein the second die is configured to engage the first die and define a projected area by projecting the second die onto the first die, and the conductive layer occupies the projected area.

3. The semiconductor element according to claim 2, further comprising:

a redistribution structure configured to serve as a trace of the first die, surrounding and covering the conductive layer.

4. The semiconductor device as defined in claim 3, wherein the conductive layer is a first conductive layer, and wherein the redistribution structure comprises:

a second conductive layer configured to be electrically isolated from the first conductive layer when the second conductive layer transmits a signal other than the reference ground.

5. The semiconductor device as defined in claim 3, wherein the conductive layer is a first conductive layer, and wherein the redistribution structure comprises:

a second conductive layer configured to be coupled to the first conductive layer when the second conductive layer conveys the reference ground.

6. The semiconductor device as defined in claim 5, wherein the redistribution structure further comprises a dielectric layer over the conductive layer, wherein the semiconductor device further comprises:

a plug disposed in the dielectric layer configured to couple the first conductive layer to the second conductive layer.

7. The semiconductor device of claim 1, wherein the second die is configured to engage the first die and define a projected area by projecting the second die onto the first die, and the conductive layer extends beyond the projected area.

8. The semiconductor element according to claim 7, further comprising:

a redistribution structure configured to serve as a trace of the first die, surrounding and covering the conductive layer.

9. The semiconductor device as defined in claim 8, wherein the conductive layer is a first conductive layer, and wherein the redistribution structure comprises:

a second conductive layer configured to be electrically isolated from the first conductive layer when the second conductive layer transmits a signal other than the reference ground.

10. The semiconductor device as defined in claim 8, wherein the conductive layer is a first conductive layer, and wherein the redistribution structure comprises:

a second conductive layer configured to be coupled to the first conductive layer when the second conductive layer conveys the reference ground.

11. The semiconductor device as defined in claim 10, wherein the redistribution structure further comprises a dielectric layer over the conductive layer, wherein the semiconductor device further comprises:

a plug disposed in the dielectric layer configured to couple the first conductive layer to the second conductive layer.

12. The semiconductor device as claimed in claim 1, wherein the first die comprises a passivation layer, wherein the conductive layer is on the passivation layer.

13. The semiconductor device as defined in claim 1, wherein the conductive layer comprises copper and has a mesh structure.

14. A semiconductor component, comprising:

a first die;

a conductive layer disposed on and extending over the first die, configured to implement a ground reference; and

a redistribution structure covering and surrounding the conductive layer.

15. The semiconductor device as defined in claim 14, wherein the conductive layer is a first conductive layer, and wherein the redistribution structure comprises:

a dielectric layer covering the conductive layer; and

a second conductive layer disposed on the dielectric layer,

wherein the semiconductor element further comprises:

a plug disposed in the dielectric layer, wherein the second conductive layer provides the first conductive layer with the reference ground through the plug.

16. The semiconductor device of claim 14, wherein the first die comprises a passivation layer on a top surface of the first die, the passivation layer contacting the conductive layer.

17. A method for forming a semiconductor element includes:

providing a first crystal grain; and

a conductive layer is formed on the first die and between the first die and a second die to be bonded to the first die.

18. The method of forming as claimed in claim 17, further comprising:

forming a redistribution structure to cover the conductive layer.

19. The method of forming as claimed in claim 17, further comprising:

forming the conductive layer on the first die in a projected area, wherein the second die is configured to engage the first die, and defining the projected area by projecting the second die onto the first die.

Technical Field

The present disclosure relates generally to semiconductor devices and methods of forming the same, and more particularly to a semiconductor device and a method of forming the same in a packaging system.

Background

A System In Package (SiP) is a package in which a plurality of integrated circuits are packaged in a single module (package). The SiP performs all or most of the functions of an electronic system and is typically used inside a cell phone, digital music player, or other electronic device. A die containing an integrated circuit may be vertically stacked on a substrate. The dice are internally connected to each other by bonding wires. SiP solutions may include a variety of packaging technologies, such as flip chip (flip chip), wire bonding (wire bonding), wafer-level packaging (wafer-level packaging), and the like.

The above description of "prior art" is merely provided as background, and it is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is any part of the present disclosure.

Disclosure of Invention

The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is configured to bond in a direction with a second die external to the semiconductor device. The conductive layer is disposed in the direction and between the first die and the second die, and is configured to implement a ground reference.

In some embodiments, the second die is configured to engage the first die and define a projected area by projecting the second die onto the first die, and the conductive layer occupies the projected area.

In some embodiments, the semiconductor device further includes a redistribution structure. The redistribution structure is configured to serve as a trace of the first die and surrounds and covers the conductive layer.

In some embodiments, the conductive layer is a first conductive layer. The redistribution structure includes a second conductive layer. The second conductive layer is configured to be electrically isolated from the first conductive layer when the second conductive layer transmits a signal other than the reference ground.

In some embodiments, the conductive layer is a first conductive layer. The redistribution structure includes a second conductive layer. The second conductive layer is configured to be coupled to the first conductive layer when the second conductive layer conveys the reference ground.

In some embodiments, the redistribution structure further comprises a dielectric layer on the conductive layer. The semiconductor device further includes a plug. The plug is disposed in the dielectric layer and is configured to couple the first conductive layer to the second conductive layer.

In some embodiments, the second die is configured to engage the first die and the conductive layer extends beyond a projected area defined by projecting the second die onto the first die.

In some embodiments, the first die includes a passivation layer, wherein the conductive layer is disposed on the passivation layer.

In some embodiments, the conductive layer comprises copper and the conductive layer has a mesh structure.

The present disclosure further provides a semiconductor device. The semiconductor device includes a first die, a conductive layer and a redistribution structure. The conductive layer is disposed on and extends over the first die and is configured to implement a ground reference. The redistribution structure covers and surrounds the conductive layer.

In some embodiments, the conductive layer is a first conductive layer. The redistribution structure includes a dielectric layer and a second conductive layer. The dielectric layer covers the conductive layer. The second conductive layer is disposed on the dielectric layer. The semiconductor device further includes a plug. The plug is disposed in the dielectric layer. The second conductive layer provides the reference ground for the first conductive layer through the plug.

In some embodiments, the first die includes a passivation layer on a top surface of the first die, the passivation layer contacting the conductive layer.

The present disclosure further provides a method for forming a semiconductor device. The forming method comprises the following steps: providing a first die, and forming a conductive layer between the first die and the second die to be bonded to the first die.

In some embodiments, the forming method further includes forming a redistribution structure overlying the conductive layer.

In some embodiments, the forming method further includes forming the conductive layer on the first die in a projected area. The second die is configured to engage the first die and define the projected area by projecting the second die onto the first die.

In a comparative semiconductor device, if the first die and the second die are simultaneously operated at a relatively high operating frequency, the first die and the second die may interfere with each other by Radio Frequency (RF).

In the present disclosure, the conductive layer can effectively shield the first crystal grain and the second crystal grain. Thus, even when the first die and the second die are simultaneously operating at relatively high operating frequencies, the first die is no longer subject to RF interference from the second die. Furthermore, no major changes in circuit design are required. The original circuit design can still be used, the only change being the addition of conductive layers and plugs, which reduces the burden on the circuit designer.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure will become more fully understood from the consideration of the following description and the appended claims, taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like elements.

FIG. 1 is a schematic diagram of a comparison packaged semiconductor device;

FIG. 2 is a cross-sectional view of the comparative packaged semiconductor device of FIG. 1 taken along line A-A;

fig. 3 is a cross-sectional view illustrating a packaged semiconductor device according to some embodiments of the present disclosure taken along the same line a-a as in fig. 1;

fig. 4 is a cross-sectional view illustrating a cross-sectional view of the packaged semiconductor device of fig. 3 along the same line B-B as in fig. 1 in accordance with some embodiments of the present disclosure;

fig. 5 is a cross-sectional view illustrating another packaged semiconductor element of some embodiments of the present disclosure along the same line a-a as in fig. 1;

fig. 6 is a cross-sectional view illustrating the packaged semiconductor device of fig. 5 along the same line B-B as in fig. 1 in some embodiments of the present disclosure;

fig. 7-12 illustrate cross-sectional views of intermediate stages in forming a packaged semiconductor device according to some embodiments of the present disclosure;

fig. 13 is a flow chart illustrating a method of forming a packaged semiconductor device according to some embodiments of the present disclosure.

Description of reference numerals:

1 comparison packaged semiconductor element

2 semiconductor element

3 semiconductor element

4 semiconductor element

5 method

10 first crystal grain

14-piece cloth structure

16 conducting wire

20 second crystal grain

30 conductive layer

31 projection area

32 plug

40 conductive layer

50 operation

52 operation

54 operation

56 operation

100 substrate

102 bonding pad

104 passivation layer

110 connecting pad

112 pad

120 connecting pad

122 pad

140 dielectric layer

142 conductive layer

144 dielectric layer

212 contact pad

222 pad

Detailed Description

The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the present disclosure, however, the present disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

References to "one embodiment," "an example embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It will be apparent that the implementation of the disclosure does not limit the specific details known to those skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be widely implemented in other embodiments besides the embodiments. The scope of the present disclosure is not limited to the content of the embodiments but is defined by the claims.

Fig. 1 is a schematic diagram of a comparative packaged semiconductor component 1. Referring to fig. 1, the comparative packaged semiconductor device 1 includes a semiconductor device 2, and the semiconductor device 2 includes a first die 10 and a second die 20 outside the semiconductor device 2.

The first die 10 includes, for example, a Dynamic Random Access Memory (DRAM). In some embodiments, the first die 10 may include a logic chip (e.g., a central processing unit, a microcontroller), a memory chip (e.g., a Static Random Access Memory (SRAM) chip), a power management chip (e.g., a Power Management Integrated Circuit (PMIC) chip, a Radio Frequency (RF) chip, a sensing chip, a micro-electro-mechanical system (MEMS) chip), a signal processing chip (e.g., a Digital Signal Processing (DSP) chip, a front-end chip (e.g., an analog front-end) chip), or a combination thereof.

The second die 20 is stacked and bonded to the first die 10 in one direction (e.g., a vertical direction) by, for example, System In Package (SiP) technology. In some embodiments, the second die 20 is bonded to the first die 10 by, for example, direct surface bonding, metal-to-metal bonding, hybrid bonding, or other bonding processes. The second die 20 includes, for example, a system on chip (SoC). The second die 20 may perform a different function than the first die 10. The area of the second crystal grain 20 in this comparative example is smaller than the area of the first crystal grain 10. However, the present disclosure is not limited thereto. In some embodiments, the second die 20 may include a logic chip (e.g., a central processing unit, a microcontroller), a memory chip (e.g., a Static Random Access Memory (SRAM) chip), a power management chip (e.g., a Power Management Integrated Circuit (PMIC) chip, a Radio Frequency (RF) chip, a sensing chip, a micro-electro-mechanical system (MEMS) chip, a signal processing chip (e.g., a Digital Signal Processing (DSP) chip, a front-end chip (e.g., an analog front-end (AFE) chip), or a combination thereof.

The first die 10 communicates with the second die 20 through the pads 110, 112, 120, and 122 on the first die 10 and the pads 212 and 222 on the second die 20. For simplicity and clarity, only four pads 110, 112, 120, and 122 are depicted. However, the present disclosure is not limited thereto.

In more detail, the first die 10 communicates a reference ground with the second die 20 through the pads 110 and 212 on the first die 10 and the second die 20, respectively. However, the pads 110 may be disposed far away from the pads 212. If the bonding pad 110 is directly bonded to the bonding pad 212, a relatively long wire is required to bond the bonding pad 110 to the bonding pad 212. Such wires may cause adverse effects. To solve this problem, the bonding pad 112 and a redistribution structure 14 of the semiconductor device 2 are introduced, wherein the redistribution structure 14 is configured to serve as a trace of the first die 10, as described in detail with reference to fig. 2. By redistribution structures 14 (described in detail in fig. 2), the pads 110 provide a reference ground for the pads 112, and the pads 112 are relatively closer to the pads 212 than the pads 110.

Similarly, the first die 10 communicates a signal different from the reference ground to the second die 20 through the pads 120 and 222 on the first die 10 and the second die 20, respectively. This signal may include, for example, a data signal, a clock signal, or other suitable signal. To solve the above problem, the pad 120 provides a signal to the pad 122 through the redistribution structure 14, and the pad 122 is relatively closer to the pad 222 than the pad 120.

In operation, if the first die 10 and the second die 20 are both operating at relatively high operating frequencies, the first die 10 and the second die 20 may exhibit Radio Frequency (RF) interference with each other. In theory, a possible way to eliminate this RF interference is to adjust the operating frequencies of the first die 10 and the second die 20 such that the first die 10 and the second die 20 operate at high operating frequencies at different times, e.g., in an interleaved manner. However, this approach has its difficulties or impossibility. Further, it is difficult or impossible to eliminate or mitigate RF interference without significantly changing the circuit design of the semiconductor element 2, for example, by changing the layout and/or the circuit configuration.

Fig. 2 is a cross-sectional view of the comparative packaged semiconductor element 1 of fig. 1 along line a-a. Referring to fig. 2, the first die 10 includes a substrate 100, a pad 102 and a passivation layer 104.

The substrate 100 may include an active layer such as a bulk silicon (bulk silicon), doped or undoped, or semiconductor-on-insulator (SOI) substrate. Typically, the SOI substrate includes a layer of semiconductor material, such as silicon, formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In another embodiment, the substrate 100 may comprise a substrate to which an integrated circuit die may be attached. For example, the substrate 100 may include an interposer, a package substrate, a high-density interconnect, a printed circuit board, another integrated circuit die, and so forth.

It should be noted that in some embodiments, particularly embodiments in which substrate 100 includes an integrated circuit die, substrate 100 may include circuitry (not shown). In one embodiment, the circuit includes electronic components formed on the substrate 100, wherein one or more dielectric layers overlie the electronic components. Metal layers may be formed between the dielectric layers to route electrical signals between the electrical components. Electronic components may also be formed in one or more dielectric layers.

For example, the circuit may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) elements, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like, interconnected to perform one or more functions. These functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input or output circuitry, and the like. Those of ordinary skill in the art will appreciate that the foregoing illustrations are provided for illustrative purposes only to further illustrate the application of some illustrative embodiments and are not meant to limit the disclosure in any way. Other circuits may be used as appropriate for a given application. Where the substrate 100 is an interposer, the interposer may include passive devices (passive devices), active devices, both active devices and both passive devices, or neither.

In addition, the substrate 100 may be a wafer that may be formed into a plurality of dies and later separated, thereby forming a single integrated circuit die. As such, a single die is illustrated for ease of illustration, while it is understood that a portion of a wafer may be fabricated as a die.

Pads 102 are disposed in the upper surface of the substrate 100 to provide external electrical connections. In the present disclosure, the pad 102 is in the metal-3 (M3). However, the present disclosure is not limited thereto. It should be noted that the pad 102 may represent an electrical connection to the circuit formed on the substrate 100. The pad 102 may comprise a conductive material such as copper, but other conductive materials such as tungsten, aluminum, or copper alloys may alternatively be used. The pads 102 may be formed by any suitable process, such as deposition and etching, damascene or dual damascene, etc., and any suitable conductive material, such as aluminum.

The passivation layer 104 may be formed of a dielectric material, such as Polyimide (PI), polymer, oxide, nitride, etc., and is patterned on the surface of the substrate 100 to provide an opening over the pad 102 and to protect underlying layers from various environmental contaminants. In one embodiment, the passivation layer 104 comprises a composite layer of a silicon nitride layer and an oxide layer. The silicon nitride layer may be formed using Chemical Vapor Deposition (CVD) techniques using silane and ammonia as precursor gases to a thickness of about 2000 angstromsThe oxide layer may be formed by any oxidation process, such as wet or dry thermal oxidation in an ambient environment comprising oxide, H2O, NO, or a combination thereof, or by CVD techniques using tetra-ethyl-ortho-silicate (TEOS), with oxygen as a precursor gas.

Any suitable process may be used to form the structures discussed above and will not be discussed in further detail herein. The above description provides a general description of this feature of this embodiment, and many other features may be present, as will be appreciated by those of ordinary skill in the art. For example, other circuitry, pads, barrier layers, under bump metallization arrangements, additional passivation layers, etc. may be present. A single layer of conductive or bond pads and a passivation layer are shown for illustrative purposes only. Other embodiments may include any number of conductive layers and/or passivation layers. The above description is intended only to provide a context for the embodiments discussed herein, and is not intended to limit the scope of the present disclosure or any claims to a particular embodiment.

Still referring to fig. 2, the redistribution structure 14 includes a dielectric layer 140, a conductive layer 142, and a dielectric layer 144.

A dielectric layer 140 is formed over the passivation layer 104. The dielectric layer 140 serves as a mold for forming conductive pillars or plugs in subsequent processing steps. In one embodiment, the dielectric layer 140 includes a polymer, such as epoxy, Polyimide (PI), benzocyclobutene (BCB), Polybenzoxazole (PBO), and the like. In one embodiment where the polymer layer is, for example, PBO, the polymer layer may be formed to a thickness of, for example, about 2 microns (μm) to about 5 μm by Spin coating (Spin coating) and patterned using photolithography (photolithography) techniques. PBO is a photosensitive material that can be patterned by exposing a PBO layer to light according to a desired pattern, developing and curing.

As shown in fig. 2, a conductive layer 142 is formed on the surface of the dielectric layer 140 and the exposed portion of the pad 102. In one embodiment, conductive layer 142 can be formed by depositing a thin conductive layer, such as a thin layer of titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), using CVD or PVD techniques. For example, in one embodiment, conductive layer 142 comprises a Ti layer deposited by a PVD process.

The dielectric layer 144 has the same material as the dielectric layer 140. Therefore, a detailed description is omitted for the sake of brevity.

Although two dielectric layers 140 and 144 are explicitly illustrated, redistribution structure 14 may also include any number of dielectric layers having conductive features disposed therein, depending on the design of the package.

The bonding pad 112 is formed on the redistribution structure 14 and is coupled to the bonding pad 212 on the second die 20 through the wire 16 after the wire bonding process. In addition, the pads 110 are formed on the redistribution structure 14.

A cross-sectional view of packaged semiconductor device 1 along line B-B is similar to the cross-sectional view shown in fig. 2, except that pads 112 and 212 of fig. 2 are replaced with pads 122 and 222. Therefore, this cross-sectional view is omitted for the sake of brevity.

Fig. 3 is a cross-sectional view illustrating a packaged semiconductor device 3 according to some embodiments of the present disclosure along the same line a-a as in fig. 1. Referring to fig. 3, semiconductor element 3 is similar to semiconductor element 2 described and illustrated in fig. 2, except that, for example, semiconductor element 3 includes a conductive layer 30 and a plug 32 on passivation layer 104.

The conductive layer 30 is disposed between the first die 10 and the second die 20 in a direction to shield the first die 10 from the second die 2, wherein the first die 10 will be bonded to the second die 20, as described in detail below. The conductive layer 30 is disposed on the passivation layer 104, extending and contacting the passivation layer 104 in some embodiments. In addition, the conductive layer 30 is surrounded and covered by the redistribution structure 14. In more detail, the conductive layer 30 is covered by a dielectric layer 140. In some embodiments, conductive layer 30 comprises copper, and conductive layer 30 has a mesh structure. Generally, objects composed of copper can only withstand very small stresses but, due to the mesh structure of the present disclosure, the stress on the conductive layer 30 can be relieved, thus protecting the structure of the conductive layer 30 from cracking.

The conductive layer 30 occupies only the projection area 31. In detail, the second die 20 will be bonded to the first die 10. A projection area 31 is defined by projecting the second die 20 onto the first die 10.

The projected area 31 is defined by projecting the second die 20 bonded to the first die 10 onto the first die 10. The conductive layer 30 does not extend beyond the projected area 31.

Plug 32, in dielectric layer 140, is used to couple conductive layer 30 to conductive layer 142.

As mentioned above, the pad 110 is used to transmit the reference ground to the first die 10 via the pad 102. In this case, the pad 102 serves as a grounding pad. In addition, the pad 110 is also used for transmitting the reference ground to the second die 20 through the pad 102. In more detail, the pad 110 is short-circuited with the conductive layer 142. Conductive layer 142 carries a reference ground and provides this reference ground to conductive layer 30 via plug 32. Thus, conductive layer 30 has or implements a reference ground.

Since the conductive layer 30 has the reference ground and the conductive layer 30 occupies the projection area 31, the conductive layer 30 can effectively shield the first die 10 and the second die 20. Thus, even if the first die 10 and the second die 10 are simultaneously operating at relatively high operating frequencies, the first die 10 is no longer subject to interference from the RF of the second die 20.

Furthermore, no major changes in circuit design are required. The original circuit design can still be used, the only change being the addition of the conductive layer 32 and the plug 32, which reduces the burden on the circuit designer.

Fig. 4 is a cross-sectional view illustrating the packaged semiconductor device of fig. 3 in accordance with some embodiments of the present disclosure along the same line B-B as in fig. 1. Referring to fig. 4, as mentioned above, the pad 120 is used for transmitting a signal other than the reference ground to the first die 10 through the pad 102. In this case, the pad 102 serves as a signal pad. In addition, the pad 120 is also used for transmitting the signal to the second die 20 through the pad 222. In more detail, the pad 120 is short-circuited with the conductive layer 142. The conductive layer 142 transmits the signal. To allow the conductive layer 30 to continuously transmit the reference ground, the conductive layer 142 is electrically isolated from the conductive layer 30. In more detail, unlike the embodiment of fig. 3, there are no plugs coupling conductive layer 142 to conductive layer 30.

Fig. 5 is a cross-sectional view illustrating another packaged semiconductor element 4 including a semiconductor element according to some embodiments of the present disclosure, taken along the same line a-a as in fig. 1. Referring to fig. 5, semiconductor element 4 is similar to semiconductor element 3 described and illustrated in fig. 3, except that, for example, semiconductor element 4 includes a conductive layer 40.

The conductive layer 40 extends over the passivation layer 104 and beyond the projection region 31. An entire surface of the passivation layer 104 is substantially covered by the conductive layer 40. Thus, even if the first die 10 and the second die 20 are operated at a relatively high operating frequency at the same time, not only does the first die 10 no longer appear to be disturbed by RF from the second die 20, but also the second die 20 no longer appears to be disturbed by RF from the first die 10.

Fig. 6 is a cross-sectional view illustrating the packaged semiconductor device of fig. 5 in accordance with some embodiments of the present disclosure taken along the same line B-B as in fig. 1. Referring to fig. 6, similar to the embodiment of fig. 5, the conductive layer 40 extends over the passivation layer 104 and extends beyond the projection region 31. An entire surface of the passivation layer 104 is substantially covered by the conductive layer 40.

Fig. 7-12 illustrate cross-sectional views of intermediate stages in forming a packaged semiconductor device according to some embodiments of the present disclosure. Referring to fig. 7, a first die 10 is provided. In more detail, a substrate 100 is provided and an integrated circuit die is formed thereon. Next, the pads 102 are formed on the substrate 100 by any suitable process, such as deposition or etching, damascene or dual damascene, etc., and any suitable conductive material, such as aluminum. Next, a passivation layer 104 is formed on the substrate 100 and the pads 102 by, for example, a patterning process.

Referring to fig. 8, a conductive layer 40 is formed on the passivation layer 104 by, for example, a sputtering process.

Referring to fig. 9, redistribution structures 14 are formed on the conductive layer 40 and the pads 102 by, for example, a patterning process.

Referring to fig. 10, pads 110 and 112 are formed in redistribution structure 14.

Referring to fig. 11, a second die 20 having a pad 212 thereon is provided.

Referring to fig. 12, the second die 20 is bonded to the first die 10 by wires 16, for example, by a wire bonding process.

Fig. 13 is a flow chart illustrating a method 5 of forming a packaged semiconductor device according to some embodiments of the present disclosure. Referring to fig. 13, forming method 5 includes operations 50, 52, 54, and 56.

The method 5 begins with operation 50 in which a first die including a passivation layer is provided.

The method 5 proceeds to operation 52 where a conductive layer is formed over the passivation layer and between the first die and a second die. The second die is configured to engage the first die.

The method 5 continues with operation 54 in which a redistribution structure is formed on a pad of the first die. In addition, the redistribution structure covers the conductive layer.

The forming method 5 proceeds to operation 56 where a second pad is formed in the redistribution structure, the second pad being wire bonded to a pad of the second die.

The forming method 5 is only one embodiment of the present disclosure and is not intended to limit the spirit and scope of the present disclosure as defined by the claims. There may be additional operations before, during, and after the formation of method 5, and some operations may be replaced, deleted, or moved for additional embodiments of this method.

In the comparative semiconductor device 2, if the first die 10 and the second die 20 are simultaneously operated at a relatively high operating frequency, the first die 10 and the second die 20 may interfere with each other in Radio Frequency (RF).

In the present disclosure, the conductive layer 30 can effectively shield the first and second dies 10 and 20. Thus, even if the first die 10 and the second die 10 are simultaneously operating at relatively high operating frequencies, the first die 10 is no longer subject to interference from the RF of the second die 20. Furthermore, no major changes in circuit design are required. The original circuit design can still be used, the only change being the addition of the conductive layer 32 and the plug 32, which reduces the burden on the circuit designer.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is configured to bond in a direction with a second die external to the semiconductor device. The conductive layer is disposed in the direction and between the first die and the second die, and is configured to implement a ground reference

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first die, a conductive layer and a redistribution structure. The conductive layer is disposed on and extends over the first die and is configured to implement a ground reference. The redistribution structure covers and surrounds the conductive layer.

The present disclosure further provides a method for forming a semiconductor device. The forming method comprises the following steps: providing a first die, and forming a conductive layer between the first die and the second die to be bonded to the first die.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.