阅读说明：本技术 基于单元的电力网格(pg)架构 (Cell-based Power Grid (PG) architecture ) 是由 J·霍斯马尼 M·Y·夏利弗 V·萨纳卡 侯辉博 于 2018-03-26 设计创作，主要内容包括：本公开的各方面针对一种仅金属的基于单元的电力网格(PG)架构。根据一个方面,电力网格(PG)架构包括：具有N×M网格配置的单元构建块结构,N×M网格配置包括布置在第一方向上的N个单元构建块和布置在第二方向上的M个单元构建块,其中第一方向和第二方向彼此正交；以及多个电力网格(PG)单元,其中N个单元构建块中的每个和M个单元构建块中的每个由多个PG单元中的PG单元占据。(Aspects of the present disclosure are directed to a metal-only cell-based Power Grid (PG) architecture. According to one aspect, a Power Grid (PG) architecture comprises: a cell building block structure having an N × M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to each other; and a plurality of Power Grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.)

1. A Power Grid (PG) architecture, comprising:

a cell building block structure having an N M grid configuration comprising N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first and second directions are orthogonal to each other; and

a plurality of Power Grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks is occupied by a PG cell of the plurality of PG cells.

2. The Power Grid (PG) architecture of claim 1, wherein the plurality of PG cells comprises one or more basic PG cells.

3. The Power Grid (PG) architecture of claim 2, wherein the plurality of PG cells comprises at least one optimized PG cell.

4. The Power Grid (PG) architecture of claim 3, wherein the at least one optimized PG cell comprises a wiring optimized PG cell, a voltage drop optimized PG cell, or a hybrid optimized PG cell.

5. The Power Grid (PG) architecture of claim 1, wherein the value of N is equal to the value of M.

6. The Power Grid (PG) architecture of claim 1, wherein the cell building block structure comprises at least two different horizontal grid sizes.

7. The Power Grid (PG) architecture of claim 6, wherein the cell building block structure comprises at least two different vertical grid sizes.

8. A method for placing and routing one or more Power Grid (PG) cells on a Power Grid (PG) architecture, the method comprising:

determining an NxM grid configuration of the Power Grid (PG) architecture, wherein the NxM grid configuration comprises a NM number of unit building blocks;

determining a type for a PG cell to be placed on one of the cell building blocks; and

placing the determined type of PG cell on the one of the cell building blocks.

9. The method of claim 8, wherein the type of PG cell is one of: a basic PG cell, a wiring optimized PG cell, a voltage drop optimized PG cell, or a hybrid optimized PG cell.

10. The method of claim 8, further comprising: determining whether a determination of the type of PG cell has been made for each of the NM number of cell building blocks.

11. The method of claim 8, further comprising: it is determined whether the PG cell is a base PG cell and whether the base PG cell should be replaced with an optimized PG cell.

12. The method of claim 11, wherein the optimized PG cell is a route optimized PG cell and the route optimized PG cell comprises a number of metal traces that is less than a number of metal traces within the base PG cell.

13. The method of claim 11, wherein the optimized PG cell is a voltage-drop optimized PG cell, and the voltage-drop optimized PG cell comprises a number of metal traces that is greater than a number of metal traces within the base PG cell.

14. The method of claim 11, wherein the optimized PG cell is a hybrid optimized PG cell.

15. The method of claim 8, further comprising: at least one horizontal grid dimension A and at least one vertical grid dimension B of the N M grid configuration are determined.

16. The method of claim 15, wherein the horizontal grid dimension a is equal to the vertical grid dimension B.

17. The method of claim 15, wherein the horizontal grid dimension a is not equal to the vertical grid dimension B.

18. The method of claim 8, wherein N and M are integer values, and N is equal to M.

19. The method of claim 8, wherein N and M are integer values, and N is not equal to M.

20. The method of claim 8, further comprising: stitching the PG cell to the one or more PC cells of the Power Grid (PG) architecture using one or more electrical interconnects.

21. An apparatus for placing and routing one or more Power Grid (PG) cells on a PG architecture, the apparatus comprising:

means for determining an NxM grid configuration of the Power Grid (PG) architecture, wherein the NxM grid configuration comprises a NM number of unit building blocks;

means for determining a type of PG cell for placement on one of the cell building blocks; and

means for placing the determined type of PG cell on the one of the cell building blocks.

22. The apparatus of claim 21, wherein the type of PG cell is one of: a basic PG cell, a wiring optimized PG cell, a voltage drop optimized PG cell, or a hybrid optimized PG cell.

23. The apparatus of claim 21, further comprising: means for determining whether a determination of the type of PG cell has been made for each of the NM number of cell building blocks.

24. The apparatus of claim 21, further comprising: means for determining whether the PG cells are base PG cells, and means for determining whether the base PG cells should be replaced with optimized PG cells.

25. The apparatus of claim 24, wherein the optimized PG cell is a routing optimized PG cell and the routing optimized PG cell comprises a number of metal traces that is less than a number of metal traces within the base PG cell.

26. The apparatus of claim 24, wherein the optimized PG cell is a voltage-drop optimized PG cell, and the voltage-drop optimized PG cell comprises a number of metal traces that is greater than a number of metal traces within the base PG cell.

27. The apparatus of claim 24, wherein the optimized PG cell is a hybrid optimized PG cell.

28. The apparatus of claim 21, further comprising: means for determining at least one horizontal grid dimension A and at least one vertical grid dimension B of the NxM grid configuration.

29. The apparatus of claim 8, further comprising: means for stitching one or more electrical interconnects to the PG cell to the one or more PC cells of the Power Grid (PG) architecture.

30. A computer-readable medium storing computer-executable code operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to place and route one or more Power Grid (PG) cells on a Power Grid (PG) architecture, the computer-executable code comprising:

instructions for causing a computer to determine an N M grid configuration of the Power Grid (PG) architecture, wherein the N M grid configuration comprises a NM number of unit building blocks;

instructions for causing the computer to determine a type of PG cell for placement on one of the cell building blocks;

instructions for causing the computer to place the determined type of PG cell on the one of the cell building blocks; and

instructions for causing the computer to stitch the PG cell to the one or more PC cells of the Power Grid (PG) architecture using one or more electrical interconnects.

Technical Field

The present disclosure relates generally to the field of power grids, and in particular to metal-only cell-based Power Grid (PG) architectures.

Background

Electronic chips (e.g., system-on-a-chip SOCs) require dc power distribution for proper operation. DC power distribution on electronic chips may employ a predefined Power Grid (PG) architecture for each design prior to placement and routing steps at the time of manufacture. The placing and routing step is a process of: through this process, individual chip elements are positioned within the chip and interconnected to form operative circuitry. Conventionally, a unified power grid architecture may be assigned to the entire circuitry. The unified power grid architecture may include an array of vertical and horizontal conductors. This architecture may limit design optimization with respect to routability (i.e., the ability to interconnect elements) and voltage drop due to line resistance (e.g., IR drop, where I ═ current and R ═ resistance). Conventionally, to solve the local routability problem, the entire power grid must be redesigned. Similarly, in conventional approaches, to address the local voltage drop problem, the entire power grid must be redesigned. Thus, the local routability problem or the local voltage drop problem is solved in a global manner at the entire power grid, which may adversely affect the optimization for the rest of the power grid elements.

Disclosure of Invention

The following presents a simplified summary of one or more aspects of the disclosure in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended to neither identify key or critical elements of all aspects of the disclosure, nor delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

In one aspect, the present disclosure provides a Power Grid (PG) architecture comprising: a cell building block structure having an N × M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to each other; and a plurality of Power Grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

Another aspect of the present disclosure provides a method for placing and routing one or more Power Grid (PG) cells on a Power Grid (PG) architecture, the method comprising: determining an N M grid configuration of a Power Grid (PG) architecture, wherein the N M grid configuration comprises a NM number of unit building blocks; determining a type for a PG cell to place on one of the cell building blocks; and placing the PG cells of the determined type of PG cell on one of the cell building blocks. In one example, the method further comprises: a determination is made whether a determination of the type of PG cell has been made for each of the NM number of cell building blocks. In one example, the method further comprises: it is determined whether the PG cells are base PG cells and whether the base PG cells should be replaced with optimized PG cells. In one example, the method further comprises: at least one horizontal grid dimension a and at least one vertical grid dimension B of the N x M grid configuration are determined. In one example, the method further comprises: the PG cells are stitched to one or more PC cells of a Power Grid (PG) architecture using one or more electrical interconnects.

Another aspect of the present disclosure provides an apparatus for placing and routing one or more Power Grid (PG) cells on a Power Grid (PG) architecture, the apparatus comprising: means for determining an N M grid configuration of a Power Grid (PG) architecture, wherein the N M grid configuration comprises a NM number of unit building blocks; means for determining a type of PG cell for placement on one of the cell building blocks; and means for placing a PG cell of the determined type of PG cell on one of the cell building blocks. In one example, the apparatus further comprises: means for determining whether a determination of the type of PG cell has been made for each of an NM number of cell building blocks. In one example, the apparatus further comprises: means for determining whether a PG cell is a base PG cell, and means for determining whether a base PG cell should be replaced with an optimized PG cell. In one example, the apparatus further comprises: means for determining at least one horizontal grid dimension A and at least one vertical grid dimension B of an NxM grid configuration. In one example, the apparatus further comprises: means for stitching one or more electrical interconnects to a PG cell to one or more PC cells of a Power Grid (PG) architecture.

Another aspect of the disclosure provides a computer-readable medium storing computer-executable code operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to place and route one or more Power Grid (PG) cells on a Power Grid (PG) architecture, the computer-executable code comprising: instructions for causing a computer to determine an nxm grid configuration of a Power Grid (PG) architecture, wherein the nxm grid configuration includes an NM number of unit building blocks; instructions for causing a computer to determine a type for a PG cell placed on one of the cell building blocks; instructions for causing a computer to place a PG cell of the determined type of PG cell on one of cell building blocks; and instructions for causing a computer to stitch the PG cell to one or more PC cells of a Power Grid (PG) architecture using one or more electrical interconnects.

These and other aspects of the invention will be more fully understood upon review of the following detailed description. Other aspects, features and embodiments of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific exemplary embodiments of the invention in conjunction with the accompanying figures. While features of the invention may be discussed with respect to certain embodiments and figures below, all embodiments of the invention may include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various embodiments of the invention discussed herein. In a similar manner, although example embodiments may be discussed below as device, system, or method embodiments, it should be understood that such example embodiments may be implemented in a variety of devices, systems, and methods.

Drawings

Fig. 1 is an enlarged view of an example Power Grid (PG) cell.

Fig. 2 is a top view of the example Power Grid (PG) cell of fig. 1.

Fig. 3 illustrates a first example power grid architecture including Power Grid (PG) cells as its building blocks.

Fig. 4 illustrates a second example power grid architecture including Power Grid (PG) cells as its building blocks.

Fig. 5 illustrates an example Power Grid (PG) architecture that includes as its building blocks base PG cells and optimized PG cells.

Fig. 6 illustrates an example flow diagram for placement and routing of one or more PG cells over a Power Grid (PG) architecture for an electronic chip.

Detailed Description

The detailed description set forth below with respect to the drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Various aspects of the present disclosure relate to systems and methods for Power Grid (PG) architectures. DC power distribution in electronic chips (e.g., system on a chip SOCs) includes circuitry that uses a Power Grid (PG). The present disclosure relates to cell-based non-uniform power grid architectures (i.e., cell-based power grid architectures). Cell-based power grid architectures allow design optimization with respect to routability and voltage drop due to line resistance (i.e., IR drop). Various aspects of the present disclosure provide a power grid architecture that can address local routability requirements and/or local voltage drop requirements and minimize total chip area without requiring undesirable global impacts on the performance of the power grid. In one aspect, improved routability translates to improved total chip area, i.e., smaller chip area for the same power grid requirements. On the other hand, an improved voltage drop (i.e., reduced voltage drop due to line resistance) translates into improved circuit performance, e.g., improved voltage margin, improved timing margin, etc.

In various representative aspects, the disclosed cell-based Power Grid (PG) architecture uses metal-only PG cells within a hard coded circuit macro ("hard macro"). In one aspect, the hard coded circuit macro is part of circuitry. The PG cell structure is highly configurable to allow a trade-off between voltage drop and routability. In contrast to unified power grid architecture with vertical and horizontal wire arrays, the cell-based power grid architecture may employ only metal PG cells with optimized properties as basic building blocks. In various aspects, only metal PG cells can be stitched together using electrical interconnects. Cell characteristics allow improved routability with fewer metal traces and/or reduced voltage drop with more metal traces. The Power Grid (PG) architecture with cells as building blocks allows the Power Grid (PG) architecture to meet varying local routability requirements and/or local voltage drop requirements within the hard coded circuit macro.

In one aspect, a cell-based Power Grid (PG) architecture allows placement of one or more cells strategically located on a hard-coded circuit macro, where each of the one or more cells has an implemented cell structure optimized for routability, reduced voltage drop, or a balance between routability and reduced voltage drop to meet various local routability requirements and/or local voltage drop requirements of the hard-coded circuit macro.

Fig. 1 illustrates an enlarged view of an example Power Grid (PG) cell 100. In one example, PG cell 100 may include a first plurality of power supply lines 120 disposed parallel to each other on first plane 110 in the y-axis direction. In one example, each of the first plurality of power supply lines 120 is evenly spaced apart from each of the other first plurality of power supply lines 120. In another example, the first plurality of power supply lines 120 are not evenly spaced apart from each other, although disposed parallel to each other. The first plurality of supply lines 120 may be metal strips.

In addition, the PG cell 100 may include a second plurality of power supply lines 160 that are disposed parallel to each other on the second plane 150 in the x-axis direction. In one example, each of the second plurality of power supply lines 160 is evenly spaced apart from each of the other second plurality of power supply lines 160. In another example, the second plurality of power supply lines 160 are not evenly spaced apart from each other, although disposed parallel to each other. The second plurality of power supply lines 160 may be metal strips. In one aspect, the first plane 110 and the second plane 150 are parallel planes in the z-axis direction.

In one example, one or more of the first plurality of power supply lines 120 are electrically coupled to one or more of the second plurality of power supply lines 160. The electrical coupling may be accomplished, for example, through vias 130 shown in fig. 2. Fig. 2 is a top view of the example Power Grid (PG) cell 100 of fig. 1. Although only one via 130 is illustrated in fig. 2, those skilled in the art will appreciate that some PG cells may include more than one via to electrically couple the power supply line 120 on the first plane 110 to the power supply line 160 on the second plane 150.

In one aspect, each of the power supply lines 120, 160 supplies a voltage to an electronic component (not shown). For example, Vdd may refer to a drain voltage for a Metal Oxide Semiconductor (MOS) transistor, and Vss may refer to a source voltage for a MOS transistor. Fig. 2 shows only one Vdd and one Vss, even though there may be more than one drain voltage and more than one source voltage in a PG cell. Although Vdd and Vss are illustrated in fig. 2, other supply voltages may be supplied on the power supply lines 120, 160. In one example, in fig. 2, Vdd and Vss are shown as being orthogonal to each other on the PG cell, i.e., Vdd and Vss are supplied on orthogonal PG cell axes. In another example, Vdd and Vss may be parallel to each other on the PG cell, i.e., Vdd and Vss are supplied on parallel PG cell axes.

Fig. 3 illustrates a first example Power Grid (PG) architecture 300 that includes a Power Grid (PG) cell 310 as its building block. That is, the Power Grid (PG) architecture 300 may include a cell building block structure having an N × M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first and second directions are orthogonal to each other. For example, the first direction may be a horizontal direction (also referred to as an x-direction) and the second direction may be a vertical direction (also referred to as a y-direction).

For example, the Power Grid (PG) architecture 300 includes a plurality of PG cells 310 arranged in a square or rectangular grid structure (i.e., a cell building block structure), where the horizontal grid spacing has a first grid size a and the vertical grid spacing has a second grid size B. Power grid architecture 300 is shown to include N × M PG cells, with N number of PG cells arranged in a horizontal direction (also referred to as the x-direction) and M number of PG cells arranged in a vertical direction (also referred to as the y-direction). N and M are integers and those skilled in the art will appreciate that the number of PG cells in a power grid architecture will depend on application and/or design choices. In fig. 3, PG cells 310 are shown as approximately square in shape in the x-y plane. That is, the first mesh size a and the second mesh size B appear to be approximately the same in length. However, in other aspects, as shown in fig. 4, PG cells (e.g., PG cell 410) may be more rectangular in shape, with different mesh sizes.

Fig. 4 illustrates a second example power grid architecture 400 that includes Power Grid (PG) cells 410 as its building blocks. That is, the Power Grid (PG) architecture 400 may include a cell building block structure having an N × M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first and second directions are orthogonal to each other. For example, the first direction may be a horizontal direction (also referred to as an x-direction) and the second direction may be a vertical direction (also referred to as a y-direction).

In the example power grid architecture 400, the building blocks in the cell building block structure may be square in shape in the x-y plane, and rectangular in shape. Thus, PG cells 410 can be square in shape or rectangular in shape in the x-y plane. In the horizontal direction (also referred to as x-direction), four different horizontal grid sizes are shown: a. the₁、A₂、A₃And A₄. In the vertical direction (also referred to as y-direction), three different vertical grid sizes are shown: b is₁、B₂And B₃. In the example of FIG. 4, A₄And B₁Appears to be substantially the same. Thus, having a dimension A₄×B₁The PG cells of (a) may have a square shape in the x-y plane. On the other hand, A₁And B₁Appears different. Thus, having a dimension A₁×B₁The PG cells of (a) may have a rectangular shape in the x-y plane. Those skilled in the art will appreciate that the example of four different horizontal grid sizes and three different horizontal grid sizes is for illustrative purposes only, and that other numbers of different horizontal grid sizes and/or different vertical grid sizes are within the scope and spirit of the present disclosure.

In the example of fig. 4, a Power Grid (PG) architecture 400 includes six PG cells 410 in each horizontal row and seven PG cells 410 in each vertical column. Thus, Power Grid (PG) architecture 410 (shown in the example of fig. 4) has N × M PG cells, where N ═ 6 and M ═ 7. Those skilled in the art will appreciate that the number for N and the number for M may vary depending on application and/or design choices without departing from the scope and spirit of the present disclosure.

In one aspect, a Power Grid (PG) architecture (e.g., PG architecture 300 as shown in fig. 3 or PG architecture 400 as shown in fig. 4) may include a combination of basic PG cells and optimized PC cells. In one aspect, a base PG cell is a PG cell that has specified routability and voltage drop characteristics. The routability and/or voltage drop characteristics of the base PG cells can be based on usage, application, manufacturing considerations, user choices, and/or designer choices, among others. In one aspect, an optimized PG cell is a PG cell that has routability and/or voltage drop characteristics that are optimized for a particular application, which also allows for optimized PG cell placement on a Power Grid (PG) architecture.

A Power Grid (PG) architecture may be configurable to allow optimization between voltage drop and routability. In one example, a Power Grid (PG) architecture is a cell-based power grid that employs metal-only PG cells with optimized characteristics as its architectural building blocks. PG cells with optimized characteristics may be referred to as optimized PG cells. Optimized cell characteristics may include improved routability, which may be achieved by using fewer metal traces than the baseline design. An optimized PG cell with improved routability may be referred to as a route-optimized PG cell. The optimized cell characteristics may also include reduced voltage drop, which may be achieved by using more metal traces than the baseline design. An optimized PG cell with a reduced voltage drop may be referred to as a voltage drop optimized PG cell. Furthermore, an optimized PG cell that has a balance of improved routability characteristics and reduced voltage drop characteristics may be referred to as a hybrid optimized PG cell. The hybrid optimized PG cell may include a number of metal traces that is numerically between the number of metal traces in the routing optimized PG cell and the number of metal traces in the voltage drop optimized PG cell.

In one example, the baseline design is a PG cell with a default number of metal traces. PG cells with a baseline design may be referred to as basic PG cells. In one example, the base PG cell may have Q number of horizontal grid lines (i.e., baseline horizontal grid lines) and R number of vertical grid lines (i.e., baseline vertical grid lines) as shown in fig. 2. For example, a Power Grid (PG) architecture may employ one or more optimized PG cells strategically located on a hard-coded circuit macro, where each of the one or more optimized PG cells has cell characteristics optimized for routability, voltage drop, or a balance (i.e., a mix) between routability and voltage drop.

Fig. 5 illustrates an example Power Grid (PG) architecture 500 that includes as its building blocks a base PG cell 510 and an optimized PG cell 520. Although the Power Grid (PG) architecture 500 is shown as including both rectangular-shaped PG cells and square-shaped PG cells, those skilled in the art will appreciate that the power grid architecture 500 may include all rectangular-shaped PG cells or all square-shaped PG cells without departing from the scope and spirit of the present disclosure.

In one example, a Power Grid (PG) architecture 500 includes a plurality of base PG cells 510 and a plurality of optimized PG cells 520. In this example, the plurality of optimized PG cells 520 includes three different types: a) a wiring optimized PG cell 520 a; b) voltage drop optimized PG cell 520 b; and c) a hybrid optimized PG cell 520 c. Each optimized PG cell 520 may be overlaid onto the Power Grid (PG) architecture 500 according to local optimization requirements.

For example, if improved routability is desired for region 1, then the route optimized PG cell 520a is overlaid on region 1. If a reduced voltage drop is desired for region 2, then voltage drop optimized PG cell 520b is overlaid on region 2. If both improved routability and reduced voltage drop are desired for region 3, then the hybrid optimized PG cell 520c is overlaid on region 3. In the example of fig. 5, more than one area 1 is shown, and more than one area 2 is shown. Those skilled in the art will appreciate that the number of respective zones 1, 2 and 3 may vary depending on the local optimization requirements of the Power Grid (PG) architecture. In the example of Power Grid (PG) architecture 500, the remaining building blocks (which are not designated region 1, region 2, or region 3) include base PG cells 510. In one aspect, the PG cells (i.e., the base PG cell 510, the routing optimized PG cell 520a, the voltage drop optimized PG cell 520b, and the hybrid optimized PG cell 520c) can be stitched together using electrical interconnects (not shown).

For example, an optimized PG cell may have a Q_optHorizontal grid lines and R_optA vertical grid line, wherein Q_optIs different from the number of horizontal grid lines in the base PG cell. Similarly, R_optIs different from the number R of vertical grid lines in the base PG cell. Q_optHow the number of (c) is different from the number of Q, and/or R_optHow the number of cells in (c) differs from the number of R will depend on whether the optimized PG cell is optimized to: a) a routing optimized PG cell (i.e., 520 a); b) a voltage drop optimized PG cell (i.e., 520 b); or c) a hybrid optimized PG cell (i.e., 520 c).

For example, a wiring optimized PG cell may have Q_optRHorizontal grid lines and R_optRA vertical grid line, wherein Q_optR<Q and/or R_optR<R, where Q is the number of horizontal grid lines (i.e., baseline horizontal grid lines) for the base PG cell, and R is the number of vertical grid lines (i.e., baseline vertical grid lines) for the base PG cell.

For example, a voltage drop optimized PG cell may have a Q_optVHorizontal grid lines and R_optVA vertical grid line, wherein Q_optV>Q and/or R_optV>R, where Q is the number of horizontal grid lines (i.e., baseline horizontal grid lines) for the base PG cell, and R is the number of vertical grid lines (i.e., baseline vertical grid lines) for the base PG cell.

For example, a hybrid optimized PG cell may have a Q_optHHorizontal grid lines and R_optHA vertical grid line, wherein Q_optHAnd/or R_optHAre specified to balance the routability and voltage drop required for a particular local routability requirement and/or local voltage drop requirement. In the hybrid optimized PG cell, the number Q of horizontal grid lines_optHAnd the number R of vertical grid lines_optHThe corresponding number in the basic cells that will be different from the Power Grid (PG) architecture, and the difference in number is determined based on the desired routability and voltage drop characteristics.

In one aspect, a cell building block of a Power Grid (PG) architecture is a plurality of PG cells, which may include basic PG cells, wiring optimized PG cells, voltage drop optimized PG cells, and/or hybrid optimized PG cells. For example, a Power Grid (PG) architecture is assembled by determining a number N × M PG cells, where N number of PG cells are arranged in a horizontal direction (also referred to as x-direction) and M number of PG cells are arranged in a vertical direction (also referred to as y-direction). In one example, a Power Grid (PG) architecture is implemented with N × M base PG cells. However, one or more base PC cells can be replaced with one or more optimized PG cells (a routing optimized PG cell(s), a voltage drop optimized PG cell(s), and/or a hybrid optimized PG cell (s)) before the base PG cells are stitched together using electrical interconnects. The placement of each of the optimized PG cells on an N × M grid configuration of a Power Grid (PG) architecture may be determined based on local routability requirements and/or local voltage drop requirements.

In one example, a Power Grid (PG) architecture is assembled with a layout of each PG cell on an N × M grid configuration of the Power Grid (PG) architecture. For each cell building block on an N × M grid configuration, it is determined which type of PG cell is to be placed at its location. For example, for each cell building block, it is determined whether a base PG cell or a particular type of optimized PG cell (a wiring optimized PG cell, a voltage drop optimized PG cell, or a hybrid optimized PG cell) should be placed. Once the type of PG cell is determined for each of the cell building blocks, different types of PG cells are placed on an nxm grid configuration of a Power Grid (PG) architecture. After placement, the PG cells are stitched together using electrical interconnects to form a Power Grid (PG) architecture.

Fig. 6 illustrates an example flow diagram 600 for placement and routing of one or more PG cells on a Power Grid (PG) architecture for an electronic chip. In block 610, an N × M grid configuration of a Power Grid (PG) architecture is determined, where the N × M grid configuration includes a number of N multiplied by M ("NM number") unit building blocks. For example, the number N of PG cells to be arranged in the horizontal direction (also referred to as the x-direction) is determined, and the number M of PG cells to be arranged in the vertical direction (also referred to as the y-direction) is determined. In one example, N and M are integer values, and N is equal to M. In another example, N and M are integer values, and N is not equal to M. In one aspect, the determination of the nxm grid configuration may be performed by a processor, which may include hardware, software, firmware, or the like.

In block 620, at least one horizontal grid dimension a and at least one vertical grid dimension B of the N × M grid configuration are determined. In one example, the horizontal grid dimension a is equal to the vertical grid dimension B, while square cell blocks are produced in the x-y plane. In another example, the horizontal grid dimension a is not equal to the vertical grid dimension B, but rather a rectangular block of cells is produced in the x-y plane. In one aspect, an nxm grid configuration may include more than one horizontal grid size (e.g., a₁、A₂、A₃… Aw), and/or the nxm grid configuration may include more than one vertical grid dimension (e.g., B)₁、B₂、B₃… Bz), where W and Z may be any integer value to accommodate the requirements of a Power Grid (PG) architecture. In one aspect, the determination may be performed by a processor, which may include hardware, software, firmware, and so forth.

In block 630, the type of PG cells to place on one of the cell building blocks of the nxm grid configuration is determined. The type of PG cells may be one of: a basic PG cell, a wiring optimized PG cell, a voltage drop optimized PG cell, or a hybrid optimized PG cell. In one aspect, the determination may be performed by a processor, which may include hardware, software, firmware, and so forth.

In block 640, a PG cell (of the determined type of PG cell) is placed on one of the cell building blocks of the N × M grid configuration. In one aspect, the placing step may be performed by a processor, which may include hardware, software, firmware, or the like. In one example, the placing step can be performed by an actuator (e.g., a processor-controlled actuator).

In block 650, a determination is made as to whether a determination of the type of PG cell has been made for each of the N times M number ("NM number") of cell building blocks. If so, then proceed to block 660. If not, then proceed back to block 630. In one aspect, the determination may be performed by a processor, which may include hardware, software, firmware, and so forth.

In block 660, it is determined whether the PG cell is a base PG cell and whether the base PG cell should be replaced with an optimized PG cell. If the determination is yes, then the base PG cell is replaced with one of the following types of optimized PG cells: a wiring optimized PG cell, a voltage drop optimized PG cell, or a hybrid optimized PG cell. In one aspect, the determination may be performed by a processor, which may include hardware, software, firmware, and so forth.

In block 670, the PG cell is stitched to one or more PC cells of a Power Grid (PG) architecture using one or more electrical interconnects. In one aspect, the using step may be performed by a processor, which may include hardware, software, firmware, and the like. In one example, the using step can be performed by an actuator (e.g., a processor-controlled actuator).

In one example, one or more processors may be used to execute the software or firmware needed to perform the steps in the flowchart of fig. 6. Software should be construed broadly to mean instructions, instruction sets, code segments, program code, programs, subprograms, software modules, applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside on a computer readable medium. The computer readable medium may be a non-transitory computer readable medium. By way of example, a non-transitory computer-readable medium includes a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., Compact Disk (CD) or Digital Versatile Disk (DVD)), a smart card, a flash memory device (e.g., card, stick, or key drive), a Random Access Memory (RAM), a Read Only Memory (ROM), a programmable ROM (prom), an erasable prom (eprom), an electrically erasable prom (eeprom), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. By way of example, computer-readable media may also include carrier waves, transmission lines, and any other suitable media for transmitting software and/or instructions that may be accessed and read by a computer. The computer readable media may reside in the processing system 301, external to the processing system, or distributed across multiple entities including the processing system. The computer readable medium may be embodied in a computer program product. By way of example, the computer program product may comprise a computer-readable medium in a packaging material. The computer-readable medium may include software or firmware for placement and routing of PG cells to cell building blocks of a Power Grid (PG) architecture. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure, depending on the particular application and the overall design constraints imposed on the overall system.

Any circuitry included in the processor(s) is provided merely as an example, and other means for performing the described functions may be included within aspects of the present disclosure, including but not limited to instructions stored in a computer-readable medium, or any other suitable means or components described herein, and utilizing, for example, the processes and/or algorithms described herein with respect to the example flow diagrams.

Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object a physically contacts object B, and object B contacts object C, objects a and C may still be considered coupled to each other-even if they are not in direct physical contact with each other. For example, the first die may be coupled to the second die in the package even though the first die is never in direct physical contact with the second die. The terms "circuit" and "circuit arrangement" are used broadly and are intended to include both: hardware implementations of electrical devices and conductors, which when connected and configured enable the performance of the functions described in this disclosure without limitation as to the type of electronic circuitry, and software implementations of information and instructions, which when executed by a processor enable the performance of the functions described in this disclosure.

One or more of the components, steps, features and/or functions illustrated in the figures may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps or functions. Additional elements, components, steps, and/or functions may also be added without departing from the novel features disclosed herein. The apparatus, devices, and/or components illustrated in the figures may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be usefully implemented in software, and/or embedded in hardware.

It will be understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary processes. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more. The term "some" means one or more unless specifically stated otherwise. A phrase referring to "at least one of" a list of items refers to any combination of those items, including a single member. By way of example, "at least one of a, b, or c" is intended to cover: a; b; c; a and b; a and c; b and c; and a, b and c. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35u.s.c. § 112 sixth paragraph unless the element is explicitly recited using the phrase "means for … …", or in the case of a method claim, the element is recited using the phrase "step for … …".