2.5D multi-chip packaging structure of integrated antenna structure and manufacturing method
阅读说明:本技术 一种集成天线结构的2.5d多芯片封装结构及制造方法 (2.5D multi-chip packaging structure of integrated antenna structure and manufacturing method ) 是由 戴风伟 曹立强 于 2019-09-29 设计创作,主要内容包括:本发明公开了一种集成天线结构的2.5D多芯片封装结构,包括:衬底;多芯片塑封层,所述多芯片塑封层设置在所述衬底的上面;反射互连层,所述反射互连层设置在所述多芯片塑封层的上面;天线隔离层,所述天线隔离层设置在所述反射互连层的上面;天线阵列,所述天线阵列设置在所述天线隔离层的上表面;衬底背面重新布局布线层,所述衬底背面重新布局布线层设置在所述衬底的下面;外接焊球,所述外接焊球设置成与所述衬底背面重新布局布线层的外接焊盘电连接;以及钝化层,所述钝化层覆盖所述衬底背面重新布局布线层。(The invention discloses a 2.5D multi-chip packaging structure of an integrated antenna structure, which comprises: a substrate; the multi-chip plastic package layer is arranged on the substrate; a reflective interconnect layer disposed over the multi-chip molding layer; an antenna isolation layer disposed over the reflective interconnect layer; the antenna array is arranged on the upper surface of the antenna isolation layer; a substrate back-side re-layout wiring layer disposed below the substrate; the external welding ball is arranged to be electrically connected with the external welding pad of the redistribution layer on the back surface of the substrate; and a passivation layer covering the substrate back surface redistribution wiring layer.)
1. A 2.5D multi-chip package structure of an integrated antenna structure, comprising:
a substrate;
the multi-chip plastic package layer is arranged on the substrate;
a reflective interconnect layer disposed over the multi-chip molding layer;
an antenna isolation layer disposed over the reflective interconnect layer;
the antenna array is arranged on the upper surface of the antenna isolation layer;
a substrate back-side re-layout wiring layer disposed below the substrate;
the external welding ball is arranged to be electrically connected with the external welding pad of the redistribution layer on the back surface of the substrate; and
and the passivation layer covers the back surface of the substrate and redistributes the wiring layer.
2. The 2.5D multi-chip package structure of an integrated antenna structure of claim 1, wherein the substrate further comprises:
a silicon substrate;
a TSV conductive through hole penetrating through the silicon substrate; and
a first re-routed routing layer on the upper surface of the silicon substrate, the first re-routed routing layer being electrically connected to the substrate back-side re-routed routing layer through the TSV conductive vias, thereby routing electrical signals to the substrate back-side.
3. The 2.5D multi-chip package structure of an integrated antenna structure of claim 2, wherein the multi-chip molding layer further comprises:
the first plastic packaging layer covers the upper surface of the substrate;
a first copper pillar extending through the first molding layer and electrically connected to the first redistribution routing layer to direct electrical signals to a reflective interconnect layer and/or an antenna array;
one or more first chips disposed to be encapsulated by the first molding compound layer and electrically connected to the first re-layout wiring layer;
one or more second chips disposed to be encapsulated by the first molding compound layer and electrically connected to the first re-layout wiring layer; and
a bonding wire disposed to be covered by the first mold layer and electrically connecting the first chip or the second chip to the first re-layout wiring layer.
4. The 2.5D multi-chip package structure of the integrated antenna structure of claim 3, wherein the one or more first chips are radio frequency chips and the one or more second chips are control chips.
5. The 2.5D multi-chip package structure of an integrated antenna structure of claim 3, wherein a distance between the top of the first chip, the second chip, the bonding wire, and the substrate is less than a height of the first copper pillar.
6. The 2.5D multi-chip package structure of an integrated antenna structure of claim 3, wherein the reflective interconnect layer further comprises:
the dielectric layer is arranged on the upper surface of the multi-chip plastic package layer in a covering mode;
a second re-routed wiring layer electrically connected to the first copper pillar; and
and a reflective layer.
7. The 2.5D multi-chip package structure of integrated antenna structure of claim 6, wherein the antenna isolation layer further comprises a second molding layer and a second copper pillar. Wherein the second molding compound layer is arranged on the upper surface of the reflecting interconnection layer in a covering mode; the second copper pillar penetrates through the second plastic packaging layer and is electrically connected to the second re-layout wiring layer.
8. The 2.5D multi-chip package structure of integrated antenna structure of claim 7, in which the antenna array is electrically connected to the second copper pillar.
9. A method for manufacturing a 2.5D multi-chip packaging structure of an integrated antenna structure comprises the following steps:
forming a TSV conductive through hole and a first re-layout wiring layer on a first surface of a substrate;
forming a first copper pillar electrically connected to the first re-layout wiring layer;
assembling multiple chips;
forming a multi-chip plastic packaging layer and thinning the leaked first copper pillar;
forming a second re-layout wiring layer, a dielectric layer and an antenna reflection structure which are electrically connected with the first copper column;
forming a second copper pillar electrically connected to the second re-layout wiring layer;
forming an antenna isolation layer and thinning the leaked second copper pillar;
forming an antenna array electrically connected with the second copper pillar on the antenna isolation layer; and
and thinning the second surface of the substrate, realizing back exposure of the TSV conduction, and sequentially forming a passivation layer, a substrate back re-layout wiring layer electrically connected with the TSV conduction through hole, and an external solder ball arranged on an external bonding pad of the substrate back re-layout wiring layer on the passivation layer.
10. The method of claim 9, wherein the multi-chip assembly further comprises:
flip-chip bonding one or more first chips to the first re-layout routing layer;
positively mounting one or more second chips to the substrate; and
wire bonding electrically connects the second chip pad to the first re-layout wiring layer.
And the distance from the top of the lead to the substrate after the first chip, the second chip and the lead are bonded is less than the height of the first copper column.
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a 2.5D multi-chip packaging structure of an integrated antenna structure, a manufacturing method and the like.
Background
At present, components in portable/mobile consumer electronic devices represented by mobile phones continuously require designers to provide miniaturized and low-cost product solutions. In fact, miniaturization and cost reduction are not contradictory, but complement each other.
With the continuous progress of communication technology, especially the continuous development of 5G wireless communication technology, antenna system in package (AiP) appeared, and this AiP technology inherits and develops the integration concept of microstrip antenna, multi-chip circuit module and tile type phased array structure. The improvement of the integration level of the silicon-based semiconductor process drives researchers to continuously and deeply explore the integration of a single antenna or a plurality of antennas on a chip package from the end of the 90 s, the applicable antennas comprise a printed antenna, a metal sheet antenna, an ultra-wideband antenna, a composite antenna and the like, and the antennas can be embedded in the same system packaging structure, so that the whole system package is suitable for being directly applied to wireless communication products without additionally designing an additional antenna. Its further rapid development mainly benefits from the enormous demand of the market.
Since the introduction of antennas into multi-chip system-in-Package requires heterogeneous integrated radio frequency front end modules, more complicated redesign, and also must meet the trend of light, thin, short and small consumer electronics products, the Antenna Package (Antenna in Package; AiP) based on system-in-Package has become the direction of research. In the existing packaging structure, the following problems need to be overcome, and a first packaging system needs to integrate a radio frequency chip, a digital control chip and other heterogeneous chips; secondly, the signal interference of the antenna to the chip is considered, and the signal receiving performance of the antenna is considered; the third need to consider the physical performance requirements of the packaging system such as heat dissipation; the fourth also takes into account the subsequent assembly requirements of the packaging system.
The antenna is led into a multi-chip system-in-package structure, and the problems of difficulty in integration of heterogeneous chips, high requirement on antenna signals, poor heat dissipation performance and the like in the conventional structure are solved. The invention provides a 2.5D multi-chip packaging structure of an integrated antenna structure and a manufacturing method, which at least partially overcome the problems.
Disclosure of Invention
Aiming at the problems of difficult integration of heterogeneous chips, high requirement on antenna signals, poor heat dissipation performance and the like existing in the conventional multi-chip system-in-package structure, the invention provides a 2.5D multi-chip package structure of an integrated antenna structure according to one embodiment of the invention, which comprises the following steps:
a substrate;
the multi-chip plastic package layer is arranged on the substrate;
a reflective interconnect layer disposed over the multi-chip molding layer;
an antenna isolation layer disposed over the reflective interconnect layer;
the antenna array is arranged on the upper surface of the antenna isolation layer;
a substrate back-side re-layout wiring layer disposed below the substrate;
the external welding ball is arranged to be electrically connected with the external welding pad of the redistribution layer on the back surface of the substrate; and
and the passivation layer covers the back surface of the substrate and redistributes the wiring layer.
In one embodiment of the present invention, the substrate further comprises:
a silicon substrate;
a TSV conductive through hole penetrating through the silicon substrate; and
a first re-layout wiring layer on the upper surface of the silicon substrate, the first re-layout wiring layer being electrically connected to the substrate back-side re-layout wiring layer through the TSV conductive vias.
In one embodiment of the present invention, the multi-chip molding layer further comprises:
the first plastic packaging layer covers the upper surface of the substrate;
a first copper pillar penetrating the first molding compound layer and electrically connected to the first redistribution routing layer;
a first chip disposed to be encapsulated by the first molding compound layer and electrically connected to the first re-layout wiring layer;
a second chip disposed to be encapsulated by the first molding compound layer and electrically connected to the first re-layout wiring layer; and
a bonding wire disposed to be covered by the first mold layer and electrically connecting the first chip or the second chip to the first re-layout wiring layer.
In an embodiment of the present invention, the first chip is a radio frequency chip, and the second chip is a control chip.
In one embodiment of the present invention, a distance between the first chip, the second chip, a top of the bonding wire, and the substrate is less than a height of the first copper pillar.
In one embodiment of the present invention, the reflective interconnect layer further comprises:
the dielectric layer is arranged on the upper surface of the multi-chip plastic package layer in a covering mode;
a second re-routed wiring layer electrically connected to the first copper pillar; and
and a reflective layer.
In one embodiment of the present invention, the antenna isolation layer further comprises a second molding layer and a second copper pillar. Wherein the second molding compound layer is arranged on the upper surface of the reflecting interconnection layer in a covering mode; the second copper pillar penetrates through the second plastic packaging layer and is electrically connected to the second re-layout wiring layer.
In one embodiment of the invention, the antenna array is electrically connected to the second copper pillar.
According to another embodiment of the present invention, there is provided a method of manufacturing a 2.5D multi-chip package structure of an integrated antenna structure, including:
forming a TSV conductive through hole and a first re-layout wiring layer on a first surface of a substrate;
forming a first copper pillar electrically connected to the first re-layout wiring layer;
assembling multiple chips;
forming a multi-chip plastic packaging layer and thinning the leaked first copper pillar;
forming a second re-layout wiring layer, a dielectric layer and an antenna reflection structure which are electrically connected with the first copper column;
forming a second copper pillar electrically connected to the second re-layout wiring layer;
forming an antenna isolation layer and thinning the leaked second copper pillar;
forming an antenna array electrically connected with the second copper pillar on the antenna isolation layer; and
and thinning the second surface of the substrate, realizing back exposure of the TSV conduction, and sequentially forming a passivation layer, a substrate back re-layout wiring layer electrically connected with the TSV conduction through hole, and an external solder ball arranged on an external bonding pad of the substrate back re-layout wiring layer on the passivation layer.
In another embodiment of the present invention, the multi-chip assembly further comprises:
flip chip bonding a first chip to the first re-layout wiring layer;
positively mounting a second chip to the substrate; and
wire bonding electrically connects the second chip pad to the first re-layout wiring layer.
And the distance from the top of the lead to the substrate after the first chip, the second chip and the lead are bonded is less than the height of the first copper column.
The invention provides a 2.5D multi-chip packaging structure of an integrated antenna structure and a manufacturing method thereof.A switching plate with TSV is adopted to realize high-density integration of heterogeneous chips, then a plastic package wafer is reconstructed and combined with a large-size conductive copper column technology, a reflecting layer is arranged on the upper layer of the chip to overcome signal interference of an antenna to the chip, an antenna array structure is formed on the top layer, and finally an interconnection circuit and an external welding ball are formed on the back surface of the switching plate with TSV. The antenna array structure is electrically connected with the multiple chips and the external solder balls through the re-layout wiring layer in the packaging structure. The 2.5D multi-chip packaging structure based on the integrated antenna structure and the manufacturing method thereof have the advantages that 1) the whole packaging structure has the characteristics of thinness, miniaturization and high-density integration; 2) the integration of various heterogeneous chips can be realized, including heterogeneous radio frequency chips and digital control chips; 3) the assembly mode of the chip in the packaging structure is flexible, and FC, WB or both FC and WB can be adopted; 4) the TSVs of the package substrate (interposer) can be used for both interconnection to the substrate and heat dissipation.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional view of a 2.5D
Fig. 2A-2I illustrate cross-sectional projection views of a process for forming such a 2.5D
Fig. 3 illustrates a flow diagram of a 2.5D
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a 2.5D multi-chip packaging structure of an integrated antenna structure and a manufacturing method thereof.A switching plate with TSV is adopted to realize high-density integration of heterogeneous chips, then a plastic package wafer is reconstructed and combined with a large-size conductive copper column technology, a reflecting layer is arranged on the upper layer of the chip to overcome signal interference of an antenna to the chip, an antenna array structure is formed on the top layer, and finally an interconnection circuit and an external welding ball are formed on the back surface of the switching plate with TSV. The antenna array structure is electrically connected with the multiple chips and the external solder balls through the re-layout wiring layer in the packaging structure. The 2.5D multi-chip packaging structure based on the integrated antenna structure and the manufacturing method thereof have the advantages that 1) the whole packaging structure has the characteristics of thinness, miniaturization and high-density integration; 2) the integration of various heterogeneous chips can be realized, including heterogeneous radio frequency chips and digital control chips; 3) the assembly mode of the chip in the packaging structure is flexible, and FC, WB or both FC and WB can be adopted; 4) the TSVs of the package substrate (interposer) can be used for both interconnection to the substrate and heat dissipation.
A 2.5D multi-chip package structure of an integrated antenna structure according to an embodiment of the present invention is described in detail below with reference to fig. 1. Fig. 1 illustrates a cross-sectional view of a 2.5D
The
The multi-chip
The
The
The
A substrate backside RDL160 is disposed on a lower surface of the
The
The
The process of forming the 2.5D
First, at step 301, as shown in fig. 2A, a TSV conductive via 202 and a first RDL203 are formed on a
Next, at step 302, as shown in fig. 2B, a first large-
Then, in step 303, as shown in fig. 2C, a chip assembly is performed on the
Next, at step 304, as shown in fig. 2D, the multi-chip
Then, in step 305, as shown in fig. 2E, a
Next, at step 306, as shown in fig. 2F, a second large-
Then, in step 307, as shown in fig. 2G, an
Next, in step 308, as shown in fig. 2H, an
Finally, in step 309, as shown in fig. 2I, the back surface of the
The 2.5D multi-chip packaging structure and the manufacturing method based on the integrated antenna structure provided by the invention have the advantages that high-density integration of heterogeneous chips is realized by adopting the adapter plate with the TSV, then the plastic package wafer reconstruction is combined with a large-size conductive copper column technology, the upper layer of the chip is provided with the reflecting layer to overcome the signal interference of the antenna to the chip, the top layer is provided with the antenna array structure, and finally the back surface of the adapter plate with the TSV is provided with the interconnection circuit and the external solder balls. The antenna array structure is electrically connected with the multiple chips and the external solder balls through the re-layout wiring layer in the packaging structure. The 2.5D multi-chip packaging structure based on the integrated antenna structure and the manufacturing method thereof have the advantages that 1) the whole packaging structure has the characteristics of thinness, miniaturization and high-density integration; 2) the integration of various heterogeneous chips can be realized, including heterogeneous radio frequency chips and digital control chips; 3) the assembly mode of the chip in the packaging structure is flexible, and FC, WB or both FC and WB can be adopted; 4) the TSVs of the package substrate (interposer) can be used for both interconnection to the substrate and heat dissipation.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
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