阅读说明：本技术 一种集成天线的扇出型封装结构及其制造方法 (Fan-out type packaging structure of integrated antenna and manufacturing method thereof ) 是由 胡文华 曹立强 于 2019-10-08 设计创作，主要内容包括：本发明提供一种集成天线的扇出型封装结构,包括：转接板,所述转接板包括微带天线结构阵列；贴装于所述转接板的芯片,所述芯片包括第二重布线结构；塑封体,所述塑封体将所述芯片包封起来；以及设置在所述塑封体上的第一重布线结构,所述第一重布线结构与所述芯片电连接。(The invention provides a fan-out type packaging structure of an integrated antenna, which comprises: the patch panel comprises a microstrip antenna structure array; a chip attached to the interposer, the chip including a second redistribution structure; a plastic package body encapsulating the chip; and the first rewiring structure is arranged on the plastic package body and is electrically connected with the chip.)

1. A fan-out package structure of an integrated antenna, comprising:

the patch board comprises a carrier, a first microstrip antenna structure array, a second microstrip antenna structure array and an insulating film medium, wherein the first microstrip antenna structure array and the second microstrip antenna structure array are arranged on the upper surface and the lower surface of the carrier, the insulating film medium is arranged on the surface of the first microstrip antenna structure array, at least one first window is formed in the insulating film medium so as to expose part of the surface of the first microstrip antenna structure array, and the first microstrip antenna structure array and the second microstrip antenna structure array are electrically connected through a conductive through hole;

the chip is attached to the adapter plate and provided with a first surface and a second surface opposite to the first surface, the first surface of the chip comprises a device area, a chip circuit, a conductive bonding pad and a second rewiring structure, and the second rewiring structure is electrically connected with the conductive bonding pad of the chip;

a plastic package body encapsulating the chip; and

the first rewiring structure is arranged on the plastic package body and is electrically connected with the second rewiring structure through a copper column penetrating through the plastic package body.

2. The fan-out package structure of an integrated antenna of claim 1, wherein the second redistribution structure comprises conductive traces and an insulating medium disposed between the conductive traces, one ends of the conductive traces are electrically connected to the conductive pads of the chip, the other ends of the conductive traces form one or more external pads, and the interposer is electrically connected to the one or more external pads through wires.

3. The fan-out package structure of an integrated antenna of claim 2, further comprising one or more copper pillars extending through the molding compound, one end of the copper pillar being electrically connected to the external pad of the second redistribution structure and the other end being electrically connected to the first redistribution structure.

4. The fan-out package structure of an integrated antenna of claim 3, comprising at least one solder bump disposed on the first rewiring structure, the first rewiring structure connecting the copper pillars to corresponding solder bumps, respectively.

5. A method of manufacturing a fan-out package structure of an integrated antenna, comprising:

manufacturing an adapter plate, forming a first microstrip antenna structure array and a second microstrip antenna structure array on the upper surface and the lower surface of a carrier, electrically connecting the first microstrip antenna structure array and the second microstrip antenna structure array through a through silicon via, preparing a dielectric material on the surface of the first microstrip antenna structure array to form an insulating film medium, and forming at least one first window on the insulating film medium;

manufacturing a second rewiring structure on the first surface of the chip, wherein the second rewiring structure is electrically connected with the conductive bonding pad of the chip, and a copper column is formed on the bonding pad of the second rewiring structure;

attaching the second surface of the chip to the insulating film medium of the adapter plate by wire bonding, wherein the second rewiring structure on the surface of the chip is electrically connected to the first microstrip antenna structure array of the adapter plate by a wire;

carrying out plastic packaging, and wrapping the chip, wherein the top surface of a plastic packaging body is higher than the top surface of the second rewiring structure;

forming a first rewiring structure on the top surface of the plastic package body, wherein the first rewiring structure is electrically connected with the second rewiring structure through a copper column penetrating through the plastic package body; and

and (6) cutting.

6. The method of claim 5, wherein the array of microstrip antenna structures is fabricated by physical or chemical deposition.

7. The method of claim 6, wherein the dielectric film dielectric is formed by chemical deposition, spraying, lamination or pasting.

8. The method of claim 5, wherein forming a second redistribution structure comprises:

forming a first dielectric layer on the first surface of the chip;

opening a window in the first dielectric layer so as to expose the conductive bonding pad on the chip;

forming one or more layers of conductive material; and

removing the areas which do not need to be conducted through photoetching and etching technologies so as to form needed conducting circuits;

forming a second dielectric layer on the conductive circuit, removing part of the second dielectric layer through photoetching and etching technologies, and exposing at least one external bonding pad with a rewiring structure;

and forming a copper column on the at least one external connection bonding pad.

9. The method of claim 5, further comprising forming at least one solder bump on the first rewiring structure.

10. The method of claim 5, wherein forming the first rewiring structure comprises:

forming a third dielectric layer on the surface of the plastic package body;

opening a window in the third dielectric layer so as to expose the top surface of the copper pillar;

forming one or more layers of conductive material; and

and removing the areas which do not need to be conductive by photoetching and etching technologies so as to form the required conductive circuit.

Technical Field

The invention relates to the field of packaging, in particular to a fan-out type packaging structure of an integrated antenna and a manufacturing method thereof.

Background

Package-in-Package (AiP) technology integrates an Antenna into a Package carrying a chip through packaging materials and processes. AiP technology has been the mainstream antenna technology in wireless communication systems due to its good compromise of antenna performance, cost and volume.

In the conventional package antenna technology, when a package substrate is designed, an external connection interface of an antenna is directly reserved on the substrate, and then an external antenna module is assembled on the substrate, or an antenna structure is directly designed and integrated on the substrate.

In recent years, many fan-out antenna package structures have also appeared. Chinese patent applications 201711014958.6 and 201821346487.9 disclose fan-out antenna package structures, respectively, and referring to fig. 4 and 5, the antenna structures are fabricated on the back of the package body through long copper pillar connection based on the fan-out package process. Although the packaging structure fully utilizes the space on the back of the packaging body so as to save the area, the implementation processes of double-sided fan-out and high copper columns are complex, packaging is required for realizing the multilayer antenna, the manufacturing cost is high, and the implementation difficulty is high.

Therefore, there is a need for a new fan-out package structure and method of manufacturing the same that at least partially solves the problems of the prior art.

Disclosure of Invention

To solve the problems in the prior art, according to an embodiment of the present invention, there is provided a fan-out package structure, including: the patch board comprises a slide glass, wherein the slide glass is provided with a first surface and a second surface opposite to the first surface, the first surface of the slide glass comprises a first microstrip antenna structure array and an insulating film medium arranged on the surface of the first microstrip antenna structure array, the insulating film medium comprises a first window, the second surface of the slide glass comprises a second microstrip antenna structure array, the first microstrip antenna structure array and the second microstrip antenna structure array are formed by metal deposition, and the second microstrip antenna structure array is electrically connected with the first microstrip antenna structure array through a through silicon via; the front surface of the chip is attached to the first surface of the adapter plate, the chip is provided with a first surface and a second surface opposite to the first surface, the second surface of the chip is attached to the insulating film medium, the first surface of the chip comprises a device area, a chip circuit, a conductive bonding pad and a second rewiring structure, and the second rewiring structure is electrically connected with the conductive bonding pad of the chip; a plastic package body encapsulating the chip; and the first rewiring structure is arranged on the plastic package body and is electrically connected with the second rewiring structure through a copper column penetrating through the plastic package body.

In an embodiment of the invention, the second redistribution structure includes conductive traces and an insulating medium disposed between the conductive traces, one end of each conductive trace is electrically connected to a conductive pad of the chip, and the other end of each conductive trace is provided with one or more external pads. The adapter plate is electrically connected with the one or more external connection bonding pads through wires.

In an embodiment of the present invention, the fan-out package structure further includes at least one copper pillar penetrating through the plastic package body, and one end of the copper pillar is electrically connected to the external pad of the second redistribution structure, and the other end of the copper pillar is electrically connected to the first redistribution structure.

In an embodiment of the invention, the fan-out package structure further includes at least one solder bump disposed on the first redistribution structure, and the first redistribution structure connects the copper pillars to the corresponding solder bumps, respectively.

According to another embodiment of the present invention, there is provided a method for manufacturing a fan-out package structure of an integrated antenna, including: manufacturing an adapter plate by using a carrier, manufacturing a first microstrip antenna structure array and a second microstrip antenna structure array on a first surface and a second surface of the carrier respectively, electrically connecting the two microstrip antenna structure arrays through silicon through holes, manufacturing an insulating film medium on the surface of the first microstrip antenna structure array, and forming at least one first window on the insulating film medium; attaching a second surface of a chip to the adapter plate, and electrically connecting the chip with the first microstrip antenna structure array through a first window by a wire; carrying out plastic package to encapsulate the chip; and the first rewiring structure is arranged on the plastic package body and is electrically connected with the chip.

In another embodiment of the present invention, the interposer is formed by physical or chemical deposition, such as lift-off, sputtering, electroplating, chemical plating or lamination.

In another embodiment of the invention, the insulating film medium is manufactured by adopting a chemical deposition, spraying, laminating or pasting method.

In another embodiment of the present invention, the method further comprises forming a second redistribution structure on the first surface of the chip, including forming a first dielectric layer on the first surface of the chip; opening a window in the first dielectric layer so as to expose the conductive bonding pad on the chip; forming one or more layers of conductive material; removing the areas which do not need to be conducted through photoetching and etching technologies to form needed conducting circuits; a second dielectric layer is formed on the conductive line, and a portion of the second dielectric layer is removed by photolithography and etching techniques to expose at least one external pad of the second redistribution structure.

In another embodiment of the present invention, the method further comprises forming a copper pillar on at least one of the external bond pads.

In another embodiment of the present invention, the method further includes forming at least one solder bump on the first redistribution structure, the solder bump being electrically connected to another end of the copper pillar on the second redistribution structure.

In another embodiment of the present invention, forming the first redistribution structure includes forming a third dielectric layer on the surface of the plastic package body, and opening a window in the third dielectric layer to expose the top surface of the copper pillar and form one or more layers of conductive materials; and removing the areas which do not need to be conductive by photoetching and etching technologies so as to form the required conductive circuit.

Drawings

To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding components will be denoted by the same or similar reference numerals for clarity.

FIG. 1 shows a cross-sectional schematic diagram of a fan-out package structure according to one embodiment of the invention.

Fig. 2A to 2H are schematic cross-sectional views illustrating a process of forming a fan-out package structure according to an embodiment of the present invention.

Fig. 3 illustrates a flow diagram for forming a fan-out package structure according to an embodiment of the invention.

Fig. 4 and 5 are schematic cross-sectional views illustrating a fan-out antenna package structure in the prior art.

Detailed Description

In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.

The invention provides a fan-out type packaging structure of an integrated antenna, which aims to solve the problems that in the prior art, an antenna structure is directly designed and integrated on a substrate, the area of a plurality of substrates is consumed, and the manufacturing cost of double-sided fan-out is high. Meanwhile, the structure adopts a conventional wafer level packaging process, and the process is simple and easy to realize.

Fig. 1 shows a cross-sectional schematic view of a fan-out package structure 100 according to one embodiment of the invention. The fan-out package structure 100 includes an interposer 110, a chip 120 mounted on the interposer 110, a molding compound 150 wrapped outside the chip 120, and a first redistribution structure 160 disposed on a surface of the molding compound 150. The interposer 110 includes a chip having a first surface 110a and a second surface 110b opposite the first surface 110 a. In the embodiment of the invention, the carrier is generally a monocrystalline silicon wafer, and other materials can be selected for the carrier, such as a glass carrier, an organic substrate, a metal substrate, a ceramic substrate, a substrate formed by combining an organic substrate and a metal substrate, or other similar materials. It will be understood by those skilled in the art that flat surfaces of a particular strength may be used as the carrier sheet in the present invention. The first surface 110a of the carrier includes a first microstrip antenna structure array 111a and an insulating film medium 113 disposed on the surface of the first microstrip antenna structure array 111 a. The insulating film dielectric 113 material may be silicon dioxide, P I, resin, ABF film, etc. The insulating film medium 113 has at least one first window 114 thereon, and the first window 114 is used to expose a portion of the first microstrip antenna array that needs to be electrically connected to the chip 120. The second surface 110b of the chip includes a second array of microstrip antenna structures 111 b. The second microstrip antenna structure array 111b and the first microstrip antenna structure array 111a may be formed by depositing metals such as copper, aluminum, tungsten, and the like, and are electrically connected through the through-silicon via 112.

A chip 120 having a first surface 120a and a second surface 120b opposite to the first surface 120a, the second surface 120b of the chip being attached to the insulating film medium 113 of the interposer 110, the first surface 120a of the chip including a device region (not shown), a chip circuit (not shown), and a conductive pad 121; a second redistribution structure 130 is arranged on the first surface 120a of the chip, the second redistribution structure 130 comprises conductive traces 131 and insulating media 132 arranged between the conductive traces 131, one end of each conductive trace 131 is electrically connected with a conductive pad 121 of the chip, and one or more external pads are arranged at the other end of each conductive trace 131; the insulating medium is provided with at least one second window 133, and the first microstrip antenna structure array 111a is electrically connected with an external pad of the second redistribution structure through a lead 140 through the second window 133; the second redistribution structure 230 further has at least one copper pillar 134, and one end of the copper pillar 134 is electrically connected to an external pad of the second redistribution structure.

The chip 120 is encapsulated by the plastic package body 150, and the surface of the plastic package body is flush with the top end of the copper pillar 134 and does not cover the top end surface of the copper pillar 134.

The first redistribution structure 160 includes one or more conductive trace layers and an insulating medium disposed between the conductive traces. At least one solder bump 161 is disposed on a surface of the first rewiring structure 160. The first rewiring structure 160 connects the other end of the copper pillar 134 to a solder bump 161.

A process of forming a fan-out package structure according to one embodiment of the invention is described below in conjunction with fig. 2 and 3. Fig. 2A-2G illustrate cross-sectional views of a process of forming a fan-out package structure according to an embodiment of the invention. Fig. 3 illustrates a flow diagram for forming a fan-out package structure according to an embodiment of the invention.

First, in step 301, the interposer 210 is fabricated, as shown in fig. 2A and 2B. In some embodiments of the present invention, the interposer 210 may select a carrier, select parameters such as material, thickness, resistivity, etc. of the carrier as required, and deposit a layer of metal with corresponding shape and thickness on the upper and lower surfaces of the carrier by physical or chemical deposition methods such as evaporation, sputtering, electroplating, chemical plating, or lamination, etc. to form the microstrip antenna structure arrays 211, 212, and the microstrip antenna structure arrays 211, 212 are electrically connected through the conductive through holes; the method of chemical deposition, spraying, laminating or pasting can be adopted to prepare a dielectric material on the surface of one microstrip antenna structure array 211 to form an insulating film medium 214, and at least one first window 215 is formed on the insulating film medium, so that the microstrip antenna structure array can be electrically connected with other components conveniently;

next, in step 302, a redistribution structure 230 is formed on the surface of the chip 220. As shown in fig. 2C, a first dielectric layer 231 is formed on the first surface of the chip; opening a window in the first dielectric layer 231 to expose the conductive pad 221 on the chip; forming one or more layers of conductive material; removing the areas not needing to be electrically conductive by photoetching and etching technologies to form required conductive circuits 232; forming a second dielectric layer 233 on the conductive line 232, removing a part of the second dielectric layer by photolithography and etching techniques, and exposing at least one external pad 234 of the rewiring structure; and manufacturing a copper pillar 235 on the at least one external connection bonding pad 234, wherein one end of the copper pillar 235 is electrically connected with the external connection bonding pad 234.

Next, at step 303, the chip 220 is mounted on the interposer 210, as shown in fig. 2D. The second surface 220b of the chip is attached to the insulating film medium 214 of the interposer 210, and the external connection pads 234 exposed by the redistribution structure 230 on the chip 210 are electrically connected to the first microstrip antenna structure array 211 through the first window 215 by the wires 240.

Next, at step 304, plastic packaging is performed, as shown in fig. 2E and 2F. Encapsulating the chip 220 by using a plastic package body 250; the plastic package body 250 is thinned by grinding and polishing until the surface of the other end of the copper pillar 235 is exposed.

Next, at step 305, a re-routing structure 260 and one or more solder bumps 261 are formed, as shown in fig. 2G. The rewiring structure is used to connect the copper pillar 235 to one or more solder bumps. For example, a specific process for forming the redistribution structure may include forming a third dielectric layer on the top surface of the plastic package body, forming a window on the third dielectric layer to expose the top surface of the copper pillar, forming one or more layers of conductive material by PVD, ALD, electroless plating, electroplating, or the like, and removing the regions not required to be conductive by photolithography and etching techniques to form the desired conductive traces. Optionally, a fourth dielectric layer may be formed on the conductive lines and portions of the fourth dielectric layer may be removed by photolithography and etching techniques to expose the external pads of the rewiring structure.

Next, at step 306, dicing results in the final structure shown in fig. 2H.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.