阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 北林拓也 于 2021-05-08 设计创作，主要内容包括：对由金属导线的发热引起的半导体元件的温度上升进行抑制。半导体装置具有：印刷基板,其在上表面具有第一电路图案及第二电路图案；以及半导体元件,其配置于第一电路图案的上表面,半导体元件在上表面配置漏极电极,在下表面配置栅极电极及源极电极,栅极电极及源极电极经由第一接合材料与第一电路图案的上表面接合,漏极电极经由与半导体元件的上表面连接的金属部件与第二电路图案的上表面接合。(The temperature rise of the semiconductor element caused by the heat generation of the metal wire is suppressed. The semiconductor device includes: a printed substrate having a first circuit pattern and a second circuit pattern on an upper surface thereof; and a semiconductor element disposed on an upper surface of the first circuit pattern, the semiconductor element having a drain electrode disposed on the upper surface and a gate electrode and a source electrode disposed on a lower surface, the gate electrode and the source electrode being bonded to the upper surface of the first circuit pattern via a first bonding material, and the drain electrode being bonded to the upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element.)

1. A semiconductor device, comprising:

a printed substrate having a first circuit pattern and a second circuit pattern on an upper surface thereof; and

a semiconductor element disposed on an upper surface of the first circuit pattern,

the semiconductor element is provided with a drain electrode on the upper surface, a gate electrode and a source electrode on the lower surface,

the gate electrode and the source electrode are bonded to the upper surface of the first circuit pattern via a first bonding material,

the drain electrode is joined to an upper surface of the second circuit pattern via a metal member connected to an upper surface of the semiconductor element.

2. The semiconductor device according to claim 1,

the printed substrate has:

an insulating substrate;

a wiring layer disposed on an upper surface of the insulating substrate; and

an insulating layer locally disposed on an upper surface of the wiring layer,

the first circuit pattern is a part of the wiring layer exposed at a plurality of positions without being covered with the insulating layer,

the second circuit pattern is configured on the upper surface of the insulating layer.

3. The semiconductor device according to claim 2,

the wiring layer has a plating layer at a position where at least one of the gate electrode and the source electrode is bonded via the first bonding material.

4. The semiconductor device according to claim 2 or 3,

the wiring layer is exposed from a side surface of the insulating substrate,

the semiconductor device further has a metal terminal bonded to the wiring layer exposed from the side surface of the insulating substrate via a second bonding material.

5. The semiconductor device according to any one of claims 1 to 4,

the semiconductor device further includes:

a heat sink adhered to the lower surface of the printed substrate; and

a base plate adhered to a lower surface of the heat sink,

the heat sink has:

a first PET film bonded to the lower surface of the printed substrate via a first adhesive;

a graphite sheet disposed on a lower surface of the first PET film; and

and a second PET film disposed on a lower surface of the graphite sheet and bonded to an upper surface of the base plate via a second adhesive.

6. The semiconductor device according to any one of claims 1 to 5,

the printed substrate has a peel strength of 70% or more of room temperature at 175 ℃ or higher.

7. The semiconductor device according to any one of claims 1 to 6,

the semiconductor element is composed of SiC.

8. The semiconductor device according to any one of claims 1 to 7,

the metal part is a metal wire.

9. The semiconductor device according to any one of claims 1 to 7,

the metal part is a metal block.

Technical Field

The technology disclosed in the present specification relates to a semiconductor device.

Background

In the conventional semiconductor device, for example, a drain electrode of a semiconductor element is bonded to a circuit pattern on an upper surface of an insulating substrate with solder or the like, and a source electrode and a gate electrode of the semiconductor element are connected to a metal terminal or the like via a metal wire made of Al, Cu, or the like.

On the other hand, in order to reduce the manufacturing cost, the external dimensions of semiconductor devices are being reduced, and the area where the metal wires of the gate electrode and the source electrode can be bonded tends to be reduced.

If the area where the metal wires of the gate electrode and the source electrode can be bonded is reduced, the number of metal wires that can be wired to the source electrode is reduced, and therefore the amount of heat generated by each metal wire is increased. As a result, the temperature of the semiconductor element may increase due to heat propagation of the metal wire.

For example, patent document 1 discloses a technique for solving such a problem, and the technique is to improve heat dissipation efficiency in a lateral semiconductor element such as a GaN-High Electron Mobility Transistor (HEMT).

Patent document 1: japanese patent laid-open publication No. 2017-123358

However, the technique disclosed in patent document 1 relates to a lateral semiconductor element in which a source electrode and a drain electrode are arranged in a direction parallel to a substrate, and has a problem that the technique cannot be similarly applied to other semiconductor elements such as a vertical semiconductor element in which a source electrode and a drain electrode are arranged in a direction perpendicular to a substrate.

Disclosure of Invention

The technology disclosed in the present specification is proposed in view of the above-described problems, and is a technology for suppressing a temperature increase of a semiconductor element due to heat generation of a metal wire or the like.

A first aspect of the technology related to a semiconductor device disclosed in the present specification includes: a printed substrate having a first circuit pattern and a second circuit pattern on an upper surface thereof; and a semiconductor element disposed on an upper surface of the first circuit pattern, wherein a drain electrode is disposed on the upper surface of the semiconductor element, a gate electrode and a source electrode are disposed on a lower surface of the semiconductor element, the gate electrode and the source electrode are bonded to the upper surface of the first circuit pattern via a first bonding material, and the drain electrode is bonded to an upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element.

ADVANTAGEOUS EFFECTS OF INVENTION

A first aspect of the technology disclosed in the present specification includes: a printed substrate having a first circuit pattern and a second circuit pattern on an upper surface thereof; and a semiconductor element disposed on an upper surface of the first circuit pattern, wherein a drain electrode is disposed on the upper surface of the semiconductor element, a gate electrode and a source electrode are disposed on a lower surface of the semiconductor element, the gate electrode and the source electrode are bonded to the upper surface of the first circuit pattern via a first bonding material, and the drain electrode is bonded to an upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element. With this configuration, the temperature rise of the semiconductor element can be suppressed.

Further, objects, features, aspects and advantages associated with the technology disclosed in the present specification will become more apparent from the detailed description and the accompanying drawings.

Drawings

Fig. 1 is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to an embodiment.

Fig. 2 is a cross-sectional view schematically showing a modification of the structure of the semiconductor device according to the embodiment.

Fig. 3 is a cross-sectional view schematically showing an example of a structure in a case where a metal wire is connected to each of a gate electrode and a source electrode.

Fig. 4 is a plan view schematically showing an example of a structure in a case where a metal wire is connected to each of a gate electrode and a source electrode.

Fig. 5 is a plan view schematically showing an example of the structure of the semiconductor device according to the embodiment.

Fig. 6 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the embodiment.

Fig. 7 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the embodiment.

Fig. 8 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the embodiment.

Fig. 9 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the embodiment.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, detailed features and the like are shown for explanation of the technology, but these are examples and are for enabling implementation of the embodiments, and not all of them are essential features.

Note that the drawings are schematically illustrated, and the structures are omitted or simplified as appropriate in the drawings for convenience of description. The mutual relationship between the size and the position of the structures and the like shown in the different drawings is not necessarily described accurately, and can be changed as appropriate. In addition, in the drawings such as a plan view, which is not a cross-sectional view, a shadow may be added to facilitate understanding of the contents of the embodiment.

In the following description, the same components are denoted by the same reference numerals and are shown, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted to avoid redundancy.

In the following description, when a certain component is referred to as being "provided", "included", or "having", it is not an exclusive expression that excludes the presence of other components unless otherwise specified.

In the following description, even when ordinal numbers such as "first" and "second" are used, the ordinal numbers are used only for easy understanding of the contents of the embodiments, and are used for convenience, and are not limited to the order in which the ordinal numbers can be generated.

In the description below, even when terms indicating specific positions or directions such as "up", "down", "left", "right", "side", "bottom", "front", and "back" are used, these terms are used only for ease of understanding the contents of the embodiments and are used for convenience and are not related to positions or directions in actual implementation.

In the following description, the term "upper surface of …" or "lower surface of …" includes a state in which other components are formed on the upper surface or the lower surface of the target component, in addition to the upper surface or the lower surface of the target component. That is, for example, in the case of the description "b provided on the upper surface of a" does not prevent the other component "c" from being interposed between a "and a" b ".

< first embodiment >

Next, a semiconductor device according to this embodiment will be described.

In the following description, the expression "a and B are electrically connected" means that a current can flow between the structure a and the structure B in both directions.

< Structure of semiconductor device >

Fig. 1 is a cross-sectional view schematically showing an example of the structure of a semiconductor device according to this embodiment.

As illustrated in fig. 1, the semiconductor device includes at least a printed board 16 and a semiconductor element 18 bonded to an upper surface of the printed board 16 via a conductive bonding material 14B.

Here, the printed board 16 includes: an insulating substrate 16A; a circuit pattern 16B and a circuit pattern 16E formed on the upper surface of the insulating substrate 16A; and a circuit pattern 16C formed on the lower surface of the insulating substrate 16A.

The semiconductor element 18 is a field effect transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), an Insulated Gate Bipolar Transistor (IGBT), or a High Electron Mobility Transistor (HEMT), and the semiconductor element 18 includes: a drain electrode 18A on the upper surface; a gate electrode 18B on the lower surface, which is connected to the circuit pattern 16B via the bonding material 14B; and a source electrode 18C on the lower surface, which is connected to the circuit pattern 16B via the bonding material 14B. The semiconductor element 18 is made of, for example, Si. When an IGBT is used as the semiconductor element 18, the source electrode in the above description is referred to as an emitter electrode of the IGBT instead, and the drain electrode in the above description is referred to as a collector electrode (electrode) of the IGBT instead.

In addition, the semiconductor device may further include: a base plate 12 bonded to the lower surface of the printed board 16 via a conductive bonding material 14A; a metal wire 20 connecting the drain electrode 18A and the circuit pattern 16E; a metal terminal 24 further connected to the circuit pattern 16E through a metal wire 20; a housing 26 that accommodates these configurations; and a sealing material 22 such as gel or epoxy resin filled in the case 26. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

With such a configuration, in the semiconductor element 18, the drain electrode 18A is formed on the upper surface connected to the metal wire 20, and the area where the metal wire can be bonded can be increased as compared with a case where the metal wire 20 is connected with the surface on which the gate electrode 18B and the source electrode 18C are formed as the upper surface.

Therefore, the number of metal leads 20 that can be wired on this surface is increased, and therefore the amount of heat generated by each metal lead 20 can be suppressed. In addition, the degree of freedom in the wiring position of the metal lead 20 is also improved. As a result, even when the outer diameter of semiconductor element 18 is reduced, the temperature rise of semiconductor element 18 due to the heat of metal wire 20 can be suppressed.

Further, since the source electrode 18C is connected to the circuit pattern 16B via the bonding material 14B, a temperature increase of the semiconductor element 18 can be suppressed as compared with the case of connection by the metal wire 20.

Fig. 2 is a cross-sectional view schematically showing a modification of the structure of the semiconductor device according to the present embodiment.

As illustrated in fig. 2, the semiconductor device includes at least a printed circuit board 36 and a semiconductor element 18 bonded to an upper surface of the printed circuit board 36 via a conductive bonding material 14B.

Here, the printed board 36 has: an insulating substrate 36A; a wiring layer 36B formed on the upper surface of the insulating substrate 36A; an insulating layer 36C formed locally on an upper layer of the wiring layer 36B; a circuit pattern 36D formed on an upper layer of the insulating layer 36C; and a circuit pattern 36E formed on a lower layer of the insulating substrate 36A. Further, the wiring layer 36B and the circuit pattern 36D are electrically connected via the connection layer 36F.

In addition, the semiconductor element 18 includes: a drain electrode 18A on the upper surface; a gate electrode 18B connected to a wiring layer 36B (i.e., a circuit pattern at the upper surface of the printed substrate 36) exposed from the insulating layer 36C via a bonding material 14B; and a source electrode 18C connected to the wiring layer 36B (i.e., the circuit pattern at the upper surface of the printed substrate 36) exposed from the insulating layer 36C via the bonding material 14B.

In addition, the semiconductor device may further include: a base plate 12 bonded to the lower surface of the printed circuit board 36 via a conductive bonding material 14A; a metal wire 20 connecting the drain electrode 18A and the circuit pattern 36D; a metal terminal 24 further connected to the circuit pattern 36D through a metal wire 20; a housing 26; and an encapsulant material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

Here, the structure in the case where the metal wire is connected to each of the gate electrode 18B and the source electrode 18C, and the semiconductor device according to the present embodiment are compared.

Fig. 3 is a cross-sectional view schematically showing an example of a structure in a case where a metal wire is connected to each of the gate electrode 18B and the source electrode 18C.

As illustrated in fig. 3, the semiconductor device includes at least a printed board 46, and a semiconductor element 18 bonded to an upper surface of the printed board 46 via a conductive bonding material 14B.

Here, the printed board 46 has: an insulating substrate 16A; a circuit pattern 16D formed on the upper surface of the insulating substrate 16A; and a circuit pattern 16C formed on the lower surface of the insulating substrate 16A.

In addition, the semiconductor element 18 includes: a drain electrode 18A connected to the circuit pattern 16D via the bonding material 14B; a gate electrode 18B; and a source electrode 18C.

In addition, the semiconductor device may further include: a base plate 12 bonded to the lower surface of the printed board 46 via a conductive bonding material 14A; a metal wire 20B connecting the gate electrode 18B and the circuit pattern 16D; a metal wire 20A connecting the source electrode 18C and the circuit pattern 16D; a metal terminal 24 further connected to the circuit pattern 16D through the metal wire 20A or the metal wire 20B; a housing 26 that accommodates these configurations; and a sealing material 22 such as gel or epoxy resin filled in the case 26. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

Fig. 4 is a plan view schematically showing an example of a structure in a case where a metal wire is connected to each of the gate electrode 18B and the source electrode 18C.

As illustrated in fig. 4, the metal wire 20B connected to the gate electrode 18B and the metal wire 20A connected to the source electrode 18C are routed as wires for controlling the plurality of semiconductor elements 18. Accordingly, an area required for bonding the wiring is also increased. In addition, the degree of freedom of wiring routing is also reduced.

Fig. 5 is a plan view schematically showing an example of the structure of the semiconductor device according to the present embodiment.

As illustrated in fig. 5, the metal wire 20 connected to the drain electrode 18A is routed as a wiring for controlling the plurality of semiconductor elements 18. On the other hand, the wiring layer 36B connected to the gate electrode 18B and the source electrode 18C functions as a wiring for controlling the plurality of semiconductor elements 18 in the layer structure of the printed substrate 36.

Therefore, in the example illustrated in fig. 5, the routing of the wiring connected as the metal lead 20 can be reduced. Therefore, even when a plurality of semiconductor elements 18 are arranged in parallel with the reduced outer diameter, appropriate wiring with a high degree of freedom can be performed without increasing the outer diameter of the semiconductor device. As a result, the semiconductor device can be miniaturized.

< second embodiment >

A semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is omitted as appropriate.

< Structure of semiconductor device >

Fig. 6 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the present embodiment.

As illustrated in fig. 6, the semiconductor device includes at least a printed circuit board 56, and a semiconductor element 18 bonded to an upper surface of the printed circuit board 56 via a conductive bonding material 14B.

Here, the printed board 56 has: an insulating substrate 36A; a wiring layer 36G formed on an upper layer of the insulating substrate 36A; an insulating layer 36C formed locally on an upper layer of the wiring layer 36G; a circuit pattern 36D formed on an upper layer of the insulating layer 36C; and a circuit pattern 36E formed on a lower layer of the insulating substrate 36A. The wiring layer 36G has a via hole plating layer 36H formed with a plating layer on the inner wall of the via hole at a position where it is joined to the gate electrode 18B and the source electrode 18C via the joining material 14B. Further, the wiring layer 36G and the circuit pattern 36D are electrically connected via the connection layer 36F. The via hole plating layer 36H may be disposed at any one of a position of the wiring layer 36G to be bonded to the gate electrode 18B and a position of the wiring layer 36G to be bonded to the source electrode 18C.

In addition, the semiconductor element 18 includes: a drain electrode 18A; a gate electrode 18B connected to the via hole plating layer 36H exposed from the insulating layer 36C via the bonding material 14B, and further connected to the wiring layer 36G; and a source electrode 18C connected to the via hole plating layer 36H exposed from the insulating layer 36C via the bonding material 14B, and further connected to the wiring layer 36G.

In addition, the semiconductor device may further include: a base plate 12 bonded to the lower surface of the printed board 56 via a conductive bonding material 14A; a metal wire 20 connecting the drain electrode 18A and the circuit pattern 36D; a metal terminal 24 further connected to the circuit pattern 36D through a metal wire 20; a housing 26; and an encapsulant material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

In fig. 6, the gate electrode 18B and the source electrode 18C are connected to the via hole plating layer 36H and further to the wiring layer 36G via the bonding material 14B, respectively. Therefore, when the semiconductor element 18 and the printed board 56 are bonded, the bonding material 14B enters the inside of the via hole plating layer 36H. Therefore, the bonding area of the bonding material 14B and the via hole plating layer 36H increases, so the bonding process is stable. Further, since heat generation at the wiring of the semiconductor element 18 can be suppressed, the reliability of the semiconductor element can be improved.

< third embodiment >

A semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is omitted as appropriate.

< Structure of semiconductor device >

Fig. 7 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the present embodiment.

As illustrated in fig. 7, the semiconductor device includes at least a printed board 66, and a semiconductor element 18 bonded to an upper surface of the printed board 66 via a conductive bonding material 14B.

Here, the printed board 66 has: an insulating substrate 36A; a wiring layer 36G formed on an upper layer of the insulating substrate 36A; an insulating layer 36C formed locally on an upper layer of the wiring layer 36G; and a circuit pattern 36D formed on an upper layer of the insulating layer 36C. The wiring layer 36G has a via hole plating layer 36H at a position where it is bonded to the gate electrode 18B and the source electrode 18C via the bonding material 14B. Further, the wiring layer 36G and the circuit pattern 36D are electrically connected via the connection layer 36F.

In addition, the semiconductor element 18 includes: a drain electrode 18A; a gate electrode 18B connected to the via hole plating layer 36H exposed from the insulating layer 36C via the bonding material 14B, and further connected to the wiring layer 36G; and a source electrode 18C connected to the via hole plating layer 36H exposed from the insulating layer 36C via the bonding material 14B, and further connected to the wiring layer 36G.

In addition, the semiconductor device may further include: a base plate 12 bonded to the lower surface of the printed circuit board 56 via a heat sink 100; a metal wire 20 connecting the drain electrode 18A and the circuit pattern 36D; a metal terminal 24 further connected to the circuit pattern 36D through a metal wire 20; a housing 26; and an encapsulant material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

The heat sink 100 has: a polyethylene terephthalate (PET) film 102A bonded via an acrylic adhesive 101A bonded to the lower surface of the insulating substrate 36A; a graphite sheet 103 disposed on the lower surface of the PET film 102A; a PET film 102B disposed on the lower surface of graphite sheet 103; and an acrylic adhesive 101B adhered to the lower surface of the PET film 102B. The base plate 12 is bonded to the lower surface of the acrylic adhesive 101B.

According to the structure illustrated in fig. 7, the heat dissipation of the semiconductor element 18 is improved. Therefore, even when the outer diameter of semiconductor element 18 is reduced, deterioration of heat dissipation of semiconductor element 18 can be suppressed by dispersing heat generated by semiconductor element 18 by graphite sheet 103.

< fourth embodiment >

A semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is omitted as appropriate.

< Structure of semiconductor device >

Fig. 8 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the present embodiment.

As illustrated in fig. 8, the semiconductor device includes at least a printed circuit board 66 and a semiconductor element 18.

In addition, the semiconductor device may further include: a base plate 12 bonded to the lower surface of the printed circuit board 66 via a heat sink 100; a metal block 110 connecting the drain electrode 18A and the circuit pattern 36D via the bonding material 14C; a metal terminal 24 connected to the circuit pattern 36D through a metal wire 20; a housing 26; and an encapsulant material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

The heat sink 100 includes an acrylic adhesive 101A, PET film 102A, a graphite sheet 103, a PET film 102B, and an acrylic adhesive 101B. The base plate 12 is bonded to the lower surface of the acrylic adhesive 101B.

According to the structure illustrated in fig. 8, since the metal block 110 connected to the drain electrode 18A and the circuit pattern 36D has a larger bonding area than a metal wire, the heat dissipation of the semiconductor element 18 can be improved. As a result, the current density of the semiconductor element 18 can be improved.

< fifth embodiment >

A semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is omitted as appropriate.

< Structure of semiconductor device >

Fig. 9 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the present embodiment.

As illustrated in fig. 9, the semiconductor device includes at least a printed board 76 and a semiconductor element 18 bonded to an upper surface of the printed board 76 via a conductive bonding material 14B.

Here, the printed board 76 has: an insulating substrate 36A; a wiring layer 36J formed on an upper layer of the insulating substrate 36A; an insulating layer 36C formed locally on an upper layer of the wiring layer 36J; and a circuit pattern 36D formed on an upper layer of the insulating layer 36C. The wiring layer 36J has a via hole plating layer 36H at a position where it is bonded to the gate electrode 18B and the source electrode 18C via the bonding material 14B. Further, the wiring layer 36J and the circuit pattern 36D are electrically connected via the connection layer 36F.

In addition, the semiconductor element 18 includes: a drain electrode 18A; a gate electrode 18B connected to the via hole plating layer 36H exposed from the insulating layer 36C via the bonding material 14B, and further connected to the wiring layer 36J; and a source electrode 18C connected to the via hole plating layer 36H exposed from the insulating layer 36C via the bonding material 14B, and further connected to the wiring layer 36J.

In addition, the semiconductor device may further include: a base plate 12 bonded to the lower surface of the printed board 76 via a heat sink 100; a metal block 110 connecting the drain electrode 18A and the circuit pattern 36D via the bonding material 14C; a metal terminal 24A connected to the wiring layer 36J exposed on the side of the insulating layer 36C via the bonding material 14D; a housing 26A; and an encapsulant material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26A.

The heat sink 100 includes an acrylic adhesive 101A, PET film 102A, a graphite sheet 103, a PET film 102B, and an acrylic adhesive 101B. The base plate 12 is bonded to the lower surface of the acrylic adhesive 101B.

According to the configuration illustrated in fig. 9, since the metal terminal 24A and the wiring layer 36J are connected via the bonding material 14D, it is not necessary to form a pattern for connecting metal wires. Therefore, the area for mounting the semiconductor element 18 can be secured large, and the semiconductor device can be miniaturized.

< sixth embodiment >

A semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is omitted as appropriate.

< Structure of semiconductor device >

The semiconductor device described in the above-described embodiment can have a printed circuit board having a peel strength of 70% or more at room temperature when Tj is 175 ℃.

By providing a printed circuit board made of a heat-resistant resin material or the like as described above, the reliability of the semiconductor device in a high-temperature environment can be improved.

< seventh embodiment >

A semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is omitted as appropriate.

< Structure of semiconductor device >

The semiconductor device described in the above-described embodiment may include the semiconductor element 18 made of silicon carbide (SiC). Here, silicon carbide (SiC) is one of wide band gap semiconductors. A wide band gap semiconductor generally refers to a semiconductor having a band gap of about 2eV or more, and known examples thereof include group 3 nitrides such as gallium nitride (GaN), group 2 oxides such as zinc oxide (ZnO), group 2 chalcogenide compounds such as zinc selenide (ZnSe), diamond, silicon carbide, and the like.

When the semiconductor element included in the semiconductor device is formed of SiC, SiC can operate at a higher temperature than Si or the like, and therefore, the semiconductor element can be downsized and a plurality of SiC can be arranged in parallel. As a result, the semiconductor device can be miniaturized.

< effects produced by the above-described embodiments >

Next, an example of the effects produced by the above-described embodiments is shown. In the following description, the effects are described based on the specific configurations illustrated in the above-described embodiments, but may be replaced with other specific configurations illustrated in the present specification within a range in which the similar effects are produced.

In addition, the replacement may be performed across a plurality of embodiments. That is, the same effects can be produced by combining the respective configurations illustrated in the different embodiments.

According to the above-described embodiment, the semiconductor device includes the printed circuit board and the semiconductor element 18. Here, the printed board corresponds to, for example, any 1 of the printed boards 16, 36, 56, 66, 76, and the like (hereinafter, for convenience, description may be made to correspond to any 1 of them). The printed substrate 16 has a first circuit pattern and a second circuit pattern on an upper surface thereof. Here, the first circuit pattern corresponds to, for example, any 1 of the circuit pattern 16B, the wiring layer 36B, the via hole plating layer 36H, the wiring layer 36G, the wiring layer 36J, and the like (hereinafter, for convenience, the description may be made to correspond to any 1 of these). The second circuit pattern corresponds to, for example, any 1 of the circuit patterns 16E and 36D (hereinafter, for convenience, it may be described as corresponding to any 1 of them). The semiconductor element 18 is disposed on the upper surface of the circuit pattern 16B. The semiconductor element 18 has a drain electrode 18A disposed on the upper surface. In addition, the semiconductor element 18 has a gate electrode 18B and a source electrode 18C disposed on the lower surface thereof. The gate electrode 18B and the source electrode 18C are bonded to the upper surface of the circuit pattern 16B via a first bonding material. Here, the first bonding material corresponds to, for example, the bonding material 14B and the like. The drain electrode 18A is joined to the upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element 18. Here, the metal member corresponds to, for example, any 1 of the metal lead 20 and the metal block 110 (hereinafter, for convenience, it may be described as corresponding to any 1 of them). The second circuit pattern corresponds to, for example, any 1 of the circuit patterns 16E and 36D (hereinafter, for convenience, it may be described as corresponding to any 1 of them).

With this configuration, the temperature rise of the semiconductor element 18 can be suppressed. Specifically, the drain electrode 18A is formed on the surface of the semiconductor element 18 connected to the metal wire 20 (or the metal block 110), and the area where the metal wire can be bonded can be increased as compared with the case where the metal wire 20 is connected to the surface on which the gate electrode 18B and the source electrode 18C are formed. Therefore, since the number of metal leads 20 that can be wired on this surface is large (or the metal block 110 can be connected), the amount of heat generated by each metal lead 20 (or the metal block 110) can be suppressed. In addition, the degree of freedom in the wiring position of the metal lead 20 is also improved. As a result, even when the outer diameter of the semiconductor element 18 is reduced for the purpose of improving the yield (that is, when the area of the source electrode is reduced), the temperature rise of the semiconductor element 18 due to the heat of the metal wire 20 can be suppressed. Further, since the source electrode 18C is connected to the circuit pattern 16B via the bonding material 14B, a temperature increase of the semiconductor element 18 can be suppressed as compared with the case of connection by the metal wire 20. Therefore, since the temperature rise of the wiring can be suppressed on the upper and lower surfaces of the semiconductor element 18, the temperature rise of the semiconductor element 18 can be suppressed as a result.

In addition, the same effects can be produced also in the case where another structure exemplified in the present specification is appropriately added to the above-described structure, that is, in the case where another structure in the present specification which is not mentioned as the above-described structure is appropriately added.

Further, according to the above-described embodiment, the printed board 36 includes: an insulating substrate 36A; a wiring layer disposed on the upper surface of the insulating substrate 36A; and an insulating layer 36C locally disposed on the upper surface of the wiring layer. Here, the wiring layer corresponds to, for example, any 1 of the wiring layers 36B, 36G, and 36J (hereinafter, for convenience, description may be made to correspond to any 1 of them). The first circuit pattern is a part of the wiring layer 36B exposed at a plurality of positions without being covered with the insulating layer 36C. The second circuit pattern is a circuit pattern 36D disposed on the upper surface of the insulating layer 36C. With this configuration, it is possible to reduce the number of wires connected as the metal lead 20. Therefore, even when a plurality of semiconductor elements 18 are arranged in parallel with the reduced outer diameter, appropriate wiring with a high degree of freedom can be performed without increasing the outer diameter of the semiconductor device. As a result, the semiconductor device can be miniaturized.

In addition, according to the above-described embodiment, the wiring layer 36G has the via hole plating layer 36H at a position where it is bonded to at least one of the gate electrode 18B and the source electrode 18C via the bonding material 14B. With this configuration, when the semiconductor element 18 and the printed circuit board 56 are bonded, the bonding material 14B enters the inside of the via hole plating layer 36H. Therefore, the bonding area of the bonding material 14B and the via hole plating layer 36H increases, so the bonding process is stable. Further, since heat generation at the wiring of the semiconductor element 18 can be suppressed, the reliability of the semiconductor element can be improved.

In addition, according to the above-described embodiment, the wiring layer 36J is exposed from the side surface of the insulating substrate 36A. The semiconductor device further includes a metal terminal 24A bonded to the wiring layer 36J exposed from the side surface of the insulating substrate 36A via a second bonding material. Here, the second bonding material corresponds to, for example, the bonding material 14D. According to such a structure, since the metal terminal 24A and the wiring layer 36J are connected via the bonding material 14D, it is not necessary to form a pattern for connecting metal wires. Therefore, the area for mounting the semiconductor element 18 can be secured large, and the semiconductor device can be miniaturized.

In addition, according to the above-described embodiment, the semiconductor device includes: a heat sink 100 adhered to the lower surface of the printed board 66 (or the printed board 76); and a base plate 12 bonded to the lower surface of the heat sink 100. The heat sink 100 includes a first PET film, a graphite sheet 103, and a second PET film. Here, the first PET film corresponds to, for example, the PET film 102A. The second PET film corresponds to, for example, the PET film 102B. The PET film 102A is bonded to the lower surface of the printed substrate 66 (or the printed substrate 76) via a first adhesive. Here, the first adhesive corresponds to, for example, the acrylic adhesive 101A. The graphite sheet 103 is disposed on the lower surface of the PET film 102A. The PET film 102B is disposed on the lower surface of the graphite sheet 103. The PET film 102B is bonded to the upper surface of the base plate 12 via a second adhesive. Here, the second adhesive corresponds to, for example, the acrylic adhesive 101B. With this structure, the heat dissipation of the semiconductor element 18 is improved. Therefore, even when the outer diameter of semiconductor element 18 is reduced, deterioration of heat dissipation of semiconductor element 18 can be suppressed by dispersing heat generated by semiconductor element 18 by graphite sheet 103.

In addition, according to the above-described embodiment, the peel strength of the printed board 16 at 175 ℃ or higher is 70% or higher of the room temperature. With this configuration, the reliability of the semiconductor device in a high-temperature environment can be improved.

In addition, according to the above-described embodiment, the semiconductor element 18 is made of SiC. According to such a configuration, SiC can operate at a higher temperature than Si or the like, and therefore, the semiconductor elements can be downsized and a plurality of SiC can be arranged in parallel. As a result, the semiconductor device can be miniaturized.

In addition, according to the above-described embodiment, the metal member is the metal wire 20.

With this configuration, the drain electrode 18A is formed on the surface of the semiconductor element 18 connected to the metal wire 20, and the area where the metal wire can be bonded can be increased as compared with the case where the metal wire 20 is connected to the surface on which the gate electrode 18B and the source electrode 18C are formed. Therefore, the number of metal leads 20 that can be wired on this surface is increased, and therefore the amount of heat generated by each metal lead 20 can be suppressed.

In addition, according to the above-described embodiment, the metal member is the metal block 110. According to such a configuration, since the metal block 110 connected to the drain electrode 18A and the circuit pattern 36D has a larger bonding area than a metal wire, the heat dissipation of the semiconductor element 18 can be improved. As a result, the current density of the semiconductor element 18 can be improved.

< modification of the above-described embodiment >

In the above-described embodiments, materials, dimensions, shapes, relative arrangement, implementation conditions, and the like of the respective constituent elements are described in some cases, but these are merely examples in all respects and are not restrictive.

Therefore, a myriad of modifications and equivalents not shown in the examples can be conceived within the technical scope disclosed in the present specification. For example, the case where at least 1 component is modified, added, or omitted, and the case where at least 1 component in at least 1 embodiment is extracted and combined with components in other embodiments are included.

In the above-described embodiments, when a material name or the like is not specifically described, for example, an alloy or the like containing another additive in the material is included as long as no contradiction occurs.

In the above-described embodiments, the "1" component may be provided, or "1 or more" may be provided, as long as no contradiction occurs.

Each of the components in the above-described embodiments is a conceptual unit, and includes a case where 1 component is composed of a plurality of structures, a case where 1 component corresponds to a part of a certain structure, and a case where 1 structure has a plurality of components within the technical scope disclosed in the present specification.

In addition, each component in the above-described embodiments includes a structure having another structure or shape as long as the same function is exerted.

The description in the specification of the present application is referred to for all purposes related to the present technology, and is not admitted to be prior art.

Description of the reference numerals

12 base plate, 14A, 14B, 14C, 14D bonding material, 16, 36, 46, 56, 66, 76 printed substrate, 16A, 36A insulating substrate, 16B, 16C, 16D, 16E, 36D, 36E circuit pattern, 18 semiconductor element, 18A drain electrode, 18B gate electrode, 18C source electrode, 20A, 20B metal wire, 22 encapsulating material, 24A metal terminal, 26A case, 36C insulating layer, 36F connection layer, 36H via hole plating layer, 36B, 36G, 36J wiring layer, 100 heat sink, 101A, 101B acrylic adhesive, 102A, 102B PET film, 103 graphite sheet, 110 metal block.