阅读说明：本技术 半导体封装结构及其制造方法 (Semiconductor package structure and manufacturing method thereof ) 是由 曾吉生 赖律名 黄煜哲 汤士杰 彭宇民 柳辉忠 于 2021-05-13 设计创作，主要内容包括：提供一种半导体封装结构和一种制造半导体封装结构的方法。所述半导体封装结构包含半导体裸片和光吸收层。所述半导体裸片具有第一表面、第二表面和第三表面。所述半导体裸片的主动层邻近于所述第一表面。所述第二表面与所述第一表面相对。所述第三表面从所述第一表面延伸到所述第二表面。所述光吸收层覆盖所述半导体裸片的所述第二表面和所述第三表面。所述半导体裸片具有从所述第一表面到所述第二表面定义的厚度,并且所述半导体裸片的所述厚度小于或等于约300微米(μm)。(A semiconductor package and a method of manufacturing the semiconductor package are provided. The semiconductor package structure includes a semiconductor die and a light absorbing layer. The semiconductor die has a first surface, a second surface, and a third surface. An active layer of the semiconductor die is adjacent to the first surface. The second surface is opposite to the first surface. The third surface extends from the first surface to the second surface. The light absorbing layer covers the second surface and the third surface of the semiconductor die. The semiconductor die has a thickness defined from the first surface to the second surface, and the thickness of the semiconductor die is less than or equal to about 300 micrometers (μm).)

1. A semiconductor package structure, comprising:

a semiconductor die having a first surface, a second surface, and a third surface, wherein an active layer of the semiconductor die is adjacent to the first surface, the second surface is opposite the first surface, and the third surface extends from the first surface to the second surface;

a light absorbing layer covering the second surface and the third surface of the semiconductor die,

wherein the semiconductor die has a thickness defined from the first surface to the second surface, and the thickness of the semiconductor die is less than or equal to about 300 microns.

2. The semiconductor package structure of claim 1, wherein the light absorbing layer has a thickness in a range from about 1.5 microns to about 30 microns.

3. The semiconductor package structure of claim 1, further comprising a passivation layer covering the first surface of the semiconductor die.

4. The semiconductor package structure of claim 3, wherein the passivation layer partially covers the first surface of the semiconductor die, and the light absorbing layer further covers a portion of the first surface of the semiconductor die.

5. The semiconductor package structure of claim 3, wherein the passivation layer completely covers the first surface of the semiconductor die, and the light absorbing layer further covers a portion of the passivation layer.

6. The semiconductor package structure of claim 1, wherein the light absorbing layer comprises a first portion having a first thickness and a second portion having a second thickness less than the first thickness.

7. The semiconductor package structure of claim 6, wherein the first portion of the light absorbing layer abuts the first surface and surrounds the active layer.

8. The semiconductor package structure of claim 7, wherein the first portion of the light absorbing layer has a height that is higher than a height of the active layer.

9. The semiconductor package structure of claim 6, wherein the first portion of the light absorbing layer is disposed on the third surface and abuts the second surface.

10. The semiconductor package structure of claim 6, wherein the first and second portions of the light absorbing layer form a stepped profile.

11. The semiconductor package structure of claim 10, wherein the light absorbing layer includes an inner surface facing the semiconductor die and an outer surface opposite the inner surface, and the inner surface or the outer surface of the first portion and the inner surface or the outer surface of the second portion form the stepped profile.

12. The semiconductor package structure of claim 6, wherein the first portion of the light absorbing layer comprises a tapered portion.

13. The semiconductor package structure of claim 12, wherein the light absorbing layer includes an inner surface facing the semiconductor die and an outer surface opposite the inner surface, and the inner surface of the tapered portion of the light absorbing layer is tapered relative to the outer surface of the tapered portion.

14. The semiconductor package structure of claim 12, wherein the tapered portion of the light absorbing layer is tapered in a direction from the first surface toward the second surface, or the tapered portion of the light absorbing layer is tapered in the direction from the second surface toward the first surface.

15. The semiconductor package structure of claim 1, wherein the light absorbing layer has a curved surface located at a corner of the second and third surfaces of the semiconductor die.

16. The semiconductor package structure of claim 1, further comprising:

a shield layer disposed between the semiconductor die and the light absorbing layer.

17. A method of fabricating a semiconductor package structure, comprising:

providing a substrate having a first surface and a second surface opposite the first surface;

recessing at least one of the first surface and the second surface of the substrate;

singulating the substrate to form a first semiconductor die and a second semiconductor die; and

a light absorbing layer is formed over the first and second semiconductor dies.

18. The method of claim 17, wherein forming at least one of the first and second surfaces of the substrate into the recess comprises forming a plurality of first notches on the first surface of the substrate, and singulating the substrate to form the first and second semiconductor dies comprises cutting the substrate through the plurality of first notches such that each of the first and second semiconductor dies has a first stepped profile or a first tapered profile.

19. The method of claim 17, wherein forming at least one of the first and second surfaces of the substrate into the recess comprises forming a plurality of second notches on the second surface of the substrate, and singulating the substrate to form the first and second semiconductor dies comprises cutting the substrate through the plurality of second notches such that each of the first and second semiconductor dies has a second step profile or a second tapered profile.

20. The method of claim 17, wherein forming the light absorbing layer on each of the first and second semiconductor dies comprises spraying a light absorbing material on each of the first and second semiconductor dies, and the light absorbing material has a viscosity in a range of about 2Cp to about 11 Cp.

Technical Field

The present disclosure relates to a semiconductor package structure, and more particularly, to a semiconductor package structure having a light absorbing layer.

Background

Conventionally, semiconductor packages have semiconductor dies with sufficient thickness to block light-generated noise. As the size of semiconductor packages decreases, thinner semiconductor die are required. However, when the thickness of the semiconductor die is too thin, light may pass through the semiconductor die and reach the active layer, thereby causing noise, which may affect the performance of the semiconductor package structure. Therefore, a new semiconductor package structure is required to solve the above problems.

Disclosure of Invention

In some embodiments, a semiconductor package structure includes a semiconductor die and a light absorbing layer. The semiconductor die has a first surface, a second surface, and a third surface. An active layer of the semiconductor die is adjacent to the first surface. The second surface is opposite to the first surface. The third surface extends from the first surface to the second surface. The light absorbing layer covers the second surface and the third surface of the semiconductor die. The semiconductor die has a thickness defined from the first surface to the second surface, and the thickness of the semiconductor die is less than or equal to about 300 micrometers (μm).

In some embodiments, a method of fabricating a semiconductor package structure includes: providing a semiconductor die comprising a first surface, a second surface, and a third surface, wherein the second surface is opposite the first surface, and the third surface extends from the first surface to the second surface; and forming a light absorbing layer to cover the second surface and the third surface of the semiconductor die, wherein the light absorbing layer includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness.

Drawings

Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and that the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 1A illustrates a cross-sectional view of an example of a semiconductor package structure, according to some embodiments of the present disclosure.

Fig. 2 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 3 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 4 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 5 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 6 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 7 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 8 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 9 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 10 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 11 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 12 illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 13A illustrates a cross-sectional view of an example of a semiconductor package structure, in accordance with some embodiments of the present disclosure.

Fig. 13B illustrates a cross-sectional view of a comparative semiconductor device, according to some embodiments of the present disclosure.

Fig. 14A, 14B, 14C, 14D, 14E, 14F, and 14G illustrate various stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Fig. 15A, 15B, and 15C illustrate various stages of a method of fabricating a semiconductor package structure according to some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and detailed description to refer to the same or like components. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 1 illustrates a cross-sectional view of an example of a semiconductor package structure 1a, according to some embodiments of the present disclosure. In some embodiments, the semiconductor package structure 1a includes a semiconductor die 10 and a light absorbing layer (light absorbing layer) 30.

The semiconductor die 10 may include a silicon substrate or other suitable substrate. Semiconductor die 10 may have a surface 101, a surface 102 opposite surface 101, and a surface 103 extending from surface 101 to surface 102. Surface 101 may also be referred to as an active surface or first surface. Surface 102 may also be referred to as a backside surface (backside surface) or a second surface. Surface 103 may also be referred to as a side surface or a third surface. In some embodiments, semiconductor die 10 has a thickness H1, defined or bounded by surface 101 to surface 102 (define), that is greater than 0 and less than or equal to about 300 micrometers (μm).

The semiconductor die 10 may include an active layer 20. Active layer 20 may be disposed on surface 101 of semiconductor die 10. In some embodiments, active layer 20 may be embedded adjacent to surface 101 of semiconductor die 10. In some embodiments, a portion of active layer 20 may be disposed on surface 101 of semiconductor die 10 and another portion embedded in semiconductor die 10, to which the present disclosure is not intended to be limited. In some embodiments, the active layer 20 may comprise an optically sensitive element. The active layer 20 may include one or more Integrated Circuits (ICs). For example, the active layer 20 may include a combination of diodes, transistors, or other suitable elements.

The light absorbing layer 30 may cover the surfaces 102 and 103 of the semiconductor die 10. That is, from a top view, the light absorbing layer 30 may surround all edges (edges) of the surface 102. The light absorbing layer 30 is configured to prevent light from being incident on the active layer 20 through the surfaces 102 and/or 103. The light absorbing layer 30 may absorb light, particularly light having a wavelength of about 390nm to about 1000 nm. For example, when the light absorbing layer 30 has a thickness of about 2 μm, light having a wavelength of 390nm to 1000nm passes through the light absorbing layer 30 by 0.1% or less than 0.1%. In some embodiments, when the semiconductor die 10 has a thickness of about 300 μm and the light absorbing layer 30 has a thickness of about 2 μm, incident light from the surface 302 may be absorbed by the light absorbing layer 30 and the semiconductor die 10, and light incident to the active layer 20 may be reduced to 0.01% or less than 0.1%.

In some embodiments, the material of the light absorbing layer 30 may include polymers such as acrylics, polyvinyl alcohol, and polyimide. In some embodiments, the light absorbing layer 30 may include carbon black. In some embodiments, the light absorbing layer 30 does not contain a photoactive agent (photoactive agent). In some embodiments, the light absorbing layer 30 is free of optically cured material.

The light absorbing layer 30 may have an inner surface 301 facing the semiconductor die 10 and an outer surface 302 opposite the inner surface 301. In the present disclosure, the thickness of the light absorbing layer 30 may be measured along the normal direction of the surface 102 or 103. In the present disclosure, the light absorbing layer 30 may have different thicknesses at different positions. For example, the light absorbing layer 30 may have a thicker thickness on the surface 102 and a thinner thickness on the surface 103. However, the present disclosure is not intended to be so limited. In some embodiments, the light absorbing layer 30 may have a thickness in the range of about 1.5 μm to 5 μm. In some embodiments, the light absorbing layer 30 may have a thickness in the range of about 5 μm to 10 μm. In some embodiments, the light absorbing layer 30 may have a thickness in the range of about 10 μm to 30 μm.

The semiconductor package structure 1a may include a passivation layer 40. The passivation layer 40 may cover the surface 101 of the semiconductor die 10. The passivation layer 40 may cover the active layer 20. The passivation layer 40 may be configured to protect conductive elements, the active layer 20, and/or other elements in the semiconductor die 10 from damage or contamination. The passivation layer 40 may comprise a nitride, oxide, oxynitride, resin, or other suitable material.

The semiconductor package structure 1a may include a terminal (terminal) 50. The terminals 50 may be configured to electrically connect the semiconductor package 1a and other components, such as a Printed Circuit Board (PCB). In some embodiments, the terminals 50 are solder balls (e.g., Sn balls). The active layer 20 may be electrically connected to the terminals 50 through conductive lines formed in the semiconductor die 10 or in the passivation layer 40.

In some embodiments, the semiconductor package structure 1a includes a light-absorbing layer 30 that can function as a light-shielding layer, which reduces noise signals and facilitates manufacturing of the semiconductor package structure 1a having a smaller size, as compared to a conventional semiconductor package structure. For example, the comparative example semiconductor package structure uses a metal layer as a light shielding layer. Because light may reflect from metal, the metal shielding layer may cause light to be reflected and incident on other elements or devices that are sensitive to light, which may adversely affect the other elements or devices. Another comparative semiconductor package structure may use molding compound (molding compound) as a light shielding layer to prevent light from being reflected. However, the thickness of the molding material is more than 50 μm in consideration of the limitation of the molding process and the allowance of the single cut. Furthermore, the molding compound should have a thickness greater than 150 μm to ensure that most of the light can be absorbed by the molding compound, which increases the size of the semiconductor package structure.

Fig. 1A illustrates a cross-sectional view of an example of a semiconductor package structure 1A' according to some embodiments of the present disclosure. In some embodiments, the passivation layer 40 may completely cover the surface 101 of the semiconductor die 10, and the light absorbing layer 30 may further cover a portion of the passivation layer 40. In some embodiments, a portion of the light absorbing layer 30 may cover the passivation layer 40 adjacent to the surface 103. A portion of the light absorbing layer 30 may have a substantially uniform thickness, or a portion of the light absorbing layer 30 may gradually decrease or increase in thickness from the surface 103 toward the surface 101.

Fig. 2 illustrates a cross-sectional view of an example of a semiconductor package structure 1b, according to some embodiments of the present disclosure. The semiconductor package 1b of fig. 2 has a structure similar to that of the semiconductor package 1a of fig. 1, except that the semiconductor package 1b has a passivation layer 40'. The passivation layer 40' may expose a portion of the surface 101 of the semiconductor die 10. That is, the surface 101 is not completely covered by the passivation layer 40'. In some embodiments, light absorbing layer 30 may further cover a portion of surface 101 of semiconductor die 10. In other embodiments, the passivation layer 40 'may partially cover the surface 101 of the semiconductor die 10, and the light absorbing layer 30 may further cover a portion of the surface 101 of the semiconductor die 10 exposed from the passivation layer 40'.

Fig. 3 illustrates a cross-sectional view of an example of a semiconductor package structure 1c, according to some embodiments of the present disclosure. The semiconductor package structure 1c of fig. 3 has a structure similar to that of the semiconductor package structure 1a of fig. 1, except that the light absorbing layer 30 may have portions 31 and 32 having different thicknesses.

In some embodiments, a portion of the semiconductor die 10 may be cut or removed. In some embodiments, the surface 103 of the semiconductor die 10 and the corner (corner) of the surface 101 may be cut or removed such that the semiconductor die 10 may have a stepped profile at the corner of the surface 101 and the surface 103. In the present disclosure, a corner may mean an area where two surfaces meet. From a bottom view, when cutting or removing the corners of surface 103 and surface 101 of semiconductor die 10, semiconductor die 10 may have an annular groove in a peripheral region of surface 101 and a protruding portion in a central region of surface 101. The grooves may correspond, for example, to the corners of the cross-sectional view of fig. 3.

When a portion of the semiconductor die 10 is removed, it is advantageous to form the light absorbing layer 30 having a greater thickness corresponding to the removed portion. In some embodiments, the portion 31 is positioned at a location corresponding to the removed portion of the semiconductor die 10. In some embodiments, portion 31 abuts surface 101. In some embodiments, portion 31 may be disposed on surface 103. The portion 32 is positioned at a location corresponding to an unremoved portion of the semiconductor die 10. In some embodiments, inner surface 301 of portion 31 and inner surface 301 of portion 32 form a stepped profile at the corners of surface 101 and surface 103 of semiconductor die 10.

Portion 31 has a thickness T1. Portion 32 has a thickness T2. In some embodiments, thickness T1 is greater than thickness T2. Portion 31 may have a thicker thickness and abut surface 101. In some embodiments, the height of the portion 31 may be higher than the height of the active layer 20. That is, the portion 31 covers the active layer 20 in the horizontal direction. That is, the portion 31 may completely cover the active layer 20 in the horizontal direction. In this embodiment, even if light is incident from a side near the active layer 20, most of the light is absorbed by the portion 31, thus reducing the signal-to-noise ratio generated by the undesired light.

Fig. 4 illustrates a cross-sectional view of an example of a semiconductor package structure 1d, according to some embodiments of the present disclosure. The semiconductor package 1d of fig. 4 has a structure similar to that of the semiconductor package 1c of fig. 3 except that the position of the portion 31 is different.

In some embodiments, the corners of surface 103 and surface 102 are cut or removed so that semiconductor die 10 may have a stepped profile at the corners of surface 102 and surface 103. From a top view, semiconductor die 10 may have an annular recess in a peripheral region of surface 102 and a protruding portion in a central region of surface 102. The grooves may correspond, for example, to the corners of the cross-sectional view of fig. 3.

The portion 31 is positioned at a location corresponding to the removed portion of the semiconductor die 10. In this embodiment, portion 31 may abut surface 102. Thus, the light absorbing layer 30 has a thicker thickness corresponding to the corner defined by the surface 102 and the surface 103. In some embodiments, inner surface 301 of portion 31 and inner surface 301 of portion 32 form a stepped profile at the corners of surface 102 and surface 103 of semiconductor die 10.

Because the light absorbing layer 30 is formed by a spraying coating process and thus may have a sagging phenomenon (sagging phenomenon), this allows the light absorbing layer 30 to have a thinner thickness at the corners of the semiconductor die 10. In this embodiment, the corners of the semiconductor die 10 are removed, which helps to form a thicker light absorbing layer 30 to eliminate sagging.

Fig. 5 illustrates a cross-sectional view of an example of a semiconductor package structure 1e, according to some embodiments of the present disclosure. The semiconductor package 1e of fig. 5 has a structure similar to that of the semiconductor package 1c of fig. 3 except that the contour of the portion 31 is different.

In some embodiments, the corners of surface 101 and surface 103 of semiconductor 10 may be cut or removed by way of a bevel cut (bevel cut) so that semiconductor die 10 may have a tapered portion (tapered portion) abutting surface 101. In some embodiments, a portion of the passivation layer 40 is removed so that the semiconductor die 10 and the passivation layer 40 can have a coplanar surface. In some embodiments, the tapered portion of semiconductor die 10 may taper in a direction from surface 102 toward surface 101. In the present disclosure, a tapered portion means that (from a cross-sectional view) the width or thickness of the portion gradually changes, e.g., becomes smaller or larger.

In some embodiments, the portion 31 can include a tapered portion positioned on a tapered portion of the semiconductor die 10. In some embodiments, portion 31 may taper in a direction from surface 101 toward surface 102. In some embodiments, light absorbing layer 30 may have a curved surface at a corner defined by surface 101 and surface 103 of semiconductor die 10. That is, the inner surface 301 of the light absorbing layer 30 is curved or bent corresponding to the corners of the surfaces 101 and 103. In some embodiments, the curved surface of the light absorbing layer 30 is recessed relative to the semiconductor die 10. In some embodiments, the inner surface 301 of the portion 31 is tapered relative to the outer surface 302 of the portion 31. In some embodiments, the portion 32 may include a non-tapered portion corresponding to an unremoved portion of the semiconductor die 10. The inner surface 301 of the portion 32 is substantially parallel to the outer surface 302 of the portion 32.

Fig. 6 illustrates a cross-sectional view of an example of a semiconductor package structure 1f, according to some embodiments of the present disclosure. The semiconductor package structure 1f of fig. 6 has a structure similar to that of the semiconductor package structure 1c of fig. 3, except that the light absorbing layer 30 may have two thicker portions, such as portions 31 and 33 adjacent to the surface 101 and the surface 102, respectively.

In some embodiments, the light absorbing layer 30 may have a portion 33 and a portion 34. The portion 33 is positioned on the removed portion of the semiconductor die 10. Portion 33 may abut surface 102. The portion 34 is positioned over an unremoved portion of the semiconductor die 10. Portion 33 has a thickness T3. Portion 34 has a thickness T4. In some embodiments, thickness T3 is greater than thickness T4. In some embodiments, thickness T4 is greater than thickness T2. In this embodiment, the light absorbing layer 30 may have thicker portions corresponding to corners of the surfaces 101 and 103, and corresponding to corners of the surfaces 102 and 103, respectively.

Fig. 7 illustrates a cross-sectional view of an example of a semiconductor package structure 1g, according to some embodiments of the present disclosure. The semiconductor package 1g of fig. 7 has a structure similar to that of the semiconductor package 1e of fig. 5, except that the semiconductor package 1g further includes a portion 33 and a portion 34.

In some embodiments, the corners of surface 102 and surface 103 may be removed by way of an oblique angle cut, such that semiconductor die 10 may have a tapered portion abutting surface 102. In some embodiments, the tapered portion of semiconductor die 10 may taper in a direction from surface 101 toward surface 102.

In some embodiments, the portion 33 may include a tapered portion on a tapered portion of the semiconductor die 10. In some embodiments, portion 33 may taper in a direction from surface 102 toward surface 101. In some embodiments, the light absorbing layer 30 may have a curved or bent surface at the corners of the surface 102 and the surface 103 of the semiconductor die 10. That is, the inner surface 301 of the light absorbing layer 30 is curved or bent at the corners of the surface 102 and the surface 103. In some embodiments, the portion 34 may include a non-tapered portion corresponding to an unremoved portion of the semiconductor die 10. The inner surface 301 of the portion 34 is substantially parallel to the outer surface 302 of the portion 34.

Fig. 8 illustrates a cross-sectional view of an example of a semiconductor package structure 1h, according to some embodiments of the present disclosure. The semiconductor package 1h of fig. 8 has a structure similar to that of the semiconductor package 1c of fig. 3, except that the corners of the semiconductor die 10 of the semiconductor package 1h are not removed. In some embodiments, outer surface 302 of portion 32 and outer surface 302 of portion 31 form a stepped profile at the corners of surfaces 101 and 103.

Fig. 9 illustrates a cross-sectional view of an example of a semiconductor package structure 1i according to some embodiments of the present disclosure. The semiconductor package 1i of fig. 9 has a structure similar to that of the semiconductor package 1e of fig. 5 except that corners of the semiconductor die 10 of the semiconductor package 1i are not removed. In this embodiment, portion 31 may include a tapered portion at the corner of surface 101 and surface 102. In some embodiments, portion 31 may taper in a direction from surface 101 toward surface 102. In some embodiments, the outer surface 302 of the portion 31 is tapered relative to the inner surface 301.

Fig. 10 illustrates a cross-sectional view of an example of a semiconductor package structure 1j, according to some embodiments of the present disclosure. The semiconductor package 1j of fig. 10 has a structure similar to that of the semiconductor package 1f of fig. 6, except that the corners of the semiconductor die 10 of the semiconductor package 1i are not removed. In some embodiments, outer surface 302 of portion 33 and outer surface 302 of portion 32 form a stepped profile at the corners of surface 102 and surface 103.

Fig. 11 illustrates a cross-sectional view of an example of a semiconductor package structure 1k, according to some embodiments of the present disclosure. The semiconductor package 1k of fig. 11 has a structure similar to that of the semiconductor package 1g of fig. 7 except that corners of the semiconductor die 10 of the semiconductor package 1k are not removed. In some embodiments, portion 33 may taper in a direction from surface 102 toward surface 101. In some embodiments, the outer surface 302 of the portion 33 is tapered relative to the inner surface 301.

Fig. 12 illustrates a cross-sectional view of an example of a semiconductor package structure 1l according to some embodiments of the present disclosure. The semiconductor package 1l of fig. 12 has a structure similar to that of the semiconductor package 1a of fig. 1, except that the semiconductor package 1l includes a shielding layer (shielding layer) 60.

The shielding layer 60 may cover the surface 102 and the surface 103 of the semiconductor die 10. The light absorbing layer 30 may cover the shielding layer 60. In some embodiments, the shielding layer 60 is disposed between the semiconductor die 10 and the light absorbing layer 30. The material of the shield layer 60 may comprise a metal, metal alloy, or other suitable material. In some embodiments, the conductivity of the light absorbing layer 30 is less than the conductivity of the shielding layer 60. The shielding layer 60 may be configured to function as an electromagnetic shielding (EMI) layer. In this embodiment, the shielding layer 60 is covered by the light absorbing layer 30. Accordingly, incident light may be absorbed by the light absorbing layer 30, so that other elements (not shown) may be protected from the negative effects of reflected light.

Fig. 13A illustrates a cross-sectional view of an example of a semiconductor device 4, according to some embodiments of the present disclosure. The semiconductor device 4 may include a semiconductor package structure 1 and at least one element 2 attached on a substrate 3.

The semiconductor package 1 may be one of the semiconductor packages 1a-1 l. The element 2 may comprise an optical element or a non-optical element, which may comprise a plurality of ICs. The substrate 3 may comprise a PCB or other suitable substrate. In some embodiments, the element 2 is an optically sensitive element. In this embodiment, the light L incident to the semiconductor package structure 1 is absorbed by the light absorption layer 30, so that the element 2 can be protected from the negative influence of the reflected light from the light L.

Fig. 13B illustrates a cross-sectional view of a comparative semiconductor device 5, according to some embodiments of the present disclosure. The semiconductor device 5 does not include a light absorbing layer. The semiconductor device 5 includes a shield layer 60. As shown in fig. 13B, when the light L is incident to the semiconductor die 10, the reflected light L' is reflected from the shielding layer 60. As a result, the element 2 may be affected by the reflected light L'.

Fig. 14A, 14B, 14C, 14D, 14E, 14F and 14G illustrate various stages of a method of fabricating a semiconductor package structure 1F according to some embodiments of the present disclosure.

Referring to fig. 14A, a substrate 10' is provided. Substrate 10' may include a portion 10a and a portion 10 b. After singulation (singulation) of substrate 10', each of portions 10a and 10b may correspond to semiconductor die 10. A plurality of active layers 20, passivation layers 40, and/or terminals 50 may be disposed or formed on each of the portions 10a and 10 b. Substrate 10 'may include surface 101', surface 102', and surface 103'. The surface 101' may be the surface on which the active layer 20 is disposed. Surface 102' may be a backside surface. The surface 103' may be a side surface. In some embodiments, surface 102 'may be thinned such that substrate 10' may have a thickness of less than 300 μm.

Referring to fig. 14B, the terminal 50 may be attached to the carrier 71 by an adhesive 80. In some embodiments, a portion of surface 102' is removed or recessed (or recessed). In some embodiments, the portion corresponding to the cut-out (not shown) between portions 10a and 10b is removed or recessed to form notch 11. In addition, the peripheral region of surface 102' is removed. In some embodiments, the substrate 10' may be removed by a step cut. In some embodiments, the substrate 10 'may be removed by bevel cutting, such that the substrate 10' may have a tapered portion.

Referring to fig. 14C, after removing or recessing portions of surface 102' of substrate 10', carrier 71 is removed and surface 101' may be attached to carrier 72. In some embodiments, a portion of surface 101' is removed or recessed. In some embodiments, a portion corresponding to a cutting lane (not shown) between the portions 10a and 10b is removed or recessed to form a notch (also referred to as a fillet) 12. In addition, the peripheral region of the surface 101' is removed. In some embodiments, the notches 11 are aligned with the notches 12.

Referring to fig. 14D, the substrate 10' is singulated to form a plurality of semiconductor dies 10 that are separated from each other. In some embodiments, the substrate 10' is cut through the notches 11 and/or 12.

Referring to fig. 14E, semiconductor die 10 may be attached to a carrier 73, such as tape (tape).

Referring to fig. 14F, a light absorbing layer 30 is formed on the semiconductor die 10 to cover the surface 102 and the surface 103 of the semiconductor die 10. In some embodiments, a light absorbing material is prepared. The viscosity of the light absorbing material may be in the range of about 2Cp to about 11 Cp. The light absorbing material may be formed on the semiconductor die 10 by a spray coating process. After the light absorbing material is coated on the semiconductor die 10, the light absorbing material may be thermally cured by, for example, a baking process to form the light absorbing layer 30.

Referring to fig. 14G, the carrier 73 is removed, and the semiconductor package 1f is produced.

Fig. 15A, 15B and 15C illustrate various stages of a method of manufacturing a semiconductor package structure 1h according to some embodiments of the present disclosure.

Fig. 15A depicts a stage subsequent to that depicted in fig. 14A. Referring to fig. 15A, the semiconductor die 10 is provided without forming a stepped profile or tapered portion. More specifically, the substrate 10' is singulated without forming recessed portions or notches. In some embodiments, the semiconductor die 10 may be attached to and supported by a carrier, such as a tape.

Referring to fig. 15B, a first coating process is performed to coat the light-absorbing material on the surface 102 and the surface 103 of the semiconductor die 10, and a first curing process, such as a baking process, may be performed to cure the light-absorbing material. In some embodiments, the edges of the carrier may be slightly distorted and the light absorbing material may be inserted into the space between the passivation layer 40 and the carrier. As a result, the semiconductor package structure 1a' is produced.

Referring to fig. 15C, a second coating process is performed to partially coat the light absorbing material on the semiconductor die 10, and a second curing process, such as a baking process, may be performed to cure the light absorbing material. As a result, the light absorbing layer 30 may have a thicker portion and a thinner portion adjacent to the surface 101. As a result, the semiconductor package structure 1h is produced.

According to an embodiment of the present disclosure, a semiconductor package structure includes a light absorbing layer covering a backside surface and a side surface of a semiconductor die. The light absorbing layer may prevent light from being incident on the semiconductor die. According to embodiments of the present disclosure, the light absorbing layer may include thicker portions disposed at corners of the active surface and the side surfaces, which may further reduce light incident to the active layer of the semiconductor die. According to an embodiment of the present disclosure, the light absorbing layer may include a thicker portion disposed at a corner of the backside surface and the side surface, which may compensate for a thickness occurring due to a sagging phenomenon. The light absorbing layer may enhance the reliability of the semiconductor package structure. The light absorbing layer may prevent delamination of the passivation layer from the semiconductor die.

Unless otherwise specified, spatial descriptions such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "above," "below," and the like are indicated with respect to the orientation shown in the figures. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the embodiments of the present disclosure advantageously do not deviate from such arrangements.

As used herein, the terms "approximately," "substantially," "essentially," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can refer to an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are "substantially" identical or equal if the difference between the two numerical values is less than or equal to ± 10% of the mean of the values, e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%.

Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms "a" and "the" may include a plurality of the referents unless the context clearly dictates otherwise.

As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to pass an electrical current. Conductive materials generally indicate those materials that present little or zero opposition to current flow. One measure of conductivity is siemens per meter (S/m). Typically, the conductive material has a conductivity greater than about 10⁴S/m (e.g., at least 10)⁵S/m or at least 10⁶S/m) of the above-mentioned material. Material guideThe electrical rate may sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such a range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not to be considered in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be a difference between process reproductions in this disclosure and actual devices. There may be other embodiments of the disclosure that are not specifically shown. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.