阅读说明：本技术 半导体装置和包括该半导体装置的电子设备 (Semiconductor device and electronic apparatus including the same ) 是由 徐焰 姬忠礼 陈余 于 2020-06-11 设计创作，主要内容包括：本申请涉及半导体装置和包括该半导体装置的电子设备。该半导体装置包括：第一半导体层；第二芯片；导热层,与所述第一半导体层和所述第二芯片层叠设置并且位于所述第一半导体层与所述第二芯片之间,用于在所述导热层内传导来自所述第一半导体层和/或所述第二芯片的热量,所述导热层在水平方向的导热系数大于或等于在垂直方向的导热系数,且大于所述第一半导体层的导热系数；以及第一导电柱,贯穿所述导热层,以使得所述第一半导体层与所述第二芯片通过所述第一导电柱实现电互连,其中所述第一导电柱与所述导热层电绝缘,所述第一导电柱的延伸方向为所述垂直方向。采用该半导体装置,可以降低局部热点效应。(The present application relates to a semiconductor device and an electronic apparatus including the semiconductor device. The semiconductor device includes: a first semiconductor layer; a second chip; a heat conduction layer, disposed in a stacked manner with the first semiconductor layer and the second chip and between the first semiconductor layer and the second chip, for conducting heat from the first semiconductor layer and/or the second chip in the heat conduction layer, wherein a thermal conductivity of the heat conduction layer in a horizontal direction is greater than or equal to a thermal conductivity of the heat conduction layer in a vertical direction and is greater than a thermal conductivity of the first semiconductor layer; and the first conductive column penetrates through the heat conduction layer, so that the first semiconductor layer and the second chip are electrically interconnected through the first conductive column, wherein the first conductive column is electrically insulated from the heat conduction layer, and the extending direction of the first conductive column is the vertical direction. By using the semiconductor device, local hot spot effect can be reduced.)

1. A semiconductor device, comprising:

a first semiconductor layer;

a second chip;

a heat conduction layer, disposed in a stacked manner with the first semiconductor layer and the second chip and between the first semiconductor layer and the second chip, for conducting heat from the first semiconductor layer and/or the second chip in the heat conduction layer, wherein a thermal conductivity of the heat conduction layer in a horizontal direction is greater than or equal to a thermal conductivity of the heat conduction layer in a vertical direction, and a thermal conductivity of the heat conduction layer in the horizontal direction is greater than a thermal conductivity of the first semiconductor layer; and

the first conductive column penetrates through the heat conduction layer, so that the first semiconductor layer and the second chip are electrically interconnected through the first conductive column, wherein the first conductive column is electrically insulated from the heat conduction layer, and the extending direction of the first conductive column is the vertical direction.

2. The semiconductor device according to claim 1, wherein the thermally conductive layer has a plurality of through holes, and one or more of the first conductive pillars pass through one of the through holes.

3. The semiconductor device according to claim 1 or 2, wherein the heat conductive layer and the first semiconductor layer are bonded and connected.

4. The semiconductor device according to any one of claims 1 to 3, further comprising an insulating material that covers a surface of the thermally conductive layer, wherein the first conductive pillar further penetrates the insulating material.

5. The semiconductor device according to any one of claims 1 to 4, further comprising:

an insulating layer arranged at least partially around and extending along the first conductive post for isolating the first conductive post from the thermally conductive layer for electrical insulation.

6. The semiconductor device according to claim 5, further comprising:

a filler material disposed in the thermally conductive layer and between the thermally conductive layer and the insulating layer.

7. The semiconductor device of claim 6, wherein the fill material is compatible with a through-silicon-via (TSV) process, which refers to an electrical interconnection achieved by filling a via in a silicon wafer with a conductive material.

8. The semiconductor device according to any one of claims 1 to 7, wherein the first semiconductor layer is a first chip or a first interconnect layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein when the first semiconductor layer is a first chip, the first conductive pillar further penetrates the first chip.

10. The semiconductor device according to claim 9, further comprising:

a third semiconductor layer disposed on a side of the first semiconductor layer distal from the thermally conductive layer, the third semiconductor layer electrically coupled with the electrically conductive post.

11. The semiconductor device according to any one of claims 1 to 10, wherein the thermally conductive layer comprises a carbon-based material, a metal material, or a combination thereof.

12. The semiconductor device according to claim 11, wherein the carbon-based material comprises a graphene film.

13. The semiconductor device of claim 1, wherein the thermally conductive layer is at least 5um thick.

14. An electronic device, comprising: the semiconductor device according to any one of claims 1 to 13.

15. A heat spreader, comprising:

a carbon-based material layer having a thermal conductivity in a horizontal direction greater than or equal to a thermal conductivity in a vertical direction; and the number of the first and second groups,

the carbon-based material layer, the extending direction of first nonmetal post is vertical direction, the material of first nonmetal post is insulating or semiconductor, wherein the part that first nonmetal post and carbon-based material layer contact is insulating material.

16. The heat spreader according to claim 15, wherein the roughness of the surface of the heat conductive layer is 1nm or less.

17. Heat spreader according to claim 15 or 16, wherein the diameter of the first non-metallic pillars is between 10 μ ι η and 40 μ ι η.

Technical Field

Embodiments disclosed herein relate to the field of semiconductor technology, and more particularly, to a semiconductor device and an electronic apparatus including the same.

Background

During the packaging of integrated circuits, semiconductor chips may be bonded to other components such as interconnect layers or package substrates, and the resulting package structure is referred to as a three-dimensional integrated circuit (3D IC). In 3D ICs, heat dissipation is a challenge.

In a typical 3D IC (e.g., a Chip-on-Wafer-on-Substrate (CoWoS) package), heat may build up in an interior region at the bottom of the Chip stack, resulting in significant local temperature peaks (also known as hot spots). In addition, hot spots due to heat generated by high power chips may cause thermal crosstalk problems to surrounding chips, thereby adversely affecting the performance of the surrounding chips and the reliability of the entire 3D IC package. This local hot spot problem, discussed in the example of 3DIC, is also prevalent in other semiconductor chip package structures (e.g., 2.5D IC packages).

Disclosure of Invention

The present application provides a semiconductor device for solving the problem of local hot spots in the semiconductor device to a certain extent. In addition, the application also provides electronic equipment which comprises the semiconductor device.

According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a first semiconductor layer; a second chip; a heat conductive layer, disposed in a stacked manner with the first semiconductor layer and the second chip and between the first semiconductor layer and the second chip, for conducting heat from the first semiconductor layer and/or the second chip in the heat conductive layer, wherein a thermal conductivity of the heat conductive layer in a horizontal direction is greater than or equal to a thermal conductivity of the heat conductive layer in a vertical direction; and the first conductive column penetrates through the heat conduction layer, so that the first semiconductor layer and the second chip are electrically interconnected through the first conductive column, wherein the first conductive column is electrically insulated from the heat conduction layer, the extending direction of the first conductive column is the vertical direction, and the heat conduction coefficient of the heat conduction layer in the horizontal direction is greater than that of the first semiconductor layer.

The first semiconductor layer and/or the second chip may generate heat in operation, and the heat may be unevenly distributed in the horizontal direction. Because the heat conduction layer is stacked with the first semiconductor layer and the second chip, and the heat conduction coefficient of the heat conduction layer in the horizontal direction is larger than or equal to that in the vertical direction, heat can be diffused in the horizontal direction, the effect of horizontal soaking is achieved, and the local hot spot effect is slowed down or eliminated. Furthermore, a first conductive pillar is disposed in the thermally conductive layer to electrically interconnect the first semiconductor layer and the second chip. Because the heat-conducting layer is also the conducting material usually, through making the heat-conducting layer carry out electrical isolation with first electrically conductive post, the electrical function of first electrically conductive post can not receive the influence, ensures that semiconductor device can normally work.

In some embodiments, the thermally conductive layer has a plurality of through holes, and one or more of the first conductive pillars pass through one of the through holes.

The number of the through holes and the conductive pillars can be determined according to the specific requirements of the chip. Typically, the interconnection between chips is achieved by a plurality of vias. The size of the conductive pillars is generally determined by the semiconductor fabrication process as well as the size, performance, etc. of the chip. The through holes with large apertures are easier to manufacture and lower in cost. Therefore, in order to reduce the production cost of the heat conductive layer, a through hole capable of accommodating a plurality of conductive posts may be used. In some cases, to promote uniform thermal performance, smaller vias may be made, leaving as much of the thermally conductive layer as possible. That is, one via only accommodates one conductive post.

In some embodiments, the thermally conductive layer is bonded to the first semiconductor layer.

The bonding connection is a connection without adhesive and welding layer, and can remarkably reduce the thermal resistance between the heat conduction layer and the first semiconductor layer, so that the heat can be rapidly expanded in the horizontal direction through the heat conduction layer, and the soaking effect is improved.

In some embodiments, the semiconductor device further includes an insulating material covering a surface of the thermally conductive layer, and the first conductive pillar further penetrates through the insulating material.

Because the insulating material covers the surface of the heat conducting layer, the conducting path between the heat conducting layer and other elements is cut off, and the electrical operation of the semiconductor device is not influenced.

In some embodiments, the semiconductor device further comprises: an insulating layer arranged at least partially around and extending along the first conductive post for isolating the first conductive post from the thermally conductive layer for electrical insulation.

By providing an insulating layer around the first conductive post, the first conductive post can be electrically insulated from the thermally conductive layer.

In some embodiments, the semiconductor device further comprises: a filler material disposed in the thermally conductive layer and between the thermally conductive layer and the insulating layer.

In the process of drilling the heat conductive layer, through holes with relatively large apertures may be manufactured to reduce the cost, and therefore, a filling material is required to fill the through holes to reduce the difficulty of forming the conductive pillars.

In some embodiments, the fill material is compatible with through-silicon via (TSV) processes, which refers to electrical interconnections achieved by filling conductive material in vias of a silicon wafer.

Since the filling material is compatible with the TSV process, the filling material can be formed by using a known semiconductor manufacturing process during the punching process, so that the filling material has good process compatibility.

In some embodiments, the first semiconductor layer is a first chip or a first interconnect layer.

In some embodiments, when the first semiconductor layer is a first chip, the first conductive pillar further penetrates through the first chip.

In some embodiments, the semiconductor device further comprises: a third semiconductor layer disposed on a side of the first semiconductor layer distal from the thermally conductive layer, the third semiconductor layer electrically coupled with the electrically conductive post.

In some embodiments, the thermally conductive layer comprises a carbon-based material, a metallic material, or a combination thereof.

In some embodiments, the carbon-based material comprises a graphene film.

In some embodiments, the thermally conductive layer is at least 5um thick.

In a second aspect, there is provided an electronic device comprising: the semiconductor device according to the first aspect.

In some embodiments, the electronic device comprises: a switch, router, mobile phone, Personal Digital Assistant (PDA), navigation device, set top box, music player, or video player.

In a third aspect, there is provided a heat equalizing sheet comprising: a carbon-based material layer having a thermal conductivity in a horizontal direction greater than or equal to a thermal conductivity in a vertical direction; and the first nonmetal column penetrates through the carbon-based material layer, the extending direction of the first nonmetal column is the vertical direction, the first nonmetal column is made of insulating or semiconductor materials, and the part of the first nonmetal column, which is in contact with the carbon-based material layer, is made of insulating materials.

The heat spreader may be used in a semiconductor package structure for heat spreading a chip in the semiconductor package structure. The first non-metallic posts allow electrical interconnect structures to be fabricated therein, and therefore, do not affect the electrical performance of the semiconductor chip while soaking the same. Since the portion of the first non-metallic pillar in contact with the carbon-based material layer is an insulating material, if the conductive pillar is formed in the first non-metallic pillar, the insulating material can achieve electrical insulation of the conductive pillar.

In some embodiments, the roughness of the surface of the thermally conductive layer is less than or equal to 1 nm.

In some embodiments, the first non-metallic posts are between 10 μm and 40 μm in diameter.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to be used to limit the scope of the disclosure.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings, wherein like reference numerals generally represent like parts throughout the exemplary embodiments thereof.

Fig. 1A illustrates a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 1B illustrates a cross-sectional view of a semiconductor device, according to some embodiments of the present disclosure;

fig. 2 shows a cross-sectional view of a cofos packaged semiconductor device according to the conventional art;

fig. 3A illustrates a cross-sectional view of a copos packaged semiconductor device according to some embodiments of the present disclosure;

FIG. 3B illustrates an enlarged cross-sectional view of a portion of the semiconductor device shown in FIG. 3A;

FIG. 4 shows a schematic diagram of a simulation structure according to an embodiment of the present disclosure;

fig. 5A to 5Q respectively show schematic views of stages in a process of manufacturing a semiconductor device according to a first embodiment disclosed in the present application;

fig. 6A and 6B are schematic views each showing a first variation of the manufacturing method according to the first embodiment disclosed in the present application;

fig. 7A to 7D are schematic views each showing a second variation of the manufacturing method according to the first embodiment disclosed in the present application;

fig. 8A to 8H show schematic diagrams of several stages in a process of manufacturing a semiconductor device according to a second embodiment of the present disclosure, respectively;

fig. 9A to 9C show schematic diagrams of several stages in a process of manufacturing a semiconductor device according to a third embodiment of the present disclosure, respectively;

fig. 10A to 10I show schematic diagrams of several stages in a process of manufacturing a semiconductor device according to a fourth embodiment of the present disclosure, respectively;

11A-11J respectively show schematic diagrams of several stages in a process of manufacturing a semiconductor device, according to a fifth embodiment of the present disclosure; and

fig. 12 illustrates a flow chart of a method for fabricating a semiconductor device according to some embodiments disclosed herein.

In accordance with common practice, the various features shown in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Additionally, some of the figures may not depict all of the components of a given system, method, or apparatus. Finally, throughout the specification and drawings, like reference numerals may be used to refer to like features.

Detailed Description

Embodiments related to the present application will be described in more detail below with reference to the accompanying drawings. The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Any reference to direction or orientation is intended only to facilitate description and not to limit the scope of the invention in any way. Relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "upward," "downward," "top" and "bottom" as well as derivatives thereof (e.g., "horizontally," "upward," "downward," etc.) are used in the discussion to refer to the orientation as then described or as shown in the drawings. These relative terms are for convenience of description only and do not require that the apparatus be constructed or operated in a particular orientation.

Semiconductor devices and methods of fabricating the same for mitigating or eliminating local hot spot problems are provided according to various exemplary embodiments. Intermediate stages in forming the semiconductor device are shown and various embodiments and variations thereof are discussed herein. Like reference numerals are used to refer to like elements throughout the various views and example embodiments.

Fig. 1A shows a cross-sectional view of a semiconductor device 100. The semiconductor device 100 includes a first semiconductor layer 114, for example, a first chip (logic chip or memory chip) or a first interconnect layer (interposer). The thermally conductive layer 102 is stacked with the first semiconductor layer 114, and by virtue of its thermally conductive properties, the thermally conductive layer 102 allows heat to be conducted internally from either side of the thermally conductive layer 102 (note that the first semiconductor layer 114 is on one side of the thermally conductive layer 102, and the other side of the thermally conductive layer 102 is away from the first semiconductor layer 114). In the example shown in fig. 1A, the thermally conductive layer 102 allows heat to be conducted from above and/or below the thermally conductive layer 102 within it. For convenience, the orientation of the various components will be described below in connection with the drawings, however, as noted above, these orientation-related terms are merely for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation.

For example, a second chip may be disposed over the thermally conductive layer 102, and the first semiconductor layer 114 may also be composed of the first chip, and a third semiconductor layer may also be disposed under the first semiconductor layer 114, and the third semiconductor layer may also be composed of the third chip. Thus, there may be a source of heat above and below the heat conductive layer 102. The thermal conductivity of the thermally conductive layer 102 in the horizontal direction may be greater than or equal to the thermal conductivity in the vertical direction to facilitate thermal conduction in the horizontal direction. In addition, the thermal conductivity of the thermally conductive layer 102 in the horizontal direction is larger than that of the first semiconductor layer 114. By means of the heat conductive layer 102, the heat from above and/or below the heat conductive layer 102 may be distributed as evenly as possible in the entire plane of the heat conductive layer 102. In this manner, localized hot spot problems in semiconductor devices may be mitigated or eliminated.

The thermally conductive layer 102 and the first semiconductor layer 114 may be bonded, for example, by an adhesive-free or solder-free bonding or bonding attachment using a wafer bonding process or a Surface Activated Bonding (SAB) process. This can significantly reduce the thermal resistance between the thermally conductive layer 102 and the first semiconductor layer 114 so that hot spots within the first semiconductor layer 114 can quickly spread through the thermally conductive layer 102.

The conductive posts 130 extend through the thermally conductive layer 102 to electrically interconnect the second chip above the thermally conductive layer 102 with the first semiconductor layer 114. In one example, electrical contacts to the first semiconductor layer 114 may be provided on the upper surface, forming conductive interconnects with the conductive pillars 130. In another example, electrical contacts of the first semiconductor chip 114 may be disposed on a lower surface of the first semiconductor layer 114, and the conductive pillars 130 may penetrate through the first semiconductor layer 114 and the thermally conductive layer 102 to enable electrical interconnection of the second chip above the thermally conductive layer 102 with the first semiconductor layer 114. In yet another example, where a third semiconductor layer is disposed below the first semiconductor layer 114, the conductive pillars 130 can also extend through the first semiconductor layer 114 and the thermally conductive layer 102 to provide vertical interconnection between the second chip above the thermally conductive layer 102 and the third semiconductor layer below the first semiconductor layer 114.

The conductive post 130 is electrically insulated from the thermally conductive layer 102 for insulative isolation. For example, electrical isolation may be achieved by disposing one or more layers of dielectric between conductive pillars 130 and conductive layer 102, which may be several tens of nanometers thick, depending on the particular process. In some examples, to reduce the difficulty of opening the thermally conductive layer 102, a larger aperture opening is made in the thermally conductive layer 102. In this case, the openings may be filled with a filling material such as silicon or silicon dioxide compatible with a through-silicon-via (TSV) process, which refers to an electrical interconnection achieved by filling a conductive material in a via of a silicon wafer. Such a structure is compatible with a 3D or 2.5D IC package, etc., and thus is very conveniently applied to the related art. The conductive pillars 130 may include a barrier layer, a seed layer, and a through conductor (e.g., copper), which may be implemented through a TSV process. It should be understood that the term "conductive post" does not mean that the cross-sectional shape is circular, for example, the cross-sectional shape may also be oval, polygonal, and other various suitable shapes. In addition, the term "conductive pillar" also does not mean that the cross-sectional shape or size is the same along the length direction of the entire conductive pillar, for example, the conductive pillar may have different shapes, sizes, etc. in different cross sections in its extending direction (e.g., the vertical direction in fig. 1A).

For example, the shape of the conductive pillars is related to the shape of the openings, which are affected by different opening processes. For example, in a laser drilling process, the shape of the hole is typically a structure with a larger upper dimension and a smaller lower dimension. In the bosch process for TSVs, the shape of the hole is generally cylindrical. The structural formation of the conductive posts may also result in voids within the structure due to process limitations.

The thermally conductive layer 102 may be made of various thermally conductive materials, for example, carbon-based materials, metallic materials, or combinations thereof, particularly graphene films. The thickness of the thermally conductive layer 102 can be at least 5um, such as 5um to 1000um, for example, 10um to 300um, for example, 20um to 100um, and particularly, 30um to 60 um. In a conventional semiconductor process, a functional layer of a semiconductor device is usually formed by a thin film deposition process such as Chemical Vapor Deposition (CVD) or a thin film synthesis process, and the thickness of the thin film formed by the semiconductor process is usually in the nanometer level. By using a thicker heat conducting layer 102, embodiments disclosed herein may achieve good soaking effects, better eliminating local hot spot effects. The planar thermal conductivity of the heat conduction layer 102 can be more than 600W/mk, and the planar thermal conductivity can be more than 1000W/mk and even more than 1200W/mk by using the graphene-based film.

The graphene film is formed by stacking a plurality of graphene layers in a spiral stacking manner. Unlike graphite, graphene is constructed with a regular AB stack (half of the carbon atoms of a graphene layer are located on another atom of the underlying graphene, while the other half are located on the center of the hexagon formed by the carbon atoms in the underlying graphene). For example, the graphene film may be made of a graphene nanosheet, and may be made of a graphene nanosheet having a thickness of 5nm or less and a planar dimension of 1 to 100 μm, for example. The graphene film may also be composited with other materials, such as Cu, SiC, Si, SiO₂、Al₂O₃The materials are compounded, so that higher strength is realized under the condition of maintaining high plane heat conductivity coefficient, and the process for manufacturing the through hole in the heat conduction layer 102 is matched. For example, the composite process may be CVD deposition of enhanced materials on and within the graphene film, such as deposition of metal, non-metal or metal/non-metal oxides, nitrides, carbides, fluorides, etc. The composite process may also be carried out by infiltrating metal, such as Al, Cu, etc., on the surface and inside of the graphene film at high temperature and high pressure. It will be appreciated by those skilled in the art that other suitable processes may also be used to composite the graphene film with other materials.

The graphene film has excellent plane thermal conductivity, for example, the plane thermal conductivity of the graphene film can reach 1500-1700W/mk, so that heat can be effectively conducted in the plane of the graphene film. However, the material of the heat conductive layer 102 is not limited to the graphene-based film, and a graphene-based composite film, such as a graphite/metal composite film, a graphite/metal composite film, a metal/carbon composite film, or even a copper alloy film, may be used. Of these materials, graphene films are more suitable for conducting heat in the plane of the thermally conductive layer 102 due to their higher planar thermal conductivity, thereby alleviating or eliminating the problem of localized hot spots.

Since most thermally conductive materials are also electrically conductive materials, the semiconductor device 100 may further include an insulating material covering the surface of the thermally conductive layer 102 to achieve insulation. The surface of the heat conductive layer 102 includes not only the upper surface and the lower surface but also the side surface inside the through hole. The insulating material may comprise different structures according to different manufacturing processes, for example, in the example shown in fig. 1A, the insulating material comprises a first insulating layer 110 and a second insulating layer 116, wherein the first insulating layer 110 is disposed on the lower surface and the side surfaces of the heat conductive layer 102, and the second insulating layer 116 is disposed on the upper surface of the heat conductive layer 102. The presence of these insulating layers prevents electrically conductive coupling of the thermally conductive layer 102 to various components within the semiconductor device 102, thereby avoiding damage to the electrical performance of the semiconductor device 102. The insulating layers can be made of low dielectric insulating materials, and the temperature resistance and other properties can meet the requirements of the subsequent semiconductor manufacturing process. Alternative materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicate glass, carbon-doped silicon oxide, and polymers. The first insulating layer 110 and the second insulating layer 116 may each include multiple layers of materials, such as passivation layers, barrier layers, dielectric layers, etc., and may be fabricated using physical deposition or chemical deposition methods.

Additionally, as shown in fig. 1A, the insulating layer 128 at least partially surrounds the conductive post 130 and extends along the conductive post 130 for electrically insulating the conductive post 130 from the thermally conductive layer 102. The conductive post 130 may be disposed within the first via 126, wherein the first via 126 may extend through the first semiconductor layer 114, the first insulating layer 110, the thermally conductive layer 102, the second insulating layer 116, and so on. An insulating layer 128 is formed on the sidewalls of the first via 126. The insulating material forming the insulating layer 128 may be at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, fluorine-containing silicon glass, carbon-doped silicon oxide, and polymer. The insulating layer 128 may comprise multiple layers of materials, such as passivation layers, barrier layers, dielectric layers, etc., and may be fabricated using physical deposition or chemical deposition methods. It should be understood that the dashed box represents only the horizontal extent of the first via 126.

In some embodiments, the semiconductor device 100 may further include a second via 104, the second via 104 penetrating at least the thermally conductive layer 102, and an aperture size of the second via 104 being larger than an aperture size of the first via 126 so as to surround the first via 126. The second via 104 may reduce the process requirements for fabricating the semiconductor device 100. For example, the larger second via 106 reduces alignment requirements when forming the first via 126, thereby facilitating increased yield and reduced manufacturing costs.

Optionally, the semiconductor device 100 may further include a filler material 112, the filler material 112 being disposed between the thermally conductive layer 102 and the insulating layer 128. The second via 104 may not be filled during the deposition of the insulating layer. Accordingly, the filling material 112 may be formed to fill the second via hole 104. The fill material 112 may be an insulating material (e.g., silicon oxide), a semiconductor material (e.g., silicon), or a combination of both. The fill material 112 is generally compatible with Through Silicon Via (TSV) processes, thereby facilitating the fabrication of the first via 126. Through silicon vias refer to electrical interconnections made by filling vias in a silicon wafer with a conductive material. Optionally, the semiconductor device 100 may further include an insulating layer 124, which may serve as passivation or protection during the manufacturing process.

As described above, the semiconductor device 100 may be compatible with various packaging processes. For example, the semiconductor device 100 may be applied in a 3D or 2.5D IC package. For example, the first semiconductor layer 114 may be a first chip, and a second chip may be disposed over the semiconductor device 100, the second chip may be electrically coupled with the conductive pillars 130. In this way, vertical interconnection between the first chip and the second chip can be achieved through the TSVs. For example, the first chip may have a thickness of 55um, a silicon-based material, and a thermal conductivity of about 90W/mK. It should be understood that the above parameters are provided as examples only and may be adapted according to the specific application.

Further, a third semiconductor layer may be disposed below the first semiconductor layer 114, wherein the third semiconductor layer may be a third chip or an interconnect layer. For example, the third semiconductor chip may be electrically coupled with the conductive posts 130 through bumps, solder balls, or the like, thereby enabling interconnection with the second chip or other chips above the second chip. In one particular example, a High Bandwidth Memory (HBM) chip stack includes a bottom chip and a stack of multiple core chips above the bottom chip. The bottom chip may be implemented as the first semiconductor layer 114 shown in fig. 1A, and the core chip may be disposed over the structure shown in fig. 1A.

It should be appreciated that since the semiconductor device 100 is not limited to implementation in an interconnect layer application, the semiconductor device 100 may also be applied to 2.5D IC or 3D IC packaging approaches without an interconnect layer, such as, for example, the enhancement of planar thermal soaking capability of a multi-layer chip inside an integrated fan-out (INFO) package.

Fig. 1B illustrates a cross-sectional view of a semiconductor device 100, according to some embodiments disclosed herein. Unlike fig. 1A, in fig. 1B, the aperture size of the second through hole 104 is large so as to be able to accommodate the first through hole 126 and the third through hole 132. A second conductive post 134 is disposed within the third via 132 and surrounded by the second via 104. It should be understood that more than two vias may be formed within the second via 104. The rest of fig. 1B is substantially the same as fig. 1A, and is not described again here. Compared with the semiconductor device 100 shown in fig. a, the semiconductor device 100 shown in fig. 1B further reduces the requirements for the size, shape, and the like of the second via hole 104, and reduces the difficulty and cost of the hole forming technology. In addition, it allows the filling material to be formed using a coating process in addition to the deposition process, so that the cost can be significantly reduced.

The semiconductor apparatus 100 can be applied to various electronic devices, particularly communication devices, such as a switch, a router, a mobile phone, a Personal Digital Assistant (PDA), a navigation device, a set-top box, a music player, a video player, and the like. In addition, the semiconductor device 100 may also be compatible with a variety of different package types, such as a CoWOS package and an INFO package. Applications of the semiconductor device 100 according to some embodiments disclosed herein will be described below with reference to a specific application. Fig. 2 shows a cross-sectional view of a cofos packaged semiconductor device 200 according to the conventional art. The CoWOS packaging technology can realize the integration of a logic chip and a memory chip in the same chip package. As shown in fig. 2, the semiconductor device 200 includes a controller 202, core chips 204, and a bottom chip 206, wherein the number of the core chips 204 is four. It should be understood that more or fewer core chips 204 may also be used. The core chip 204 and the bottom chip 206 form a multi-layer memory chip stack, e.g., a High Bandwidth Memory (HBM) chip stack.

The controller 202 and the underlying die 206 are disposed side-by-side on an interconnect layer 208, and the interconnect layer 208 is in turn disposed on a package substrate 210. The encapsulation material 212 encapsulates these components and forms external contacts on the package substrate 210, thereby forming a chip package. A physical layer (PHY) interface may be provided on the controller 202 and the underlying chip 206 to allow data communication between the chips.

As described above, there is a local hot spot problem in a 3D IC (e.g., HBM chip), and the overheating and over-temperature of the chip may become one of the key issues for heat dissipation of the subsequent 3D IC chip. For example, the junction temperature specification of an HBM chip using a DRAM process is only 95 degrees, significantly lower than the junction temperature specification of a peripheral CMOS chip by 105 degrees. The heat of the bottom chip cannot be effectively led out after the multiple layers of HBM chips are stacked, and the bottom chip becomes a bottleneck of chip heat dissipation.

The main reason for the overheating of the HBM chip is the insufficient thermal uniformity of the silicon-based chip itself. Taking a 4-layer second generation high bandwidth memory (HBM2) chip stack as an example, the local hot spot maximum temperature of the bottom chip may differ by 24 ℃ from the minimum temperature.

The mainstream measures for cooling the HBM chip in the industry include: more thermally conductive dummy solder balls are arranged, a hybrid bonding process with higher interconnect density is adopted, and the like. According to the schemes, the interlayer thermal resistance is improved by increasing the heat conduction area among stacked HBM chips, the influence of heat accumulation on the temperature rise of the bottom chip can be relieved, and the problem of local hot spots of the HBM chips cannot be solved by improving the plane extension thermal resistance layer of the chips. The planar soaking capability of the chip needs to be improved, the rapid expansion of the local hot spot heat of the chip in the planar direction is realized, and the planar thermal resistance of the chip is reduced.

Fig. 3A illustrates a cross-sectional view of a CoWoS packaged semiconductor device 300, according to some embodiments disclosed herein. Unlike the semiconductor device 200 shown in fig. 2, the semiconductor device 300 is provided with a thermally conductive layer 314 at the bottom chip 306. The rest of fig. 3A is substantially the same as fig. 2, and will not be described again.

Fig. 3B shows an enlarged view of a portion 316 of the semiconductor device 300. As shown in fig. 3, the semiconductor device 300 includes a bottom chip 306, a first insulating layer 318 disposed over the bottom chip 306, a thermally conductive layer 314 disposed over the first insulating layer 318, and a second insulating layer 320 disposed over the thermally conductive layer 314. In addition, an insulating layer 322 may be disposed on the sidewall of the via hole 330 and over the second insulating layer 320. Conductive pillars 328 are disposed inside vias 330, forming a through-silicon via (TSV) structure, and are insulated from thermally conductive layer 314 by insulating layer 322. The interconnect layer 308 is interconnected with the conductive posts 328 by solder balls 324, and the core chip 304 is interconnected with the conductive posts 328 by solder balls 326. In this manner, the I/O pins of the core chip 304 are vertically interconnected with the I/O pins of the bottom chip 306 by conductive posts 328, and the bottom chip 306 is electrically interconnected with the interconnect layer 308 by solder balls 326. Logic chips, such as controller 302, may also be assembled on other areas of interconnect layer 308. Electrical interconnection of the bottom chip 306, the core chip 304, the controller 302, and the package substrate 310 is achieved through an interconnect layer 308. It should be understood that the portion 316 of the semiconductor device 300 may also be implemented using the semiconductor device 100 shown in fig. 1A-1B.

Additionally or alternatively, in the semiconductor device 300 shown in fig. 3A, a thermally conductive layer (not shown) may also be disposed over the controller 302. In this way, the packaging space within the semiconductor device 300 can be fully utilized, and the soaking effect of the controller 302 is improved. In an example embodiment, the controller 302 may also be thinned to more conveniently accommodate the thermally conductive layer.

FIG. 4 shows a schematic diagram of a simulation structure according to one embodiment of the present disclosure. In this embodiment, a Printed Circuit Board (PCB)408, a substrate 406 disposed over PCB 408, an HBM2 memory chip module 404 disposed over substrate 406, and an Epoxy (EMC)402 disposed over HBM chip stack 404. In this embodiment, a graphene-based thermally conductive layer is integrated over the underlying chip, for example as shown in fig. 3A-3B.

In conventional technology, the highest temperature point of the 4-layer HBM2 chip is 24 ℃ higher than the lowest temperature point of the bottom layer chip in the 2.0Gbps mode of operation. And (3) constructing a simulation model aiming at the 4-layer HBM2 chip scene, and reconstructing a scene that the temperature of the highest temperature point in the bottom layer chip is higher than the lowest temperature by 24 ℃. On the basis, a group of simulation conditions are added, and a heat conduction material with the thickness of 50um and the plane heat conduction coefficient of 1500W/mk is added on the bottom chip.

The size of the HBM chip stack 404 is 11mm x 8mm and the power of the bottom chip is 4W, the power of each DRAM HBM chip is 0.75W (4W total). During the simulation, the temperature of the EMC 402 was fixed at 25 degrees of room temperature. The surface temperature of the bottom chip in the conventional technology is 63-87 ℃ (Δ T ═ 24 ℃). According to the embodiment disclosed in the application, the surface temperature of the bottom chip is 65-75 ℃ (Δ T ═ 12 ℃). The thermal simulation result shows that the plane temperature difference of the bottom chip can be reduced from 24 ℃ to 12 ℃, namely the plane soaking capacity of the silicon substrate layer chip is improved by 1 time. The chip temperature specification of the memory chip module in the same 3D IC chip package is improved by 12 ℃.

As described above, other heat conductive materials, such as graphene-based composite films, graphite/metal composite films, metal/carbon composite films, and even copper alloy films, may be used in addition to the graphene films.

These non-graphene film materials have a planar thermal conductivity of not less than 1500W/mk, but not less than 400W/mk. According to the simulation model shown in fig. 4, when a thermally conductive material with a thickness of 50um and a thermal conductivity of 400W/mk is integrated on the surface of the bottom chip, the thermal simulation result shows that the planar temperature difference of the bottom chip can be reduced from 24 ℃ to 18.8 ℃. Therefore, even if the graphene film is not adopted, the plane heat conduction capability of the silicon-based chip can be improved by over 50 percent.

Example embodiments disclosed herein will be described with reference to a specific environment, for example, a chip on wafer on substrate (CoWOS) package. More specifically, the CoWOS package includes a multi-layer memory chip stack including an underlying chip and one or more layers of core chips disposed on the underlying chip. However, example embodiments disclosed herein are also applicable to other package types and chip structures, including other three-dimensional integrated circuit (3D IC) packages, as well as 2.5D IC packages, and the like.

Fig. 5A-5Q show schematic diagrams at various stages in the manufacture of a semiconductor device according to a first embodiment disclosed herein. Fig. 5A shows a cross-sectional view of graphene film 502. For example, the graphene film 502 can be about 55um thick and the planar thermal conductivity can be 1500-1700W/mk. It should be understood that the thickness and planar thermal conductivity of the graphene film may also vary depending on the particular application requirements and manufacturing process. For example, graphene film 502 may be purchased commercially. In addition, a single-layer graphene oxide dispersion liquid with a large size (a plane size of more than 20 um) can be used to prepare a slurry, and the slurry is coated to form a film, and the graphene film 502 with a required thickness is manufactured through multiple heat treatment processes and compaction processes. One skilled in the art will appreciate that any other suitable process may also be used to fabricate graphene film 502.

According to predefined locations, vias 504 can be formed in graphene film 502. Fig. 5B shows a plan view of the graphene film 502, and fig. 5C shows a cross-sectional view at a position corresponding to the section a-a' of fig. 5B. Fig. 5B and 5C show a plurality of vias 504. It should be understood that the number, shape, size, and distribution position of the through holes 504 shown in fig. 5B and 5C are provided as examples, and the number, shape, size, and distribution position of the through holes 504 may be determined according to the situation of a specific application. For example, in a chip stack such as a High Bandwidth Memory (HBM), the size and distribution location of vias 504 may be determined according to the requirements of the vertical interconnection of the underlying chip and the core chip in the HBM chip stack.

To reduce the need for high precision alignment for back-end processing, the diameter of the via 504 may be larger than the diameter of the through-silicon vias (TSVs) of the bottom chip and the core chip in the HBM stack. For example, in the example of a 4-layer second generation high bandwidth memory (HBM2) chip stack, the I/O count is 5024, the corresponding area is about 1 x 6mm, the via density can be about 170 vias per square millimeter, with typical via diameters of about 10-40 um, and via diameters of about 76um maximum. It should be understood that these numbers are provided by way of example only and are not intended to limit the scope of the present invention.

Various opening processes may be used to make the vias 504, including laser drilling, drill drilling, and the like. Before forming the via 504, a mask may be formed to define the opening position according to a predetermined position requirement, so as to facilitate forming the via 504. It should be understood that any other suitable technique may be used to make vias 504.

Next, the graphene film 502 may be bonded to the first carrier wafer 508, facilitating subsequent processing. For example, as shown in fig. 5D, the graphene film 502 may be bonded to a first carrier wafer 508 through an adhesive material 506. For example, the adhesive material 506 is a peelable adhesive material, such as a heat sensitive or UV sensitive glue material, to facilitate subsequent peeling of the first carrier wafer 508. When the temperature of the thermosensitive gluing material is changed, the bonding strength can be greatly reduced, and when the UV sensitive gluing material is irradiated by UV light, the bonding strength can be greatly reduced. It should be understood that any other suitable method may also be used to bond graphene film 502 to first carrier wafer 508.

The first carrier wafer 508 may be made of a material such as glass or silicon. The dimensions of the first carrier wafer 508 may be consistent with the dimensions of the graphene film 502, e.g., 4 inches, 6 inches, 8 inches, 12 inches, etc. In some cases, the graphene film 502 may not be identical in size and shape to the first carrier wafer 508. To do so, the graphene film 502 may be cut to a circular size, and the graphene film 502 may be attached to the surface of the first carrier wafer 508 via the adhesive material 506.

As shown in fig. 5E, the graphene film 502 is thinned. For example, the graphene film 502 can be thinned from 55um to 50um by grinding the back side of the graphene film 502 using chemical mechanical grinding. In this manner, the surface roughness of the graphene film 502 may be on the order of nanometers, e.g., less than or equal to 1nm, e.g., below 0.5 nm. Alternatively, a graphene film 502 of appropriate thickness and surface roughness to the desired requirements may be used, thereby eliminating the thinning step.

As shown in fig. 5F, an insulating material 510 is formed on the exposed surface of the graphene film 502. For example, an insulating material is deposited on the upper surface of graphene film 502 and the sidewalls of via 504. For example, the insulating material 510 may be a low dielectric material with temperature resistance suitable for subsequent semiconductor fabrication processes, such as silicon oxide. Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicate glass, carbon-doped silicon oxide, and polymers. For example, the thickness of the insulating material 510 may be about 100 nm. It should be understood that this value is provided by way of example only and is not intended to limit the scope of the present invention.

The insulating material 510 may include multiple layers of materials, such as passivation layers, barrier layers, dielectric layers, etc., depending on the particular process recipe and requirements. For example, the insulating material 510 may be deposited by various methods, such as physical deposition or chemical deposition.

Due to the large size of the through-holes 504 of the graphene film 502, the film deposition process may be difficult to fill uniformly. In this case, after the insulating isolation is achieved on the sidewalls of the via 504 by the insulating material 510, a filling material 512 compatible with the semiconductor TSV process, such as an insulating material (e.g., silicon oxide) and/or a semiconductor material (e.g., silicon), may be formed within the via 504.

After forming the fill material 512 within the via 504, surface planarization may be accomplished by a variety of suitable polishing processes. For example, a surface roughness of less than or equal to 1nm (e.g., less than 0.5 nm) may be achieved to facilitate subsequent bonding with the underlying chip.

In some embodiments, the first carrier wafer 508 may be removed by virtue of the strippable properties of the bonding material 506, thereby forming a heat spreader comprising a layer of carbon-based material (e.g., graphene film 502) having a thermal conductivity in the horizontal direction that is greater than or equal to the thermal conductivity in the vertical direction. In addition, the heat spreader further includes a first non-metal column penetrating through the carbon-based material layer (e.g., the graphene film 502), and the first non-metal column is made of an insulating or semiconductor material, such as silicon or silicon oxide. In the example shown in fig. 5F, the first non-metallic pillar may include an insulating material 510 and a filler material 512 on both sides of the insulating material 510 as shown in fig. 5F, where the portion of the first non-metallic pillar in contact with the graphene film 502 is the insulating material 510. For example, the diameter of the first non-metallic main column may be between 10um and 40 um.

In fig. 5G, the graphene film 502 is bonded to the first semiconductor layer 514. In a wafer level packaging process, the first semiconductor layer 514 may be a wafer including a plurality of first chips or a plurality of first interconnect layers, and may be cut into a plurality of first chips or a plurality of first interconnect layers. For example, the first semiconductor layer 514 may include an active structure such as a circuit to implement a corresponding chip function, and may be cut into a plurality of first chips. For example, the bonding may be performed between the graphene film 502 and the first semiconductor layer 514 through a wafer bonding process. Various suitable wafer bonding processes may be used, in particular, a Surface Activated Bonding (SAB) bonding process. In the SAB bonding process, silicon oxide is deposited to a thickness of nm order on the surface of the first semiconductor layer 514 and silicon oxide is deposited to a thickness of nm order on the surface of the insulating material 510, and directly bonded under certain temperature and pressure conditions.

When the graphene film 502 and the first semiconductor layer 514 are bonded, preliminary alignment may be performed on the through hole 504 in the graphene film 502 and the position of the first semiconductor layer 514 where a TSV through hole needs to be made, as needed.

In fig. 5H, the first carrier wafer 508 is separated from the graphene film 502. Based on the strippable properties of the bonding material 506, the first carrier wafer 508 can be stripped from the graphene film 502. For example, in embodiments where the bonding material 506 is a heat-sensitive glue material, the bonding strength of the heat-sensitive glue material between the first carrier wafer 508 and the graphene film 502 may be significantly reduced by means of heating. Then, by applying a force, separation of the first carrier wafer 508 from the graphene film 502 is achieved. In embodiments where the bonding material 506 is a UV sensitive glue material, the bonding strength of the UV sensitive glue material between the first carrier wafer 508 and the graphene film 502 may be significantly reduced by UV illumination or the like. Then, by applying a force, separation of the first carrier wafer 508 from the graphene film 502 is achieved.

In fig. 5I, the first semiconductor layer 514 is bonded to a second carrier wafer 520. Similar to fig. 5D, first semiconductor layer 514 may be bonded to second carrier wafer 520 by adhesive material 518. For example, the adhesive material 518 is a peelable adhesive material, such as a heat sensitive or UV sensitive glue material, to facilitate subsequent peeling of the second carrier wafer 520.

In addition, an insulating material 516 is formed on the exposed surface of the graphene film 502. For example, the insulating material 516 can be formed by a deposition method, such as physical deposition or chemical deposition. Before the insulating material 516 is formed, a surface treatment such as polishing/cleaning may be performed on the surface of the graphene film 502 to improve surface flatness.

In some examples, the insulating material 516 can be a low dielectric material with temperature resistance suitable for subsequent semiconductor fabrication processes, such as silicon oxide. Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicate glass, carbon-doped silicon oxide, and polymers. For example, the thickness of the insulating material 516 may be about 100 nm. It should be understood that this value is provided by way of example only and is not intended to limit the scope of the present invention.

As shown in fig. 5J, a through-hole 522 is formed in the graphene film 502 according to a set position. Via 522 may pass through insulating material 516 and filler material 512. The opening process may be performed by Reactive Ion Etching (RIE), for example. In the RIE, oxygen plasma may be used, and hydrogen or argon plasma may be used. Using RIE requires masking the surface of graphene film 502 in advance to define the locations where vias 522 are to be formed. The trompil can be designed according to actual demand, and the aperture diameter of through-hole 522 can be for example in 2 ~ 20um within ranges.

In fig. 5K, an insulating material 524 is formed on the exposed upper surface of the structure shown in fig. 5J, specifically, insulating material 524 is formed on the surfaces of insulating material 516 and fill material 512 (i.e., the sidewalls of vias 522). Insulating material 524 may be a passivation layer, such as silicon nitride. The thickness of the insulating material 524 may be about 100 to 300 nm. For example, the insulating material 524 may be formed by a deposition process, such as a physical deposition or a chemical deposition process.

As shown in fig. 5L, a via hole 526 is formed in the first semiconductor layer 514 according to a set position. This is similar to the via last (via last) process. For example, the via 526 may be formed using a bosch process or a deep reactive ion etch process. In the Bosch process, SF can be passed₆And C₄F₈The plasma is alternately cycled to achieve the vias 526. The location of the through hole 526 corresponds to the location of the through hole 522, e.g., the center locations of the two remain the same and may be the same or very close in size. The trompil is designed according to actual demand, and the aperture diameter is usually in 2 ~ 20um within range.

As shown in fig. 5M, an insulating layer 528 is formed on the upper surface of the structure of fig. 5L. Specifically, an insulating layer 528 is formed on the surface of insulating material 524 and on the sidewalls of via 526. The insulating layer 528 may be formed by deposition, for example, a physical deposition or chemical deposition process. Insulating layer 528 may comprise silicon oxide or silicon nitride, which may be about 100nm thick.

In fig. 5N, via 526 is filled with a conductive material to form conductive pillar 530. For example, electrolytic plating may be used to form the conductive posts 530. In electrolytic plating, a barrier layer and a seed layer are first deposited sequentially on the exposed surfaces of the vias 526. The material of the barrier layer may include tantalum nitride, titanium nitride, tungsten titanium, tantalum, chromium, combinations thereof, or the like. The thickness of the barrier layer may be about 300 nm. The material of the seed layer may include copper or the like, and the thickness of the seed layer may be 200 nm. It should be understood that this value is provided by way of example only and is not intended to limit the scope of the present disclosure. Then, electroplated copper is formed within via 126 by an electrolytic plating process to fill via 526. Alternatively, the conductive pillars 530 may be formed using other suitable methods such as an electroless plating process.

After filling the via 526, the excess copper and barrier material on the top surface may be removed by chemical mechanical polishing or the like to form the structure shown in fig. 5N.

Then, as shown in fig. 5O, pads, e.g., pads 532, 534, may be formed at one or both ends of via 526, as desired. For example, the pads 532 and 534 can be formed by electroplating, such as surface gold plating, copper plating, and the like.

In one example, the bonding pad 532 can be fabricated first near one side of the graphene film 502, and the first semiconductor layer 514 can be separated from the second carrier wafer 520 after fabrication. For example, the second carrier wafer 520 may be peeled from the first semiconductor layer 514 based on the peelable property of the adhesive material 518. Then, pads 534 are formed on the bottom of the first semiconductor layer 514, followed by an array of solder balls 536, such as micro-bumped copper pillars. In another example, the first semiconductor layer 514 may be first separated from the second carrier wafer 520, and then pads 532, 534 may be formed at both ends of the via 526, respectively.

As shown in fig. 5P, the bonding of the second chip 540 to the first semiconductor layer 514 may be achieved using a wafer to wafer (wafer) process. For example, the second chip 540 may be a fourth core chip wafer in a four-layer HBM2 chip stack, and the first semiconductor layer 514 may be a bottom layer chip wafer in a four-layer HBM2 chip stack. According to actual requirements, after the multi-layer HBM chip is stacked, chip cutting can be carried out, and a 4-layer HBM2 stacked memory chip module is manufactured.

As shown in fig. 5Q, the memory chip module may be soldered on the third semiconductor layer 542 using a die-to-wafer (die-to-wafer) or a die-to-die (die-to-die) process. The third semiconductor layer 542 may be a third interconnect layer or a third chip. When the third semiconductor layer 542 is a third interconnection layer, the memory chip module can be interconnected with other logic chips and the package substrate through the third semiconductor layer 542.

According to the first embodiment, a graphene film is integrated on one side of a bottom chip, and TSVs penetrating the graphene film are used as vertical interconnections between the bottom chip and a core chip. By carrying out larger through holes and surface isolation measures on the graphene film in advance, the vertical interconnection among three-dimensional chips can be realized after the high-heat-conductivity graphene film with electric conduction of the integrated body is realized. In addition, materials compatible with the TSV process are filled in the large through hole which is manufactured in advance in the graphene film, and the TSV process difficulty in the integration of the rear-end three-dimensional chip is remarkably reduced.

A method of manufacturing according to the first embodiment of the present disclosure is described above in connection with fig. 5A-5Q. It should be understood that various possible modifications to the process can be made by those skilled in the art without departing from the scope of the disclosure herein. Several variations of the manufacturing method according to the first embodiment will be described below with reference to fig. 6A to 7D for explanation.

Fig. 6A to 6B are schematic views showing a first modification of the manufacturing method according to the first embodiment. A first modification of the first embodiment starts with the structure shown in fig. 5I. Then, unlike fig. 5J, in the first modification of the first embodiment, a via 526 is formed through the insulating material 516, the filling material 512, and the first semiconductor layer 514, as shown in fig. 6A. Then, according to the same steps as fig. 5M to 5Q, the structure shown in fig. 6B is formed. The first modification of the first embodiment is mainly different from the first embodiment in that the holes shown in fig. 5J and 5L are modified to be performed simultaneously.

Fig. 7A to 7D are schematic views showing a second modification of the manufacturing method according to the first embodiment. A second modification of the first embodiment starts with the structure shown in fig. 5E. Then, unlike fig. 5F, in the second modification of the first embodiment, only the insulating material 510 is formed without filling the via 504 with the filling material 512, as shown in fig. 7A. In fig. 7B, similar to fig. 5G, a first semiconductor layer 514 is bonded to the graphene film 502. Then, the same process flow as fig. 5H to 5I is performed. As shown in fig. 7C, an insulating material 516 is formed on the exposed surface of the graphene film 502, and the via 504 is filled with a filling material 512. Next, in fig. 7D, a via 522 is formed within the fill material 512. The subsequent steps are the same as those shown in fig. 5K to 5Q, and are not described again. The second modification of the first embodiment is mainly different from the first embodiment in that the process of filling a material in fig. 5F is performed before the process of opening the hole in fig. 5J is modified.

Fig. 8A-8H show schematic diagrams at several stages in the manufacture of a semiconductor device according to a second embodiment of the present disclosure. Fig. 8A is the same as fig. 5A, providing a graphene film 502. In fig. 8B, similar to fig. 5D, the graphene film 502 is bonded to a first carrier wafer 508 by an adhesive material 506. In fig. 8C, the graphene film 502 is thinned, similar to fig. 5E. In fig. 8D, similar to fig. 5F, an insulating material 510 is deposited on the graphene film 502. In fig. 8E, a first semiconductor layer 514 is bonded to the insulating material 510, similar to fig. 5G. In fig. 8F, the first carrier wafer 508 is stripped, similar to fig. 5H. In fig. 8G, similar to fig. 5I and 5J, first semiconductor layer 514 is bonded to second carrier wafer 520 and insulating material 516 is formed on graphene film 502. In fig. 8H, similar to fig. 5J, a via 522 is formed through the insulating material 510, the thermally conductive layer 502, and the insulating material 516. The subsequent steps are the same as fig. 5K-5Q.

The second embodiment is different from the first embodiment in the process of forming a through hole in the graphene film 502, the first embodiment forms a plurality of through holes 504 in the graphene film 502 in the process flow of fig. 5B and 5C, fills the through holes 504 in the graphene film 504 in the process flow of fig. 5F, and opens the hole in the filling material 512 of the graphene film 502 in the process flow of fig. 5J. In contrast, the second embodiment does not require pre-perforating the graphene film 502. Specifically, in the first embodiment, the opening processes shown in fig. 5B and 5C are removed, so that in fig. 5F, via filling is not needed, and only the corresponding position of the graphene film 102 is opened in fig. 5J. In contrast to the first embodiment, the second embodiment avoids the challenges of alignment of the via locations of the graphene film and the underlying chip that may be encountered in the first embodiment.

Fig. 9A-9C show schematic diagrams at several stages in the manufacture of a semiconductor device according to a third embodiment of the present disclosure. Fig. 5A to 5H in the first embodiment can be applied to the third embodiment, however, in the hole forming process shown in fig. 5B and 5C, a larger via hole can be realized. For example, the size of the via 504 may be on the millimeter level, and for the HBM2 scenario, the maximum size of the via 504 may be designed to be the entire effective I/O pin area, such as 1 × 6mm, or the size of the via 504 may be made to be 110 × 110um or more. In this case, the shape of the through-hole 504 may have various suitable shapes, for example, a circular shape, a square shape, or the like. Because the size of the through-hole 504 is increased, other suitable processes such as a die cutting process which is simpler and suitable for low-cost mass production can be adopted for the hole opening mode of the through-hole 504.

In fig. 5F, an insulating material 510 is formed on the exposed surface of the graphene film 502. The via 504 is then filled with a material compatible with the TSV process, e.g., silicon. Since the via 504 has a large size, various processes may be used to fill the via 504. For example, a slurry made from silicon powder can be filled using a coating process, and sintered and cured under certain process conditions to form a dense filler material.

Following the process flow shown in fig. 5H, the structure shown in fig. 9A may be formed, wherein the fill material 512 fills the via 504, similar to fig. 5I. Then, in fig. 9B, an insulating material 516 is formed on the graphene film 502, similarly to fig. 5J. In fig. 9C, similar to fig. 5K, a via 522 is formed in the graphene film 502. Unlike fig. 5K, in fig. 9C, two through holes 522 and 538 are formed in one through hole 504. It should be understood that more than two vias may be formed within via 504. Other process flows are substantially the same as those of the first embodiment, and are not described herein again.

The third embodiment is similar to the first embodiment, and can also significantly reduce the planar temperature difference of the bottom chip and improve the planar heat conduction capability of the bottom chip. Compared to the first embodiment, the actual area of the graphene film 502 of the third embodiment is reduced, and the planar temperature difference performance of the bottom chip may be slightly reduced, depending on the size of the through hole 504. However, since the size of the through hole 504 becomes significantly larger, the third embodiment can significantly reduce the difficulty of the through hole opening technology of the graphene film 502. In addition, the third embodiment may fill the through hole 504 by a coating process, which may significantly reduce the cost compared to the deposition process.

Fig. 10A-10I show schematic diagrams at several stages in the manufacture of a semiconductor device according to a fourth embodiment of the present disclosure. In the fourth embodiment, the process flow shown in fig. 5A to 5F is first performed. A second carrier wafer 520 is then bonded to the upper surface of graphene film 502, particularly over insulating material 510. Specifically, second carrier wafer 520 may be bonded to graphene film 502 using adhesive material 518. For example, the bonding material 508 may be different from the bonding material 506 such that the bonding material 508 is not removed at the same time as the bonding material 506 is removed. For example, the adhesive material 506 may be a heat sensitive adhesive material, and the adhesive material 518 may be a UV sensitive adhesive material. Alternatively, the adhesive material 506 may be a UV sensitive adhesive material and the adhesive material 518 may be a heat sensitive adhesive material. Alternatively, other suitable bonding processes may also be used to bond the second carrier wafer 520 to the graphene film 502.

In fig. 10B, similar to fig. 5H, the first carrier wafer 508 is removed and the graphene film 502 is inverted. In fig. 10C, similar to fig. 5J, an insulating material 516 is formed on the graphene film 502, and a via 522 is formed in the filling material 512 and the insulating material 516. In fig. 10D, similar to fig. 5K, an insulating material 524 is formed on the sidewalls of the via 522 and the surface of the insulating material 516. In fig. 10E, similar to fig. 5N, the vias 522 are filled with a conductive material to form conductive pillars 530. In fig. 5F, similar to fig. 5O, the second carrier wafer 520 is stripped, forming a soaking layer structure including vertical interconnects.

In fig. 10G, conductive pillars 550 and insulating material 548 surrounding conductive pillars 550 are formed in first semiconductor layer 514 by a TSV process. Further, pads 534, 544 are formed at both ends of the conductive post 550, respectively.

In fig. 10H, the structure shown in fig. 10F is joined with the structure shown in fig. 10G. During bonding, the conductive pillars 530 may be aligned with corresponding pads 544 of the first semiconductor layer 514, thereby forming vertical interconnects. The bonding can be realized by wafer bonding or by soldering. Prior to bonding, an insulating material 546 can be formed to achieve passivation and can serve additional support after bonding.

As shown in fig. 10H, the conductive pillars 530 and 550 may not have the same lateral dimensions, and the pads 534 are embedded in the middle as part of the entire vertical interconnect. In the case where the lateral dimension of the conductive pillars 530 is greater than the lateral dimension of the conductive pillars 550, the process for manufacturing the conductive pillars 530 is relatively simple, easy to implement, and low in cost. However, it should be understood that the lateral dimensions of the conductive posts 530 may also be equal to or less than the lateral dimensions of the conductive posts 550.

In fig. 10I, pads 552 are formed on the conductive posts 530, and the second chip 540 is bonded to the pads 552 through the solder balls 538. In addition, the bottom chip 514 is bonded to the third semiconductor layer 542 through solder balls 536.

According to the fourth embodiment, the problems of high TSV aperture ratio and increased process difficulty, complexity and cost caused by the fact that TSVs are manufactured in the graphene film and the chip wafer at the same time can be solved.

Fig. 11A-11J show schematic diagrams at various stages in the manufacture of a semiconductor device according to a fifth embodiment disclosed herein. In the fifth embodiment, the process flow shown in fig. 8A to 8G is first performed. Then, in fig. 11A, the first semiconductor layer 514 is separated from the second carrier wafer 520 by means of the peelable property of the adhesive material 518. The graphene film 502, and in particular the insulating material 516, is then bonded to a third carrier wafer 556, for example, by an adhesive material 554. The bonding material 554 may be a peelable bonding material similar to the bonding materials 506, 518.

In fig. 11B, a via 558 is formed in the first semiconductor layer 514. For example, the via 558 may be formed by an etching or laser opening process. The hole opening scheme is compatible with the TSV process, and high accuracy of through hole positioning can be guaranteed. The size of the through hole 558 may be determined according to the specific requirements of the first semiconductor layer 514, for example, about 10um in diameter. It should be understood that this value is provided by way of example only and is not intended to limit the scope of the present disclosure.

In fig. 11C, an insulating material 560 is formed on the exposed surface of the first semiconductor layer 514. For example, the insulating material 560 may be formed by a physical or chemical deposition method. The insulating material 560 may serve as a dielectric layer or passivation layer, for example, the insulating material 560 may be a low dielectric material with temperature resistance suitable for subsequent semiconductor fabrication processes, such as silicon oxide. Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicate glass, carbon-doped silicon oxide, and polymers. Alternatively, the passivation step shown in FIG. 11C may not be performed.

In fig. 11D, vias 526 are formed in the graphene film 502 and the insulating materials 510, 516. For example, via 526 may be formed by an etching or laser opening process. Alternatively, other suitable opening processes may be used. For example, by opening holes by a non-etching scheme, particularly laser opening, a higher opening efficiency can be achieved.

In fig. 11E, an insulating material 562 is formed within the via 526, specifically, the insulating material 562 is formed on the sidewalls of the via 526 and the surface of the insulating material 560. For example, the insulating material 562 may be formed by a physical or chemical deposition method. The insulating material 562 can be used as a dielectric layer or a passivation layer, for example, the insulating material 562 can be a low dielectric material with temperature resistance suitable for subsequent semiconductor fabrication processes, such as silicon oxide. Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicate glass, carbon-doped silicon oxide, and polymers. For example, the thickness of insulating material 562 may be about 100 nm. It should be understood that this value is provided by way of example only and is not intended to limit the scope of the present disclosure.

In fig. 11F, a conductive material is formed to fill the via 526 to form a conductive pillar 530. For example, electrolytic plating may be used to form the conductive material. In electrolytic plating, a barrier layer and a seed layer are first deposited sequentially on the exposed surfaces of the vias 526. The thickness of the barrier layer may be about 300 nm. The material of the seed layer may include copper or the like, and the thickness of the seed layer may be 200 nm. It should be understood that this value is provided by way of example only and is not intended to limit the scope of the present disclosure. Then, electroplated copper is formed within via 126 by an electrolytic plating process to fill via 526. Alternatively, the conductive material may be formed using other suitable methods such as an electroless plating process.

In fig. 11G, the third carrier wafer 556 is removed by virtue of the peelable property of the adhesive material 554. The seed layer, which may remain at the bottom of via 526, is then removed and pads 532 and 534 are formed by a metallization process at the ends of conductive pillar 530, respectively. In fig. 11H, solder balls 536 are formed on the pads 534. In fig. 11I, the first semiconductor layer 514 is bonded to the third semiconductor layer 542 by solder balls 536. For example, the third semiconductor layer 542 may be a third chip or a third interconnect layer.

In fig. 11J, solder balls 538 are formed on the pads 532, and the first semiconductor layer 514 is bonded to the second chip 540 through the solder balls 538. For example, the second chip 540 may be a fourth core chip wafer in a four-layer HBM2 chip stack, and the first semiconductor layer 514 may be a bottom layer chip wafer in a four-layer HBM2 chip stack.

Compared with the first embodiment, the fifth embodiment is provided with a hole on the side of the chip, is compatible with the TSV process, and simultaneously ensures high precision of through hole positioning. Then, holes are formed from the graphene side by adopting a non-etching scheme (for example, laser opening), and higher hole forming efficiency can be realized.

In the embodiments described above with reference to fig. 5A to 11J, a graphene film is taken as an example for illustration, however, the material of the heat conducting layer 502 is not limited to the graphene-based film, and a graphene-based composite film, such as a graphite/metal composite film, a graphite/metal composite film, a metal/carbon composite film, or even a copper alloy film, may also be used. Moreover, while the embodiments are described separately above, it should be appreciated that various suitable combinations of the embodiments can be made to form additional embodiments without departing from the scope of the present disclosure.

Fig. 12 illustrates a flow diagram of a method 1200 for fabricating a semiconductor device, according to some embodiments of the present disclosure. At block 1202, a thermally conductive layer is provided. For example, the thermally conductive layer may be the thermally conductive layer 102, 314 or the graphene film 502 as described above.

At block 1204, a first semiconductor layer is formed overlying the thermally conductive layer. For example, the first semiconductor layer may be the first semiconductor layer 114 or the first semiconductor layer 514.

At block 1206, a conductive pillar is formed through the first semiconductor layer, wherein the conductive pillar is electrically insulated from the thermally conductive layer. The conductive post may be conductive post 130, 134, 530, or 550.

In some embodiments, method 1200 may further include forming a first insulating layer on the first surface of the thermally conductive layer, e.g., forming insulating material 510 on the surface of graphene film 502, as shown in fig. 5F. In this embodiment, as shown in fig. 5G, a first semiconductor layer (e.g., first semiconductor layer 514) is bonded to a first insulating layer (e.g., insulating material 510) to form the first semiconductor layer under the thermally conductive layer (e.g., graphene film 502).

In some embodiments, method 1200 may further include forming a second insulating layer (e.g., insulating material 516) on a second surface of the thermally conductive layer (e.g., graphene film 502), the second surface being opposite the first surface, as shown in fig. 5J. In this embodiment, a first via (e.g., via 526) is formed through the second insulating layer (e.g., insulating material 516), the thermally conductive layer (e.g., graphene film 502), the first insulating layer (e.g., insulating material 510), and the first semiconductor layer (e.g., first semiconductor layer 514), as shown in fig. 5L. Conductive pillars (e.g., conductive pillars 530) are then formed within the first vias (e.g., vias 526), as shown in fig. 5N.

In some embodiments, forming the first insulating layer (e.g., insulating material 510) comprises: forming a second via (e.g., via 504) in the thermally conductive layer (e.g., graphene film 502), as shown in fig. 5B and 5C; and forming a first insulating layer (e.g., insulating material 510) on a first surface of the thermally conductive layer (e.g., graphene film 502) and sidewalls of the second via (e.g., via 504), as shown in fig. 5F.

In some embodiments, bonding the first semiconductor layer (e.g., first semiconductor layer 514) to the first insulating layer (e.g., insulating material 510) comprises: filling the second via (e.g., via 504) with a fill material (e.g., fill material 512), as shown in fig. 5F; and bonding a first semiconductor layer (e.g., first semiconductor layer 514) to the first insulating layer (e.g., insulating material 510) and the fill material (e.g., fill material 512), as shown in fig. 5G.

In some embodiments, forming the second insulating layer (e.g., insulating material 516) includes: forming a second insulating layer (e.g., insulating material 516) within the second via (e.g., via 504) and on the first surface of the thermally conductive layer (e.g., graphene film 502); and filling the second via (e.g., via 504) with a filler material (e.g., filler material 512), as shown in fig. 7C.

In some embodiments, forming the first via (e.g., via 526) includes: forming a third via (e.g., via 522) through the second insulating layer (e.g., insulating material 516) and the filler material (e.g., filler material 512), as shown in fig. 5J; forming a third insulating layer (e.g., insulating material 524) on sidewalls and bottoms of the second insulating layer (e.g., insulating material 516) and the third via (e.g., via 522), as shown in fig. 5K; and forming a fourth via through the third insulating layer (e.g., insulating material 524) and the first semiconductor layer (e.g., first semiconductor layer 514) at the third via (e.g., via 522), wherein the third via (e.g., via 522) and the fourth via form the first via (e.g., via 526), as shown in fig. 5L.

In some embodiments, forming the first via (e.g., via 526) includes forming the first via (e.g., via 526) through the second insulating layer (e.g., insulating material 516), the filler material (e.g., filler material 512), and the first semiconductor layer (e.g., first semiconductor layer 514), as shown in fig. 6A.

In some embodiments, forming the first via (e.g., via 526) includes: forming a fifth via (e.g., via 522) and a sixth via (e.g., via 538) through the second insulating layer (e.g., insulating material 516) and the filler material (e.g., filler material 512), as shown in fig. 9C; forming a fourth insulating layer (e.g., insulating material 524) on sidewalls and bottoms of the second insulating layer (e.g., insulating material 516) and the fifth via (e.g., via 522) and the sixth via (e.g., via 538), as shown in fig. 5K; and forming seventh and eighth vias through the fourth insulating layer (e.g., insulating material 524) and the first semiconductor layer (e.g., first semiconductor layer 514) at the fifth via (e.g., via 522) and the sixth via (e.g., via 538), respectively, wherein the fifth via (e.g., via 522) and the seventh via form a first via (e.g., via 526) and the sixth via (e.g., via 538) and the eighth via form a ninth via, as shown in fig. 5L.

In some embodiments, forming a conductor pillar (e.g., conductive pillar 530) includes: forming a fifth insulating layer (e.g., insulating layer 528) on sidewalls of the first via (e.g., via 526), as shown in fig. 5M; and filling the first via (e.g., via 526) with a conductive material (e.g., conductive pillar 530) to form a conductor pillar (e.g., conductive pillar 530). For example, the conductive material may be formed by an electrolytic plating process.

In some embodiments, a first end of a conductor pillar (e.g., conductive pillar 530) is interconnected with a contact of a first chip (e.g., second chip 540); and interconnecting the second end of the conductor pillar (e.g., conductive pillar 530) to a contact of the third semiconductor layer (e.g., third semiconductor layer 542).

In some embodiments, forming the first via (e.g., via 526) includes: forming a tenth via (e.g., via 522) through the second insulating layer (e.g., insulating material 516), the thermally conductive layer (e.g., graphene film 502), and the first insulating layer (e.g., insulating material 510), as shown in fig. 8H; forming a sixth insulating layer (e.g., insulating material 524) on sidewalls and bottoms of the second insulating layer (e.g., insulating material 516) and the tenth via (e.g., via 522), as shown in fig. 5K; and forming an eleventh via through the sixth insulating layer (e.g., insulating material 524) and the first semiconductor layer (e.g., first semiconductor layer 514) at a tenth via (e.g., via 522), wherein the tenth via (e.g., via 522) and the eleventh via form a first via (e.g., via 526), as shown in fig. 5L.

In some embodiments, the thermally conductive layer includes a first conductive post (e.g., conductive post 530 as shown in fig. 10H) and the first semiconductor layer includes a second conductive post (e.g., conductive post 550 as shown in fig. 10H), and forming the conductive post through the first semiconductor layer and the thermally conductive layer includes: aligning and interconnecting the first conductive pillars with the second conductive pillars, as shown in fig. 10H.

In some embodiments, forming the first via (e.g., via 526) includes: forming a twelfth via (e.g., via 558) in the first semiconductor layer (e.g., first semiconductor layer 514), as shown in fig. 11B; and forming a thirteenth via through the first insulating layer (e.g., insulating material 510), the thermally conductive layer (e.g., graphene film 502), and the second insulating layer (e.g., insulating material 516) at a twelfth via (e.g., via 558), wherein the twelfth via (e.g., via 558) and the thirteenth via form the first via (e.g., via 526), as shown in fig. 11D.

Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and combinations of the various claims and embodiments are within the scope of the invention.