Modular power amplifier device and architecture
阅读说明:本技术 模块化功率放大器设备和架构 (Modular power amplifier device and architecture ) 是由 孙世鹏 肯尼士·V·布尔 迈克尔·R·莱昂斯 加里·P·英格利什 强·R·陈 拉马纳默西· 于 2019-01-17 设计创作,主要内容包括:本发明公开了一种经封装的半导体芯片,该经封装的半导体芯片包括功率放大器管芯,该经封装的半导体芯片包括:半导体衬底、输入接触焊盘、输出接触焊盘、第一直流(DC)接触焊盘和第二直流接焊盘、具有耦合到输入接触焊盘的输入端的一个或多个晶体管,以及将第一DC接触焊盘电耦合到在半导体衬底上实现的第二DC接触焊盘和输入接触焊盘的输入偏置耦合路径。芯片还包括引线框架,该引线框架具有:电耦合到输入接触焊盘的一个或多个射频输入引脚、电耦合到输出接触焊盘的一个或多个射频输出引脚,以及分别电耦合到第一DC接触焊盘和第二DC接触焊盘的第一输入偏置引脚和第二输入偏置引脚。(A packaged semiconductor chip includes a power amplifier die, the packaged semiconductor chip including: the semiconductor device includes a semiconductor substrate, an input contact pad, an output contact pad, a first Direct Current (DC) contact pad and a second DC contact pad, one or more transistors having input terminals coupled to the input contact pad, and an input bias coupling path electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad implemented on the semiconductor substrate. The chip further includes a lead frame having: one or more radio frequency input pins electrically coupled to the input contact pads, one or more radio frequency output pins electrically coupled to the output contact pads, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.)
1. A packaged semiconductor chip (800), comprising:
a semiconductor substrate (810);
a radio frequency input contact pad (812) implemented on the semiconductor substrate;
a radio frequency output contact pad (813) implemented on the semiconductor substrate;
a first Direct Current (DC) contact pad (819) and a second DC contact pad (816) implemented on the semiconductor substrate; and
an input bias coupling path (873) implemented on the semiconductor substrate and electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad;
one or more transistors (815) implemented on the semiconductor substrate and having input terminals coupled to the input contact pads; and
a lead frame, the lead frame comprising:
one or more radio frequency input pins (831) electrically coupled to the input contact pads;
one or more radio frequency output pins (832) electrically coupled to the output contact pads; and
a first input bias pin (833) and a second input bias pin (837) electrically coupled to the first DC contact pad and the second DC contact pad, respectively.
2. The packaged semiconductor chip (800) of claim 1, wherein the one or more transistors (815) are configured to receive an output bias signal from at least one of the one or more radio frequency output pins (832) of the leadframe.
3. The packaged semiconductor chip (800) of claim 1, wherein the first DC contact pad (819) and the second DC contact pad (816) are disposed on opposite sides of the input contact pad (812).
4. The packaged semiconductor chip (800) of claim 1, wherein:
the one or more transistors comprise a plurality of field effect transistors; and is
The input contact pad is electrically coupled to gates of the plurality of field effect transistors.
5. The packaged semiconductor chip (800) of claim 1, wherein the input bias coupling path (873) allows the packaged semiconductor chip (800) to be daisy-chained in parallel with another packaged semiconductor chip.
6. The packaged semiconductor chip (800) of claim 1, further comprising a DC blocking circuit (871) implemented on the semiconductor substrate (810) and configured to block DC current between the input contact pad (812) and the input of the one or more transistors (815).
7. The packaged semiconductor chip (800) of claim 1, further comprising:
a first amplifier stage comprising the one or more transistors (815); and
a second amplifier stage (825) having an input coupled to an output of the first amplifier stage.
8. The packaged semiconductor chip (800) of claim 7, wherein the second amplifier stage is DC blocked from the first amplifier stage.
9. The packaged semiconductor chip (800) of claim 7, further comprising an output bias coupling path electrically coupling an output of the second amplifier stage with the output of the first amplifier stage.
10. The packaged semiconductor chip (800) of claim 7, wherein:
the second amplifier stage (825) comprises a plurality of transistors connected in parallel; and is
The input terminals of the plurality of transistors are electrically coupled.
11. The packaged semiconductor chip (800) of claim 1, wherein the leadframe is a component of a flat leadless package (830).
12. The packaged semiconductor chip (800) of claim 1, further comprising an output matching circuit (1360) disposed within the package (830,1330).
13. The packaged semiconductor chip (800) of claim 12, wherein the output matching circuit (1360) is implemented on the semiconductor substrate (810,1310).
14. A power amplifier (300,700), comprising:
a printed circuit board (340,740);
a plurality of packaged semiconductor chips (351-:
a semiconductor substrate;
a radio frequency input contact pad (812) implemented on the semiconductor substrate;
a radio frequency output contact pad (813) implemented on the semiconductor substrate;
a first Direct Current (DC) contact pad (819) and a second DC contact pad (816) implemented on the semiconductor substrate;
an input bias coupling path (873) implemented on the semiconductor substrate and electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad;
one or more transistors (815) implemented on the semiconductor substrate and having input terminals coupled to the input contact pads;
a lead frame, the lead frame comprising: one or more radio frequency input pins electrically coupled to the input contact pads, one or more radio frequency output pins electrically coupled to the output contact pads, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively; and
a surface mount package at least partially housing the semiconductor substrate and the leadframe.
15. The power amplifier (300,700) of claim 14, wherein the plurality of packaged semiconductor chips are identical.
16. The power amplifier (300,700) of claim 14, wherein the plurality of packaged semiconductor chips include:
a first group of parallel packaged semiconductor chips; and is
A second group of parallel packaged semiconductor chips;
wherein each of the first set of parallel packaged semiconductor chips is connected in series with at least one of the second set of parallel packaged semiconductor chips.
17. The power amplifier (300,700) of claim 14, further comprising a matching circuit (1361) implemented on the printed circuit board (340,740), the matching circuit configured to combine with parasitic elements of the plurality of packaged semiconductor chips to provide impedance matching for the plurality of packaged semiconductor chips for high frequency operation.
18. The power amplifier (300,700) of claim 17, wherein the high frequency operation corresponds to KaFrequency bands.
19. A method of manufacturing a power amplifier, the method comprising:
providing a plurality of packaged semiconductor chips (351-;
providing a first circuit board (340,740);
forming first electrical connections (342,343) in the first circuit board to connect to a first subset (351-364,730,731) of the plurality of packaged semiconductor chips; and is
Surface mounting the first subset of the plurality of packaged semiconductor chips on the first circuit board in a first multi-stage power amplifier configuration;
wherein the first electrical connection comprises a parallel daisy-chain connection (747) between at least two of the first subset of the plurality of packaged semiconductor chips.
20. The method of claim 19, further comprising, after the surface mounting the first subset of the plurality of packaged semiconductor chips:
providing a second circuit board (340,740);
forming second electrical connections (342,343) in the second circuit board to connect to a second subset (351-364,730,731) of the plurality of packaged semiconductor chips; and is
Surface mounting the second subset of the plurality of packaged semiconductor chips on the second circuit board in a second multi-stage power amplifier configuration having a greater number of amplifier stages than the first multi-stage power amplifier configuration;
wherein the second electrical connection comprises a parallel daisy-chain connection (747) between at least two of the second subset of the plurality of packaged semiconductor chips.
21. The method of claim 19, further comprising determining bias values for the first subset of the plurality of packaged semiconductor chips based on parasitic elements of the first subset of the plurality of packaged semiconductor chips at high operating frequencies.
22. The method of claim 19, further comprising determining a number of packaged semiconductor chips of the plurality of packaged semiconductor chips to be connected in parallel after the providing the plurality of packaged semiconductor chips.
23. The method of claim 19, further comprising determining a number of packaged semiconductor chips of the plurality of packaged semiconductor chips to be connected in series after the providing the plurality of packaged semiconductor chips.
Background
The present disclosure relates to radio frequency power amplifier devices and architectures, and more particularly to high power amplifiers. Some power amplifiers, including high power amplifiers, may be implemented, at least in part, using a solid-state (e.g., semiconductor) substrate. Different semiconductor substrates provide different performance characteristics.
Disclosure of Invention
Systems, devices, and methods for implementing modular power amplifier architectures, including high power amplifier architectures, are described herein. In some implementations, the present disclosure relates to a packaged semiconductor chip comprising: a semiconductor substrate; a radio frequency input contact pad implemented on a semiconductor substrate; a radio frequency output contact pad implemented on a semiconductor substrate; a first Direct Current (DC) contact pad and a second DC contact pad implemented on a semiconductor substrate; an input bias coupling path implemented on the semiconductor substrate and electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad; and one or more transistors implemented on the semiconductor substrate and having input terminals coupled to the input contact pads. The semiconductor substrate, the input contact pad, the output contact pad, the first DC contact pad and the second DC contact pad, the input bias coupling path, and the one or more transistors may be part of an internal amplifier/semiconductor die of a packaged semiconductor chip. The packaged semiconductor chip further includes a lead frame, the lead frame including: one or more radio frequency input pins electrically coupled to the input contact pads, one or more radio frequency output pins electrically coupled to the output contact pads, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.
The one or more transistors may be configured to receive an output bias signal from at least one of the one or more radio frequency output pins of the lead frame. In some embodiments, the first DC contact pad and the second DC contact pad are disposed on opposite sides of the input contact pad. In some embodiments, the one or more transistors include a plurality of field effect transistors, and the input contact pad is electrically coupled to gates of the plurality of field effect transistors. The input bias coupling path may allow the packaged semiconductor chip to be daisy chained in parallel with another packaged semiconductor chip. The packaged semiconductor chip may further include a DC blocking circuit implemented on the semiconductor substrate and configured to block DC current between the input contact pad and the input of the one or more transistors.
In some embodiments, the packaged semiconductor chip further comprises: a first amplifier stage comprising one or more transistors and a second amplifier stage having an input coupled to an output of the first amplifier stage. For example, the second amplifier stage is DC blocked from the first amplifier stage. In some implementations, the packaged semiconductor chip further includes an output bias coupling path that electrically couples the output of the second amplifier stage with the output of the first amplifier stage. In some embodiments, the second amplifier stage comprises a plurality of transistors connected in parallel, and the input terminals of the plurality of transistors are electrically coupled.
The lead frame may be a component of a flat leadless package. The packaged semiconductor chip may include an output matching circuit disposed within the package. For example, the output matching circuit may be implemented on a semiconductor substrate.
In some implementations, the present disclosure relates to a power amplifier including a printed circuit board and a plurality of packaged semiconductor chips mounted on the printed circuit board in a power amplifier configuration. Each of the plurality of packaged semiconductor chips includes: a semiconductor substrate; a radio frequency input contact pad implemented on a semiconductor substrate; a radio frequency output contact pad implemented on a semiconductor substrate; a first Direct Current (DC) contact pad and a second DC contact pad implemented on a semiconductor substrate; an input bias coupling path implemented on the semiconductor substrate and electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad; one or more transistors implemented on the semiconductor substrate and having input terminals coupled to the input contact pads; a lead frame including one or more radio frequency input pins electrically coupled to the input contact pads, one or more radio frequency output pins electrically coupled to the output contact pads, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively; and a surface mount package at least partially housing the semiconductor substrate and the lead frame.
In some embodiments, the plurality of packaged semiconductor chips are identical. The plurality of packaged semiconductor chips may include a first set of parallel packaged semiconductor chips and a second set of parallel packaged semiconductor chips, wherein each of the first set of parallel packaged semiconductor chips is connected in series with at least one of the second set of parallel packaged semiconductor chips. In some embodiments, the power amplifier further comprises a matching circuit implemented on the printed circuit board, the matching circuit configured to combine with parasitic elements of the plurality of packaged semiconductor chips to provide impedance matching for the plurality of packaged semiconductor chips for high frequency operation. For example, high frequency operation may correspond to the Ka band.
In some implementations, the present disclosure relates to a method of manufacturing a power amplifier. The method includes providing a plurality of packaged semiconductor chips each including a respective internal bias coupling path electrically coupling a first Direct Current (DC) contact pad, a second DC contact pad, and an input terminal of the respective packaged semiconductor chip. The method further comprises the following steps: providing a first circuit board; forming first electrical connections in a first circuit board to connect to a first subset of the plurality of packaged semiconductor chips; and surface mounting a first subset of the plurality of packaged semiconductor chips on a first circuit board in a first multi-stage power amplifier configuration. The first electrical connection includes a parallel daisy-chain connection between at least two of the first subset of the plurality of packaged semiconductor chips.
The method may further include, after said surface mounting a first subset of the plurality of packaged semiconductor chips: providing a second circuit board; forming second electrical connections in a second circuit board to connect to a second subset of the plurality of packaged semiconductor chips; and surface mounting a second subset of the plurality of packaged semiconductor chips on a second circuit board in a second multi-stage power amplifier configuration having a greater number of amplifier stages than the first multi-stage power amplifier configuration; wherein the second electrical connection comprises a parallel daisy-chain connection between at least two of the second subset of the plurality of packaged semiconductor chips.
The method may also include determining a bias value for a first subset of the plurality of packaged semiconductor chips based on parasitic elements of the first subset of the plurality of packaged semiconductor chips at the high operating frequency. In some embodiments, the method further comprises determining a number of packaged semiconductor chips of the plurality of packaged semiconductor chips to be connected in parallel after said providing the plurality of packaged semiconductor chips. In some embodiments, the method further comprises determining a number of packaged semiconductor chips of the plurality of packaged semiconductor chips to be connected in series after said providing the plurality of packaged semiconductor chips.
For the purposes of summarizing the disclosure, certain aspects, advantages, and novel features have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, the disclosed embodiments may be implemented in the following manner: one advantage or group of advantages as taught herein is achieved or optimized without necessarily achieving other advantages as may be taught or suggested herein.
Drawings
For the purpose of illustration, various embodiments are depicted in the drawings and should not be construed as limiting the scope of the disclosure in any way. In addition, various features of different embodiments disclosed may be combined to form additional embodiments that are part of this disclosure.
Fig. 1 is a plan view of an active power amplifier device in accordance with one or more embodiments.
Fig. 2 illustrates a packaged semiconductor chip for use in a modular high power amplifier architecture in accordance with one or more embodiments.
Fig. 3 illustrates an exemplary power amplifier architecture utilizing discrete packaged semiconductor chips in accordance with one or more embodiments of the present disclosure.
Fig. 4A-4C illustrate packaged semiconductor chips mounted and arranged in different amplifier architectures having different power levels, according to some embodiments.
Fig. 5A-5C illustrate packaged semiconductor chips mounted and arranged in different amplifier architectures having different gain characteristics, according to some embodiments.
Fig. 6A and 6B illustrate top and side views, respectively, of an interface between a semiconductor die and a leadframe associated with a chip package, according to one or more embodiments.
Fig. 7 illustrates a power amplifier architecture in accordance with one or more embodiments.
Fig. 8 illustrates a plan layout of a packaged semiconductor chip for a modular high power amplifier according to one or more embodiments.
Fig. 9 illustrates an architecture of a modular orthogonal switching apparatus in accordance with one or more embodiments.
Fig. 10 illustrates a modular amplifier architecture in accordance with one or more embodiments.
Fig. 11 illustrates a packaged semiconductor chip including individual amplifier and matching dies within a single package in accordance with one or more embodiments.
Fig. 12A and 12B show top and side views, respectively, of an interface between semiconductor dies according to one or more embodiments.
Fig. 13 illustrates a packaged semiconductor chip having both on-chip and off-chip matching in accordance with one or more embodiments.
Fig. 14 illustrates on-board matching between packaged amplifier chips in a modular high power amplifier architecture according to an embodiment.
Fig. 15 illustrates a single stage power amplifier die in accordance with one or more embodiments.
Fig. 16 illustrates a single stage power amplifier die in accordance with one or more embodiments.
Fig. 17 illustrates an amplifier architecture in accordance with one or more embodiments.
Fig. 18 illustrates a two-stage amplifier die packaged in a single leadless package in accordance with one or more embodiments.
Fig. 19-21 illustrate exemplary amplifier architectures that may incorporate modular packaged semiconductor chips according to some embodiments.
Detailed Description
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.
In certain implementations, the present disclosure relates to systems, devices, and methods for implementing modular power amplifier architectures, including high power amplifier architectures. Power amplifier modularity according to the present disclosure may involve combining relatively smaller gallium nitride (GaN) dies in quad flat no-lead (QFN) packages on relatively cheaper substrates, such as Printed Circuit Boards (PCBs), as an alternative to implementing the power amplifier architecture entirely on a single relatively larger GaN die.
The demand for high power amplifiers configured to operate at microwave frequencies has led to the development of transistor amplifiers implemented on semiconductor substrates that can operate at radio frequencies (e.g., microwave frequencies, including K)aBand) to provide a relatively high power signal. In the context of the present disclosure, the term "high power" is used to refer to power levels greater than about 10W (or 40dBm) output power. The term "high frequency" as used herein refers to frequencies greater than about 10 gigahertz (GHz). Such devices may include substrates composed of gallium arsenide (GaAs) or the relatively more expensive semiconductor, gallium nitride (GaN).
GaAs and GaN are group III-V compound semiconductors. GaAs and GaN are suitable for radio frequency (e.g., microwave) applications due to their relatively high electron mobility characteristics compared to silicon. Embodiments of the power amplifiers and other circuits disclosed herein may include any suitable or desired type of transistor device, including but not limited to Bipolar Junction Transistors (BJTs), Field Effect Transistors (FETs), and other types of transistors and solid state devices. For example, a FET according to embodiments of the present disclosure may include an enhancement mode Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a metal semiconductor FET (mesffet), or any other type of FET. Additional types of transistors that may be implemented in accordance with aspects of the present disclosure include Heterojunction Bipolar Transistors (HBTs), High Electron Mobility Transistors (HEMTs), lateral diffusion mos (ldmos), and other suitable or desired transistors.
GaAs power amplifiers are generally not suitable for high power applications. For example, the upper limit of GaAs devices can generally be considered as up to about 5W, since these GaAs cannot withstand the high voltage, current and heat levels of certain other semiconductor technologies such as GaN. Of course, higher power operation can be achieved by combining a sufficient number of GaAs devices in a push-pull or parallel or combination. However, other technologies such as GaN may be preferred where simpler and/or smaller designs are desired.
Newer developments in power amplifier technology have led to increased use of GaN dies as high power, high frequency (e.g., microwave) amplifier substrates. For example, GaN power amplifiers are suitable for certain microwave and millimeter wave electronics, including satellite communications, radar, and other high frequency applications. In general, the relatively high power density and/or ability to dissipate heat from a relatively small package of certain GaN devices, relative to GaAs and certain other technologies, may make it a suitable or desirable choice for high power applications. For example, while GaAs has a base power density of less than 1.5W/mm, GaN has a power density in the range of about 3W/mm-7W/mm. Furthermore, as noted above, GaN has a relatively high electron mobility, allowing it to amplify signals well into the higher gigahertz range (e.g., up to 200GHz or higher), and can generally operate in such a range at relatively high breakdown voltage levels (e.g., up to 80V or higher). Each GaN amplifier can achieve power levels of tens of watts. Furthermore, in some parallel, push-pull and/or Doherty configurations, power levels of hundreds to thousands of watts are possible. For all of the reasons mentioned above, GaN amplifiers may be preferred over Traveling Wave Tube (TWT) amplifiers in certain satellite applications, particularly in relatively low power satellite applications.
Certain embodiments disclosed herein relate to high power amplifier architectures configured to operate in the Ka band corresponding to a portion of the microwave range of the electromagnetic spectrum, between 26.5-40 gigahertz (GHz), corresponding to wavelengths in the range of as low as about 7.5 millimeters to slightly above one centimeter. The Ka band (e.g., 30/20GHz band) is a suitable frequency band for satellite uplink and/or other satellite applications. In satellite communications, the Ka band allows higher bandwidth communications. However, the Ka band is more susceptible to rain attenuation than some of the lower bands.
Due to the various characteristics of gallium nitride (GaN) described above, a GaN die may be used to implement a single die power amplifier architecture for high power applications. Fig. 1 is a plan view of an active
Fig. 1 shows a
Relative to
One aspect that can be seen as a drawback is its relatively high material and processing costs compared to certain other semiconductor technologies, such as bulk CMOS or GaAs. Furthermore, single chip GaN high power amplifiers, similar to the one shown in fig. 1, may have difficulties with thermal issues. For example, GaN high power amplifiers may generate a large amount of heat; when the entire power amplifier architecture is formed on a single GaN die, a large amount of heat may need to be removed from the relatively small space/structure. Furthermore, while it may be advantageous to implement the
In some implementations, embodiments of the present disclosure provide an alternative to the relatively more expensive and difficult to cool single die amplifier solution shown in fig. 1 by implementing a high power GaN (or other substrate) amplifier in a modular power amplifier architecture that is made up of relatively small portions of a surface mount device or package containing a relatively small GaN (or other substrate) die. Such smaller discrete packages may be combined and mounted on relatively cheaper media (such asPCB or silicon) such that the packaged semiconductor chip serves as a building block for a larger power amplifier system/architecture. Such embodiments may allow for the formation of high power amplifier systems configured to achieve desired and substantially reduced cost gain and power levels. With this approach, in some embodiments, a reduction of 50% or more of the GaN (or other substrate) chip area may be achieved without sacrificing output power levels. The modular high power amplifier architecture according to the present disclosure may take advantage of GaN's advantages with respect to high power capability, but avoids the costs typically associated with larger GaN chips/dies. For convenience and simplicity, the following disclosure describes certain semiconductor substrate elements as GaN substrates. However, any reference herein to GaN should be understood as applicable to any other type of semiconductor substrate having relatively higher power density, electron mobility, and/or heat dissipation characteristics than GaAs, including, but not limited to, indium phosphide (InP), indium gallium arsenide (In)xGayAs), silicon carbide (SiC), industrial grade diamond, glass, graphene, etc., and semiconductor substrates whether known or developed in the future.
Decomposing the single chip high power amplifier solution of fig. 1 into a modular high power amplifier system using several smaller packaged semiconductor chips may also provide thermal advantages. For example, in a single chip implementation of a GaN high power amplifier, in some solutions, a significant amount of heat can be generated within the chip. Further, heat transfer may generally occur only on the backside of the die. By using a relatively small and discretely packaged semiconductor chip, the total heat generated can be spread over a wide area. Furthermore, when certain surface mount packages (e.g., QFNs) are used to further aid in heat removal, a heat transfer mechanism may be applied on both the top and bottom of the package. The benefits of these heats may translate into higher performance and/or longer expected product life.
In addition to the cost and thermal based benefits described above, additional benefits may be achieved using a modular power amplifier architecture as disclosed herein. For example, in a laboratory test environment, rework of the amplifier device may be done on surface mount packaged semiconductor chips in a high power amplifier system, such as by replacing defective chips or components. In addition, redesign may simply involve redesigning the board that combines the packaged semiconductor chips, which may typically involve shorter redesign cycles and/or lower manufacturing costs than redesign of a single large GaN chip.
Packaged semiconductor chips used as building blocks in modular power amplifier systems according to embodiments of the present disclosure may include surface mount packages, such as leadless packages, which may contain a single relatively small GaN die. One example of a package type that may be used in conjunction with embodiments of the present disclosure is a quad flat no lead package (QFN), as described above, which is a surface mount package that connects a circuit die to a Printed Circuit Board (PCB)) or other substrate without the need for vias. QFN packages are typically plastic encapsulated and include a substantially planar, electrically conductive (e.g., copper) leadframe. In some embodiments, perimeter pins on the bottom of the package provide electrical connections to the PCB. In some embodiments, the QFN package includes exposed thermal pads or paddles on its underside to facilitate heat transfer away from the chip and into the PCB. Heat transfer may be further facilitated by metal vias in the thermal pad/paddle. Packaged semiconductor chips according to embodiments of the present disclosure may include back-patterned dies with signal vias, flip-chip dies, flip-chips implemented in QFNs, wire-bonded dies in QFNs, wafer-level fan-out packages, and/or other packages. Although certain embodiments are disclosed herein in the context of QFN packages, it should be understood that the principles disclosed herein are applicable to any other type of package.
As described above, the costs associated with high cost substrate processes (e.g., GaN) can be increased by utilizing a significant portion of the area of such dies for passive circuits (e.g., matching circuits) that does not adequately benefit from the characteristics of the high cost substrate. For example, certain implementations of GaN high power amplifiers utilize a large portion of the die area for passive circuits for impedance matching, power splitting, and/or combining. Embodiments disclosed herein provide more cost-effective power amplifiers and other devices by utilizing a relatively high percentage of high-cost die area for active devices such as amplifier transistors (e.g., FETs). By breaking an otherwise larger amplifier chip down into modular smaller chips and implementing at least a portion of the associated power splitting, combining, and/or impedance matching circuits on a relatively cheaper medium, the costs associated with power amplifier production may be significantly reduced.
Fig. 2 illustrates a packaged semiconductor chip 200 for use in a modular high power amplifier architecture including a semiconductor substrate (e.g., gallium nitride (GaN)) (semiconductor substrate 210) according to one or more embodiments of the present disclosure. For illustrative purposes, the packaged chip 200 is described below as a QFN chip. As described above, the surface mount package may include a lead frame secured to the overmolded housing 230. In some embodiments, the lead frame is about 8 to 10mm thick and includes copper or other metal. The lead frame may be etched or stamped to form a plurality of pins and/or ground reference pads/layers. While fig. 2 shows a wire bonded QFN package as an example, it should be understood that the principles disclosed herein are applicable to other types of relatively small surface mount devices and packages.
In some embodiments, chip 200 includes one or more input pins 231 that are wire bonded to input pads 212 of semiconductor substrate 210. The packaged chip 200 of the illustrated embodiment of fig. 2 includes a single amplifier stage. Although a single amplifier stage is shown implemented on the semiconductor substrate 210, it should be understood that the packaged chip 200 may include two amplifier stages in some embodiments.
The semiconductor substrate 210 may advantageously be used primarily for active amplifier devices such as FETs, BJTs or other active devices. In addition, the semiconductor substrate 210 may have some passive circuitry implanted thereon that is designed to provide an effective interface for the semiconductor substrate 210. For example, the semiconductor substrate 210 may include some passive circuitry configured to provide partial matching on the semiconductor substrate 210. In some embodiments, the semiconductor substrate 210 includes partial impedance matching to provide an impedance that is achievable to enable the bond wires and the package to withstand parasitic elements of the package. That is, parasitic elements associated with the packaging of chip 200 may be incorporated into the impedance matching design of chip 200. In some embodiments, the semiconductor substrate 210 includes a plurality of Direct Current (DC) contact pads 216 to 219 that can be used to inject input and/or output bias signals.
Semiconductor substrate 210 may be relatively small compared to certain other implementations of GaN high power amplifiers, as described above. It may be desirable to account for the loss of the substrate when cutting GaN chips from a GaN wafer according to the chip manufacturing process relative to a relatively smaller die, such as the die shown in fig. 2. For example, when manufacturing the semiconductor substrate 210, approximately 100 μm may be lost by cutting around the periphery of the semiconductor substrate 210 as part of the sawing/die sawing process. Thus, the smaller the area of the semiconductor substrate 210, the greater the percentage of area wasted due to sawing/dicing associated therewith. Accordingly, to enable more efficient use of semiconductor substrate (e.g., GaN) regions, it may be desirable to include a two-stage or other multi-stage amplifier design on the semiconductor substrate 210.
With only a single semiconductor substrate 210 housed within package 230, packaged chip 200 may present a relatively robust interface by eliminating any chip-to-chip interfaces. By not requiring a GaN substrate for some passive circuitry, chip 200 may advantageously save up to 30% or more of GaN area relative to the high power amplifier design of fig. 1. By using a leadless surface mount package, it is possible to use surface mount technology reflow components, which may be relatively less expensive to implement, rather than chip and wire bond components.
A separately packaged semiconductor chip similar to that shown in fig. 2 and described above may be used as a building block in a larger modular power amplifier architecture. The modular power amplifier architecture may be constructed by combining a plurality of discrete amplifier chips in a desired arrangement/configuration on a printed circuit board. That is, a plurality of identical or substantially identical packaged semiconductor chips may be used as building blocks for constructing a power amplifier, wherein each individual chip comprises a discrete amplifier unit of a larger power amplifier architecture. The term "identical" as used herein with respect to a packaged semiconductor chip and/or a component thereof is intended to account for manufacturing tolerances and variations between different devices, components and/or systems that are manufactured according to a common plan, configuration, architecture, design and/or form. Thus, "identical" chips/components described herein may have certain differences attributable to manufacturing tolerances or expected variances. Fig. 3 illustrates an exemplary
By implementing a modular power amplifier similar to that shown in fig. 3, certain cost, flexibility, and/or performance benefits may be realized. For example, in some implementations, the power amplifier architecture may be implemented with passive circuitry implemented at least partially on relatively lower cost materials (such as on PCB 340), while the active amplification devices (such as transistors) may be implemented on relatively higher cost materials (such as GaN dies within a single amplifier chip (e.g., 351-364)). By implementing the active amplifier transistors in a modular amplifier chip, higher yields of such chips comprising relatively higher cost materials may be enabled. Furthermore, by using the amplifier chip building blocks to build larger power amplifier architectures, greater flexibility in power amplifier design is possible, where changes to the power amplifier architecture can be achieved by changing the PCB layout, such that additional semiconductor manufacturing cycles are not required.
In some embodiments, the individually packaged semiconductor chips 351-364 may comprise QFN packages, as described in detail herein. The packaged
The
The solution shown in fig. 3 may provide a relatively flexible power amplifier design. For example, whereas a manufacturing cycle for manufacturing or producing a multi-stage single chip power amplifier chip may be relatively long (e.g., up to six months or more) where the power amplifier is constructed from modular packaged chips as shown in fig. 3, implementing modifications to the power amplifier architecture relative to the number of stages and/or the number of parallel amplifier cells may only require PCB modifications. In general, PCB modification may be able to be achieved in a shorter time frame than the wafer fabrication cycle.
The
In some embodiments, the individually packaged semiconductor chips of
As detailed herein, a modularly packaged semiconductor chip may be used as a building block for constructing a high power amplifier. Such chips may be cascaded in parallel in order to determine the amount of power handling capability of the chip. That is, amplifiers with different power levels may be constructed using modular packaged amplifier chips that are mounted and arranged according to different board designs coupling different numbers of chips in parallel. Generally, circuit board design cycles may be less expensive and/or time consuming than semiconductor wafer/chip design cycles. When designing and/or manufacturing modular power amplifier architectures with individually packaged semiconductor chips according to embodiments of the present invention, the packaged semiconductor chips may be cascaded in parallel, providing scalability in power levels. Packaged semiconductor chips may also be cascaded in series, providing scalability in gain levels.
Fig. 4A-4C illustrate packaged semiconductor chips (e.g., 401) mounted and arranged in different amplifier architectures having different power levels. For example, power amplifier 400A of fig. 4A may be capable of operating at a relatively lower power than
In addition to parallel cascading capability, in some implementations, packaged semiconductor chips may be cascaded in series to produce a power amplifier having a desired gain level. Fig. 5A-5C illustrate packaged semiconductor chips (e.g., 501) mounted and arranged in different amplifier architectures having different gain characteristics. For example,
Fig. 6A and 6B show top and side views, respectively, of an
Fig. 6A and 6B show a semiconductor chip package mounted on a printed
In general, using leadless surface mount packages (e.g., QFNs) at high frequencies (e.g., Ka band) can present challenges. Thus, certain embodiments of packaged semiconductor chips may incorporate a certain amount of matching circuitry on the inner semiconductor die (e.g., GaN) and a certain amount of matching circuitry implemented on the printed circuit board on which the package is mounted, which may be relatively less expensive. In some embodiments, the semiconductor chip interface may include a plurality of
As described herein, implementing a modular high power amplifier architecture using discrete packaged semiconductor chips may present certain challenges. For example, it may be necessary or desirable to configure input (e.g., gate) and/or output (e.g., drain) bias injections in a suitable or desired manner that allows for series cascading of individually packaged semiconductor chips to provide a desired gain and/or parallel cascading to provide a desired power level. The lead frame and amplifier die of the packaged semiconductor chip may be configured to daisy chain connect the input/gate bias connections so that the packaged semiconductor chip may be relatively easily arranged in a typical power splitting/combining network.
In some embodiments, the amplifier architecture of the present disclosure is configured such that the input/gate bias voltage is applied via a bias injection network configured to be interconnected to parallel chips, as shown in the
In the
The
The
To implement the modular architecture of fig. 7, as described above, certain internal bias connections may be needed or desired on the internal die of the respective packaged chip. By including an internal bias connection as described below, additional external connections may not be required, allowing for simplified power amplifier design/construction. In embodiments where the packaged semiconductor chip includes a multi-stage power amplifier die, the output/drain bias terminals of the amplifier stages can be linked together across the semiconductor chip within the packaged semiconductor chip. In doing so, it may not be necessary to provide drain bias connections to the various stages, which may be relatively expensive in terms of semiconductor die area and/or assembly complexity.
As described above, improved thermal isolation may be achieved in
Fig. 8 shows a plan layout of a packaged semiconductor chip 800 for a modular high power amplifier according to one or more embodiments of the present disclosure. The packaged semiconductor chip 800 of fig. 8 includes a lead frame that includes a plurality of pins that may be used to receive an RF input signal as well as certain DC bias signals. For example, a first pad 833 of the leadframe may be used to receive an input (e.g., gate) bias signal from a circuit board connection on one side 801 of the package 830, where the bias signal may be coupled to a DC pad 819 formed on the substrate 810 using one or more bond wires 838 or other types of electrical connections. The input bias may be further routed from the DC pad 819 to the input terminal 811 of the parallel configured transistor 815 and further routed to the DC pad 816 on the opposite side 802 of the parallel configured transistor 815. DC pad 816 may be coupled to another lead 837 of the leadframe by one or more bond wires 839. Pins 833 and 837 may advantageously be pins disposed on opposite sides 801, 802 of the parallel configured transistor 815 and/or package 830 such that a routing path 873 between pins 833, 837 on substrate 810 allows an input bias signal to be received from a circuit board to which packaged semiconductor device 800 is mounted at pin 833 and further output at pin 837 on opposite side 802 of chip package 830. As described above, the coupling path 873 coupling the input/gate bias input 833 and output 837 pins may allow for parallel daisy-chained connections of the packaged semiconductor chip 800, as described in detail herein. For example, when two packaged semiconductor chips according to embodiments of the present invention are placed side-by-side in a parallel configuration, a simple non-board connection between an input/gate voltage pin connection on one side of one of the packages and an input/gate voltage pin connection on the opposite side of the other package may allow for input (or output) offset daisy-chained connections such that multiple layers of circuit board wiring are not required to cascade the chips in parallel and/or in series.
Packaged semiconductor chip 800 may advantageously include a DC blocking circuit 871 between RF input pad 812 and input terminal 811 of transistor 815 in a parallel configuration. The DC blocking circuit 871 can include one or more capacitors and/or other passive circuit elements. In accordance with embodiments of the present disclosure, the DC blocking circuit 871 may be used to block any DC output bias signal that may be present at the input pad 812 of the substrate 810 from the output bias signal associated with the previous stage of the modular power amplifier architecture. Thus, in some embodiments, the RF input to the substrate 810 may be DC blocked while the RF output is not DC blocked, so that the output/drain bias voltage may be injected into the RF splitter/combiner network implemented on the circuit board without the need for additional off-chip DC blocking circuitry. In some embodiments, the output may be DC blocked while the input is not DC blocked.
In some implementations, a multi-stage amplifier can be implemented on the substrate 810. The addition of additional amplifier stages may provide more efficient use of the semiconductor substrate 810 (e.g., GaN die) than embodiments having only a single stage amplifier due to substrate loss during wafer dicing. The packaged semiconductor chip 800 may also include an output bias coupling 875 between amplifier stages of the substrate 810. For example, the output bias signal may be received at one or more of the output pins 832 of the leadframe. Output pins 832 may be coupled to output pads 813 of substrate 810 using one or more bond wires 836, as shown. An output (e.g., drain) bias signal received at the output pad 813 via the bond wire 836 and the output pin 832 may be from the output wiring 875 of the second stage 825 of the amplifier to the output 821 of the first stage 815 of the amplifier on the substrate 810. Thus, in some embodiments, the output/drain biases of all stages of an amplifier implemented on the substrate 810 are connected or linked together on the substrate 810. In some implementations, substrate 810 includes a certain amount (e.g., a minimal amount) of matching circuitry 880 for providing output matching for chip 800. With a minimum amount of on-chip matching circuitry 880, additional needed or desired matching circuitry can be implemented in or using the package interface parasitic element, as described above. In some implementations, the semiconductor substrate 810 includes one or both of a reflective stabilization circuit and a ring stabilization circuit implemented thereon.
Since amplifier (e.g., GaN) substrate 810 is relatively small compared to a multi-stage high power amplifier implemented on a single semiconductor die, where the power amplifier architecture may be constructed using many of the same chips similar to chip 800, the design effort associated with the high power amplifier may advantageously focus on optimizing the size and/or performance of a single relatively small chip (e.g., chip 800), where the benefits achieved by such optimization may be amplified by the number of packaged semiconductor chips used in the high power amplifier architecture. For example, if a high power amplifier architecture includes 10 individually packaged semiconductor chips, where the packaged semiconductor chip design achieves a certain cost savings, such savings may translate into 10 times savings relative to the overall high power amplifier system. Furthermore, because the size of chip 800 is relatively small, the yield of amplifier substrate 810 may be significantly higher than that of an amplifier substrate of a high power amplifier architecture implemented with more active devices on a single relatively large die/substrate (e.g., GaN).
Although certain interface techniques are described herein, it should be understood that any interface technique may be used to bond a semiconductor (e.g., GaN) amplifier die according to the present disclosure to a circuit board, substrate, and/or packaging material. Such alternative interface techniques include, but are not limited to, flip chip techniques and die backside patterning with signal vias. For example, flip chip technology may be used to bond the amplifier die 810 to a leadless package or directly to a printed circuit board. In such cases, it may be relatively more difficult to direct heat away from the amplifier die 810. Furthermore, in some implementations, assembly may be relatively more complex and oscillation may occur due to insufficient grounding. Furthermore, such interface techniques may limit the thickness of the die/wafer. In some embodiments, flip chip technology may be used on the back side of die 810 by using standard bumping techniques and signal vias. Although a printed circuit board is described herein, it should be understood that materials other than standard printed circuit boards may be used to combine packaged semiconductor chips together in a power amplifier architecture, as described herein.
In some embodiments, the high power amplifier system may utilize a quadrature switching architecture to provide the switching function without having switching circuitry at the output and/or input of the system. Such a switching function may be achieved by turning on or off appropriate portions of the amplifier system, which may reduce output losses and/or increase output power and power added efficiency. Furthermore, by avoiding the use of switching circuit components, additional savings can be realized in component cost, simplicity, and/or yield.
Fig. 9 shows an architecture of a modular quadrature switching device 900 comprising a plurality of packaged semiconductor amplifier chips and a plurality of 90 ° hybrid devices. The switching device as shown in fig. 9 achieves a selective output on one of the two output terminals 952, 953 with an appropriate phase. For example, the quadrature switching architecture 900 may be used as an electronic polarity switching device that may be configured to switch from right-hand circular polarization to left-hand circular polarization depending on the state of the set of amplifiers 987 and 988. For example, when the amplifier 987 is in an on configuration and the amplifier 988 is in an off configuration, an RF output signal may be provided at the RF output port 953, and when the amplifier 987 is in an off configuration and the amplifier 988 is in an on configuration, an RF output signal may be provided at the RF output port 952. To accomplish this, a 90 ° hybrid device (e.g., 983) may be configured to sum the signal power at the respective RF output ports. An orthogonal switching architecture similar to that of fig. 9 may be particularly desirable or applicable for relatively higher power applications in order to reduce losses. Furthermore, implementing orthogonal switching architectures in a modular configuration as shown in fig. 9 may provide improved isolation between output paths compared to single chip switching devices. In some implementations, the DC bias signal can be fed into the circuit 900 through an isolated port of the 90 ° hybrid.
In the architecture 900, the packaged semiconductor amplifier chip 930 may advantageously be connected in parallel with respect to input/gate bias connections and signals and/or output/drain bias connections and signals using on-board traces configured to inject bias signals into the output path of the packaged semiconductor chip 930. In an amplifier stage, such as amplifier stage 925, an output/drain bias signal may be injected at terminal 975. With respect to the amplifier stages 987, 988, an output/drain bias may be injected at the isolated port 991 of the respective 90 ° hybrid device 982. In embodiments where the individually packaged semiconductor chip 930 includes multiple amplifier stages, the coupling between the outputs of the stages may be implemented on a semiconductor die within the chip package, as described above with respect to fig. 8.
With respect to input/gate biasing, the individually packaged semiconductor chips 930 may have internal pin-to-pin input/gate biasing coupling paths, as described in detail above with respect to fig. 8. For example, contact pins on opposite sides of a leadframe of a packaged semiconductor chip may be coupled through inputs of an amplifier to allow for daisy-chained connections, as described in detail above. In some implementations, the modular orthogonal switching architecture 900 of fig. 9 can be implemented with a radio frequency isolation wall or structure between the upper and lower halves of the switching device.
Referring back to fig. 2, a modular packaged semiconductor chip according to the present invention may advantageously include or be connected to input and/or output matching circuitry to provide desired input and/or output matching for efficient power amplifier operation. In some implementations, the semiconductor die interface impedance may be non-standard (i.e., an impedance other than 50 ohms), which may allow only a portion of the RF matching circuit to be implemented on the semiconductor die. For example, in some embodiments, a semiconductor die (e.g., a GaN die) of a modular packaged semiconductor chip according to embodiments of the present invention does not have on-die matching circuitry for input and/or output impedance matching, and thus may present an impedance at the input of the chip that is higher or lower than 50 ohms and/or an impedance at the output of the chip that is higher or lower than 50 ohms is desired.
Fig. 10 illustrates a modular power amplifier architecture in which the input 1012 and output 1011 impedance interfaces of various amplifier stages are identified, according to an embodiment of the disclosure. In some embodiments, the desired input impedance matching may be achieved at least in part in a separately packaged semiconductor chip by package parasitics at high frequency operation. Each of the packaged semiconductor chips may be designed to have a standardized power matching impedance, which may be different from a standard 50 ohm input/output impedance. As such, packaged chips designed by separate manufacturers may be used substantially interchangeably in some implementations.
In some embodiments, a modular packaged semiconductor chip according to embodiments of the present invention includes a first type of amplifier semiconductor substrate (e.g., a GaN amplifier die or other relatively high cost semiconductor process die), and input and/or output matching circuits implemented on one or more separate semiconductor substrates of one or more other types for input and/or output matching circuits (e.g., GaAs) within a single package.
Fig. 11 shows a packaged
The packaged
The packaged
Fig. 12A and 12B show top and side views, respectively, of an interface between a first semiconductor-type power amplifier die 1210 (e.g., GaN) and a matching circuit die 1280, which may include a different semiconductor substrate, such as a relatively lower cost substrate (e.g., GaAs). In some embodiments, a packaged semiconductor chip according to embodiments of the invention may have one or more features of the illustrated interface 1201 between the amplifier die and the input and/or output matching die. In some embodiments, interface 1201 may form part of a matching circuit of amplifier die 1210.
The power amplifier die 1210 and the matching circuit die 1280 may be coupled using one or more bond wires 1236, as shown. The power amplifier die 1210 and the matching circuit die 1280 may be disposed any suitable or desired distance d apart. For example, in some embodiments, the amplifier die 1210 and the matching circuit die 1280 are spaced apart by approximately 5 mm.
In some embodiments, a packaged semiconductor chip according to embodiments of the present disclosure includes a power amplifier semiconductor die having an amount of pre-matching implemented on the amplifier semiconductor die, wherein no additional matching circuit die is included in the package. Fig. 13 illustrates a packaged semiconductor chip 1300 having both on-chip impedance matching 1360 and off-chip impedance matching 1361 in accordance with one or more embodiments of the present disclosure. In some embodiments, power amplifier substrate 1310 includes one or more transmission lines, capacitors, resistors, and/or other passive elements implemented thereon for impedance matching. The package 1330 may be mounted to a circuit board 1340 with additional matching circuits 1361 implemented thereon, which may include one or more transmission lines, cones, and/or other passive matching elements. Matching circuit 1361 may be implemented on board 1340 and/or in another packaged chip mounted on board 1340.
In some embodiments, the package features and wire bonded interface 1301 may be configured to perform some of the radio frequency matching functions, while the remaining matching functions may be implemented by radio frequency splitting/combining and/or other passive elements implemented on the internal power semiconductor substrate 1310 of the packaged semiconductor chip 1300. In some embodiments, the on-chip matching circuit 1360 includes one or more capacitors 1364 and one or more transmission lines 1363.
For modular high power amplifier architectures according to embodiments of the invention, impedance matching may be achieved using one or more matching elements implemented in connective circuitry on a circuit board between individually packaged semiconductor chips.
Fig. 14 illustrates on-board matching between packaged amplifier chips 1430 in a modular high power amplifier architecture according to an embodiment of the invention. In some implementations, inter-stage matching is achieved between packaged semiconductor amplifier chips in the connectivity circuitry between amplifier stages and/or chips. For example, an on-board matching circuit according to an embodiment of the present invention may include one or more transmission lines 1401 and/or tapers 1402 in addition to one or more splitters/combiners 1403 between amplifier stages. Such transmission lines and/or tapers can have any suitable or desired width and/or impedance characteristics and can be designed to match a particular input and/or output load and impedance of chip 1430.
As described herein, embodiments of packaged semiconductor chips according to aspects of the present disclosure may include single-stage power amplifier dies (e.g., GaN dies) in leadless packages. Such a single stage amplifier die may be implemented in any suitable or desirable manner. Fig. 15 shows an exemplary implementation of a single stage power amplifier die that includes a semiconductor substrate 1510 implemented in a chip package 1530. A packaged semiconductor chip similar to chip 1500 as in fig. 15 may be arranged on a printed circuit board in a modular high power amplifier architecture. For example, in some implementations, a packaged semiconductor chip similar to chip 1500 of fig. 15 may be arranged in accordance with the three-
Fig. 16 illustrates another exemplary architecture of a single-stage power amplifier die 1610 implemented in a chip package 1630. The power amplifier die 1610 may include a GaN or other type of semiconductor substrate. In some embodiments, the amplifier die 1610 includes two banks 1601, 1602 of transistors connected in parallel.
Fig. 17 illustrates an
Fig. 18 shows an embodiment of a two-stage amplifier die that includes a
An output bias voltage may be provided on another
Fig. 19-21 illustrate exemplary amplifier architectures that may incorporate modular packaged semiconductor chips according to embodiments of the invention. For example, the various chips shown in fig. 19-21 may be similar in some respects to the packaged semiconductor chip 800 shown in fig. 8 and described above.
Fig. 19 shows a four-stage amplifier architecture comprising two sets 1901, 1902 of two-stage packaged semiconductor amplifier chips connected in parallel. Fig. 20 shows a four-
As described in detail herein, a modular high power amplifier architecture utilizing individually packaged semiconductor chips electrically coupled on a printed circuit board or other substrate may allow a relatively high percentage of semiconductor die area (e.g., GaN die area) to be allocated for active amplifier transistors and less semiconductor die area to be allocated for passive matching circuits. This may be achieved, for example, by one or more of the following methods and/or features: having a semiconductor die interface impedance with a non-standard value (e.g., an impedance value other than 50, or any suitable impedance) may allow for only a partially necessary or desirable radio frequency matching circuit to be implemented on the semiconductor die or not; performing at least a portion of the necessary or desired radio frequency matching using the package features and/or wire bonded interface elements; and using the circuit board or other substrate on which the packaged semiconductor chip is mounted for all or a portion of the rf splitting/combining and/or remaining portions of the necessary or desired rf matching circuitry. For certain other off-chip matching solutions, such solutions may only be suitable for relatively low frequencies, where parasitic elements of the bond wires and/or of the package are relatively small. With respect to high frequency operation according to embodiments of the present disclosure, it may be advantageous to achieve a certain amount of impedance matching on a semiconductor die in order to make the die relatively less sensitive to parasitic elements of bond wires and/or package interfaces, and to use such parasitic elements as part of necessary or desired impedance matching circuitry.
Embodiments of the present disclosure allow for the gate bias implant and/or the drain bias implant to be configured in the following manner: allowing building block packaged semiconductor chips to be cascaded in series to achieve higher gain and/or cascaded in parallel to provide desired power scalability. The radio frequency input path may be blocked by Direct Current (DC) while the radio frequency output may not be blocked by DC, so that the drain/output voltage may be injected on the radio frequency splitter/combiner network without the need for additional off-chip DC blocking circuitry. The input/gate voltages may be applied via a bias network that may be interconnected to parallel chips. In some embodiments, all of the stabilization circuitry is included in the packaged chip, such that no external bypass is required. In some embodiments, the first level gate voltage and the second level gate voltage and/or drain voltage are interconnected on the die of the chip such that no external connections are required.
Embodiments of the present disclosure may advantageously provide improved design flexibility and/or simplicity. For example, with building block packaged amplifier chips, power amplifiers of different power levels and/or different gates may be fabricated simply by modifying or changing the connections or features of the motherboard without requiring additional fabrication cycles of the semiconductor wafer. Since the same building block chip is used multiple times, more design effort/strength can be used to optimize performance and/or minimize die size, as this yields a factor of two greater. Furthermore, since the building block packaged semiconductor chips of the present disclosure disperse the thermal distribution of the power amplifier architecture and can be spread out on a printed circuit board as needed or desired, the package may become relatively cheaper and may not require as much metal for thermal energy dissipation. That is, the thermal profile design may be balanced against the printed circuit board size.
General notes
Throughout the specification and claims, the words "comprise", "comprising", and the like, are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense, unless the context clearly requires otherwise; that is, there is a meaning of "including but not limited to". The term "coupled," as generally used herein, refers to two or more elements that may be connected directly or through one or more intermediate elements. Additionally, as used in this application, the words "herein," "above," "below," and words of similar import shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words described above using the singular or plural number may also include the plural or singular number respectively.
The word "or" refers to a list of two or more items that encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
Reference throughout this disclosure to "some embodiments," "certain embodiments," or "embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least some embodiments. Thus, the appearances of the phrases "in some embodiments," "in certain embodiments," or "in embodiments" in various places throughout this specification are not necessarily all referring to the same embodiments, but may refer to one or more of the same or different embodiments. Furthermore, the embodiments disclosed herein may or may not be embodiments of the present invention. For example, embodiments disclosed herein may partially or fully include non-inventive features and/or components. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art in view of this disclosure, in one or more embodiments.
The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a number of different ways. Additionally, while processes or blocks are sometimes shown as being performed in a sequential order, these processes or blocks may instead be performed in parallel, or may be performed at different times.
The teachings of the invention provided herein are applicable to other systems, not necessarily the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.
While certain embodiments of the invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
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