阅读说明：本技术 半导体封装件 (Semiconductor package ) 是由 闵丙国 姜允熙 宋旼友 于 2020-02-12 设计创作，主要内容包括：一种半导体封装件,包含：第一半导体芯片,具有上表面、与上表面相对的下表面以及在上表面与下表面之间的侧壁；封端绝缘层,覆盖第一半导体芯片的上表面和侧壁；以及屏蔽层,在封端绝缘层上,其中封端绝缘层的下部部分包含接触屏蔽层的下表面的侧向突出封端突出部。(A semiconductor package, comprising: a first semiconductor chip having an upper surface, a lower surface opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a cap insulating layer covering an upper surface and sidewalls of the first semiconductor chip; and a shield layer on the capping insulating layer, wherein a lower portion of the capping insulating layer includes a laterally protruding capping protrusion contacting a lower surface of the shield layer.)

1. A semiconductor package, comprising:

a first semiconductor chip having an upper surface, a lower surface opposite the upper surface, and a sidewall between the upper surface and the lower surface;

a capping insulating layer covering the upper surface and the sidewall of the first semiconductor chip; and

a shield layer on the capping insulating layer,

wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.

2. The semiconductor package of claim 1, wherein outer sidewalls of the lower portion of the capping insulating layer are aligned with outer sidewalls of the shielding layer.

3. The semiconductor package of claim 1, wherein:

the terminating insulating layer has a first terminating sidewall covered by the shielding layer and a second terminating sidewall at the laterally protruding terminating protrusion, and

the second end-capped sidewalls have a surface roughness greater than a surface roughness of the first end-capped sidewalls.

4. The semiconductor package of claim 1, wherein:

the shield layer has a first shield sidewall spaced apart from the termination protrusion and a second shield sidewall adjacent to the termination protrusion, an

The surface roughness of the second shield sidewall is greater than the surface roughness of the first shield sidewall.

5. The semiconductor package of claim 1, wherein a lower portion of the shielding layer protrudes laterally on the laterally protruding termination protrusion.

6. The semiconductor package of claim 1, wherein:

the shielding layer includes:

a first shielding layer adjacent to the capping insulating layer, an

A second shield layer on the first shield layer and spaced apart from the capping insulating layer, and

the first shield layer includes a metal different from a metal included in the second shield layer.

7. The semiconductor package of claim 6, wherein a lower portion of the first shield layer protrudes laterally on the laterally protruding termination protrusion and contacts a lower surface of the second shield layer.

8. The semiconductor package of claim 1, further comprising:

a substrate on the lower surface of the first semiconductor chip and protruding outward with respect to the sidewall of the first semiconductor chip; and

a molding layer on an upper surface of the substrate and on the sidewalls of the first semiconductor chip,

wherein:

the capping insulating layer contacts the sidewall of the substrate and the molding layer, and

the substrate is a redistribution layer or an encapsulation substrate.

9. The semiconductor package of claim 1, further comprising:

an upper package substrate on the first semiconductor chip;

a second semiconductor chip on the upper package substrate; and

a molding layer on the second semiconductor chip and the upper package substrate,

wherein the capping insulating layer contacts a sidewall of the upper package substrate and the molding layer.

10. The semiconductor package of claim 9, wherein the capping insulating layer extends between the upper package substrate and the first semiconductor chip.

11. The semiconductor package of claim 9, further comprising:

a lower package substrate on the lower surface of the first semiconductor chip; and

a package connection structure electrically connecting the upper package substrate and the lower package substrate,

wherein the end-capping insulating layer contacts a sidewall of the package connection structure.

12. The semiconductor package of claim 9, further comprising:

a redistribution layer on the lower surface of the first semiconductor chip;

a connection substrate on the redistribution layer; and

a package connection structure extending through the connection substrate and electrically connecting the upper package substrate with the connection substrate,

wherein the capping insulating layer extends to contact a sidewall of the package connection structure.

13. The semiconductor package of claim 1, further comprising:

a substrate on the lower surface of the first semiconductor chip and protruding outward with respect to the sidewall of the first semiconductor chip; and

a molding layer covering an upper surface of the substrate and sidewalls of the shielding layer,

wherein the substrate is a redistribution layer or an encapsulation substrate.

14. The semiconductor package of claim 13, wherein the molding layer contacts the laterally protruding end-capping protrusion of the end-capping insulation layer.

15. The semiconductor package according to claim 13, further comprising:

an upper redistribution pattern on the molding layer and electrically connected to the substrate; and

an upper semiconductor package on and electrically connected to the upper redistribution pattern.

16. A semiconductor package, comprising:

a first semiconductor chip having an upper surface, a lower surface opposite the upper surface, and a sidewall between the upper surface and the lower surface; and

a capping insulating layer covering the upper surface and the sidewalls of the first semiconductor chip,

wherein:

the capping insulating layer has a first capping sidewall and a second capping sidewall below the first capping sidewall such that the second capping sidewall is adjacent to the lower surface of the first semiconductor chip, an

The second end-capped sidewalls have a surface roughness greater than a surface roughness of the first end-capped sidewalls.

17. The semiconductor package of claim 16, further comprising a shield layer on the capping insulator layer,

wherein a lower portion of the capping insulating layer protrudes laterally and contacts a lower surface of the shielding layer.

18. The semiconductor package according to claim 16, further comprising:

an upper package substrate on the first semiconductor chip;

a second semiconductor chip on the upper package substrate; and

a molding layer covering the second semiconductor chip and the upper package substrate,

wherein the capping insulating layer contacts a sidewall of the upper package substrate and the molding layer.

19. The semiconductor package of claim 18, wherein the capping insulating layer extends between the upper package substrate and the first semiconductor chip.

20. The semiconductor package of claim 18, further comprising:

a lower package substrate on the lower surface of the first semiconductor chip; and

a package connection structure electrically connecting the upper package substrate and the lower package substrate,

wherein the end-capping insulating layer contacts a sidewall of the package connection structure.

21. A semiconductor package, comprising:

a first semiconductor chip having an upper surface, a lower surface opposite the upper surface, and a sidewall between the upper surface and the lower surface;

a capping insulating layer on the upper surface and the sidewalls of the first semiconductor chip; and

a shield layer on the capping insulating layer,

wherein a lower outer sidewall of the capping insulating layer is vertically aligned with a lower outer sidewall of the shielding layer.

22. The semiconductor package of claim 21, further comprising an edge chip conductive pattern on an edge of the lower surface of the first semiconductor chip and spaced apart from the shielding layer,

wherein the end-capping insulating layer is between the shielding layer and the edge chip conductive pattern.

23. The semiconductor package of claim 21, wherein a lower portion of the capping insulating layer protrudes laterally and contacts a lower surface of the shielding layer.

24. The semiconductor package of claim 21, wherein:

the end-capping insulating layer includes an upper outer sidewall on the lower outer sidewall thereof, and

the surface roughness of the lower outer side wall of the end-capping insulating layer is greater than the surface roughness of the upper outer side wall of the end-capping insulating layer.

25. The semiconductor package of claim 21, wherein:

the shielding layer includes an upper outer sidewall on the lower outer sidewall thereof, and

the surface roughness of the lower outer sidewall of the shielding layer is greater than the surface roughness of the upper outer sidewall of the shielding layer.

Technical Field

Example embodiments of the present disclosure relate to a semiconductor package.

Background

The semiconductor package may be implemented in a form that makes the integrated circuit device suitable for an electronic device. For example, a semiconductor package may have a structure in which a semiconductor chip is mounted on a Printed Circuit Board (PCB) and bonding wires and/or bumps electrically connect the semiconductor chip with the PCB.

Disclosure of Invention

Drawings

Features will be apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

fig. 1 illustrates a perspective view of a semiconductor package according to an example embodiment.

Fig. 2A shows a cross-sectional view taken along line I-I' of fig. 1.

Fig. 2B illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Fig. 3A, 3B, and 3C illustrate enlarged views of a portion 'P1' of fig. 2A.

Fig. 4 shows an enlarged view of a portion 'P2' of fig. 3A.

Fig. 5A, 5B, and 5C illustrate cross-sectional views of stages in a method of manufacturing a semiconductor package having the cross-section of fig. 2A according to an example embodiment.

Fig. 6 illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Fig. 7 illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Fig. 8 illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Fig. 9 illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Fig. 10 illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Fig. 11 shows an enlarged view of a portion 'P1' of fig. 10.

Fig. 12 illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Fig. 13 illustrates a cross-sectional view of a semiconductor package according to an example embodiment.

Description of the reference numerals

10: a lower semiconductor chip;

12: a chip conductive pattern;

12 p: an edge chip conductive pattern;

14: a chip protection layer;

15: an internal connection structure;

15 a: a conductive post;

15 b: a solder layer;

16: an external connection terminal;

17: an underfill layer;

18: a molding layer;

20: an end-capping insulating layer;

20 a: a polymer-containing layer;

20 b: insulating particles;

20 p: a laterally projecting end-capping protrusion;

20s 1: a first end-capped sidewall;

20s 2: a second end-capped sidewall;

30: a shielding layer;

30 a: a first shielding layer;

30 ap: laterally projecting a first shield projection;

30 b: a second shielding layer;

30 p: a laterally projecting shielding projection;

30s 1: a first shield sidewall;

30s 2: a second shield sidewall;

30 sp: a middle shield projection;

40: distributing layers;

41: redistributing the pattern;

42: a package substrate;

43: a ball pad;

50: a carrier substrate;

51: a housing portion;

52: packaging the connecting structure;

54: an upper package substrate;

56: an upper semiconductor chip;

58: an upper molding layer;

60: a layer of thermal interface material;

70: connecting the substrate;

71: a connection wiring structure;

72: a chamber;

73: connecting the insulating layer;

80: an upper redistribution layer;

81: an upper redistribution pattern;

83: a through hole;

100. 100a, 101, 102, 103, 104, 105, 106, 107: a semiconductor package;

100 p: a preliminary semiconductor package;

I-I': a wire;

LPK: a lower semiconductor package;

p1, P2: a moiety;

r1: a recessed region;

and (3) UPK: an upper semiconductor package;

v1: a first air gap region;

v2: a second air gap region.

Embodiments may be realized by providing a semiconductor package including a first semiconductor chip having an upper surface, a lower surface opposite to the upper surface, and a sidewall between the upper surface and the lower surface; an end-capping insulating layer covering the upper surface and the sidewall of the first semiconductor chip; and a shield layer on the capping insulating layer, wherein a lower portion of the capping insulating layer includes a laterally protruding capping protrusion contacting a lower surface of the shield layer.