阅读说明：本技术 芯片封装结构、其制作方法和电子设备 (Chip packaging structure, manufacturing method thereof and electronic equipment ) 是由 孙杰 何正鸿 于 2020-07-27 设计创作，主要内容包括：本申请提供了一种芯片封装结构、其制作方法和电子设备,涉及芯片技术领域。本申请实施例中的芯片封装结构通过在搭载芯片的基材上设置了过载保护器,并将过载保护器与芯片通过重新布线层的线路串联起来,使得芯片在运行时可以受到过载保护器的保护而避免损坏。根据需要选择过载保护器的类型,比如电流过载保护器、温度过载保护器。当电流或温度超过预设值时,过载保护器断路,使得成本较高的芯片得到保护。本申请实施例提供的制作方法用于制作本申请实施例提供的芯片封装结构。本申请提供的电子设备采用了本申请实施例提供的芯片封装结构或者本申请提供的制作方法所制得的芯片封装结构,因此也具有使用寿命长,维护成本低的问题。(The application provides a chip packaging structure, a manufacturing method thereof and electronic equipment, and relates to the technical field of chips. The chip packaging structure in the embodiment of the application is provided with the overload protector on the base material carrying the chip, and the overload protector and the chip are connected in series through the circuit of the rewiring layer, so that the chip can be protected by the overload protector to avoid damage when in operation. The type of overload protector, such as current overload protector, temperature overload protector, is selected as required. When the current or the temperature exceeds a preset value, the overload protector is broken, so that the chip with higher cost is protected. The manufacturing method provided by the embodiment of the application is used for manufacturing the chip packaging structure provided by the embodiment of the application. The electronic device provided by the application adopts the chip packaging structure provided by the embodiment of the application or the chip packaging structure manufactured by the manufacturing method provided by the application, so that the problems of long service life and low maintenance cost are solved.)

1. A chip package structure, comprising:

the chip mounting structure comprises a base material, a protective device and a chip, wherein the base material is provided with a protective device mounting groove and a chip mounting groove;

the chip and the overload protector are arranged on the base material, the overload protector is arranged in the protector mounting groove, and the chip is arranged in the chip mounting groove;

and the protection device mounting groove and the chip mounting groove are provided with openings covered by the rewiring layer, and the circuit of the rewiring layer extends to one side of the rewiring layer adjacent to the base material and connects the chip and the overload protection device in series.

2. The chip package structure according to claim 1, wherein the substrate has a first side and a second side opposite to each other, the rewiring layer is disposed on the first side of the substrate, the protector mounting groove penetrates through the substrate, and a blocking portion is filled in the mounting groove; the overload protector is adjacent to the first side of the substrate relative to the blocking portion.

3. The chip package structure according to claim 2, wherein the blocking portion is a thermoplastic adhesive and blocks an opening of the mounting groove on the second side of the substrate.

4. The chip package structure according to claim 2, wherein the overload protector abuts the blocking portion.

5. The chip package structure of claim 1, wherein the overload protector is a temperature protector, a current protector, or a voltage protector.

6. The chip package structure according to claim 1, wherein a side of the redistribution layer facing away from the substrate is provided with a plurality of solder balls, the solder balls are connected to the wires, and at least two wires between the solder balls connect the overload protector and the chip in series.

7. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:

a chip mounting groove and a protector mounting groove are formed in the base material;

fixing a chip in the chip mounting groove, and fixing an overload protector in the protector mounting groove;

and manufacturing a rewiring layer on the base material, wherein the rewiring layer covers the openings of the chip mounting groove and the protector mounting groove, and the chip and the overload protector are connected in series through a circuit in the rewiring layer.

8. The method for manufacturing the chip packaging structure according to claim 7, wherein the step of forming the chip mounting groove and the protector mounting groove on the substrate comprises:

placing the base material on a temporary carrier plate, and manufacturing the chip mounting groove and the protector mounting groove on the base material by adopting an etching process, wherein the protector mounting groove extends to the temporary carrier plate in the depth direction;

fixing the overload protector in the step in the protector mounting groove, including:

and filling thermoplastic glue at one end of the protector mounting groove close to the temporary carrier plate to form a blocking part, and mounting the overload protector on the blocking part.

9. An electronic device comprising the chip packaging structure of any one of claims 1 to 6, or the chip packaging structure manufactured by the manufacturing method of any one of claims 7 to 8.

Technical Field

The application relates to the technical field of chips, in particular to a chip packaging structure, a manufacturing method thereof and electronic equipment.

Background

With the rapid development of the semiconductor industry, Fan-out wafer level package (FOWLP) is widely used in the semiconductor industry. As the number of transistors in a chip increases, the stability, lifetime, etc. of the chip operation need to be focused. Under the condition that the area of the chip is not greatly increased, the chip is often damaged due to some reasons (such as overheating and excessive current), so that the use cost is high.

Disclosure of Invention

The purpose of the application includes providing a chip packaging structure, which can better protect the chip and make it not easy to damage. The application also provides a manufacturing method of the chip packaging structure and electronic equipment comprising the chip packaging structure, and the electronic equipment has the characteristics of long service life and low maintenance cost.

The embodiment of the application can be realized as follows:

in a first aspect, an embodiment of the present application provides a chip package structure, including:

the substrate is provided with a protector mounting groove and a chip mounting groove;

the chip and the overload protector are arranged on the base material, the overload protector is arranged in the protector mounting groove, and the chip is arranged in the chip mounting groove;

and the rewiring layer is arranged in a laminated manner with the base material, the protector mounting groove and the chip mounting groove are provided with openings covered by the rewiring layer, and the circuit of the rewiring layer extends to one side of the rewiring layer adjacent to the base material and connects the chip and the overload protector in series.

In an alternative embodiment, the base material is provided with a protector mounting groove and a chip mounting groove, both the protector mounting groove and the chip mounting groove are provided with openings covered by the rewiring layer, the overload protector is arranged in the protector mounting groove, and the chip is arranged in the chip mounting groove; the wiring extends to a side of the rewiring layer adjacent to the base material and is electrically connected to the chip and the overload protector.

In an alternative embodiment, the substrate has a first side and a second side opposite to each other, the rewiring layer is disposed on the first side of the substrate, the protector installation groove penetrates through the substrate, and the blocking portion is filled in the installation groove; the overload protector is adjacent to the first side of the substrate relative to the blocking portion.

In an alternative embodiment, the blocking portion is a thermoplastic glue and blocks the opening of the mounting groove at the second side of the substrate.

In an alternative embodiment, the overload protector abuts the blocking portion.

In an alternative embodiment, the overload protector is a temperature protector, a current protector or a voltage protector.

In an optional embodiment, a plurality of solder balls are arranged on one side of the rewiring layer, which is away from the base material, the solder balls are connected with the circuit, and the overload protector and the chip are connected in series through the circuit between at least two solder balls.

In a second aspect, an embodiment of the present application provides a method for manufacturing a chip package structure, including:

a chip mounting groove and a protector mounting groove are formed in the base material;

fixing the chip in the chip mounting groove, and fixing the overload protector in the protector mounting groove;

and manufacturing a rewiring layer on the base material, wherein the rewiring layer covers the openings of the chip mounting groove and the protector mounting groove, and the chip and the overload protector are connected in series through a circuit in the rewiring layer.

In an alternative embodiment, the step of forming the chip mounting groove and the protector mounting groove on the base material includes:

placing a base material on a temporary support plate, and manufacturing a chip mounting groove and a protector mounting groove on the base material by adopting an etching process, wherein the protector mounting groove extends to the temporary support plate in the depth direction;

the step of being fixed in the protector mounting groove with overload protector includes:

and filling thermoplastic glue at one end of the protector mounting groove close to the temporary carrier plate to form a blocking part, and mounting an overload protector on the blocking part.

In a third aspect, an embodiment of the present application provides an electronic device, including the chip packaging structure in any one of the foregoing embodiments, or including the chip packaging structure manufactured by the manufacturing method in any one of the foregoing embodiments.

The beneficial effects of the embodiment of the application include, for example:

the chip packaging structure in the embodiment of the application is provided with the overload protector on the base material carrying the chip, and the overload protector and the chip are connected in series through the circuit of the rewiring layer, so that the chip can be protected by the overload protector to avoid damage when in operation. The type of overload protector, such as current overload protector, temperature overload protector, is selected as required. When the current or the temperature exceeds a preset value, the overload protector is broken, so that the chip with higher cost is protected. Set up overload protector and chip in the mounting groove that corresponds, can show and reduce the encapsulation volume to make overload protector and chip more stable.

The manufacturing method provided by the embodiment of the application is used for manufacturing the chip packaging structure provided by the embodiment of the application. The electronic device provided by the application adopts the chip packaging structure provided by the embodiment of the application or the chip packaging structure manufactured by the manufacturing method provided by the application, so that the problems of long service life and low maintenance cost are solved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure;

fig. 2 is a flowchart illustrating a method for fabricating a chip package structure according to an embodiment of the present disclosure;

fig. 3 to 8 are schematic diagrams illustrating different aspects of a chip package structure in a manufacturing process according to an embodiment of the present application.

Icon: 010-chip package structure; 100-a substrate; 110-chip mounting groove; 112-plastic package body; 120-protector mounting groove; 122-a blocking portion; 200-chip; 300-an overload protector; 400-rewiring layer; 410-line; 420-a dielectric material; 430-metal posts; 500-tin ball; 020-temporary carrier plate.

Detailed Description

With the rapid development of the semiconductor industry, Fan-out wafer level package (FOWLP) is widely used in the semiconductor industry. As the number of transistors in a chip increases, the amount of heat generated also increases. Under the condition that the area of the chip is not greatly increased, the heating density of the device is higher and higher, and the packaged device on the back-end circuit board generates heat, so that the chip is overheated and burnt out; or, different devices on the circuit board are impacted by current, so that the chip of the packaging body is damaged by current overload. Generally, a chip (7 nm/5 nm chip) packaged by a fan-out wafer level is valuable, for example, when the chip is applied to a chip packaging structure of a central Processing unit (cpu), a graphic Processing unit (gpu), and an artificial intelligence (ai), the inside of the chip packaging structure is not protected by an overload protection device, and once the chip is damaged, only the whole chip packaging structure can be replaced, which often brings higher maintenance cost.

In order to solve the above mentioned problems that a chip is easily damaged and the maintenance cost of a corresponding electronic device is high, embodiments of the present application provide a chip packaging structure, a manufacturing method thereof, and an electronic device. In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. It should be noted that, in the description of the present application, if the terms "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the product of the present invention is usually placed in when used, it is only for convenience of description and simplification of the description, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.

Fig. 1 is a schematic diagram of a chip package structure 010 according to an embodiment of the present disclosure. Referring to fig. 1, the chip package structure 010 of the present embodiment includes a substrate 100, a chip 200 and an overload protector 300 disposed on the substrate 100, and a redistribution layer 400 disposed on the substrate 100 in a stacked manner, wherein a circuit 410 in the redistribution layer 400 connects the overload protector 300 and the chip 200 in series. When the current, voltage, temperature, or the like is too high, the overload protector 300 can perform disconnection so that the chip 200 can be protected.

As shown in fig. 1, the substrate 100 of the embodiment of the present application is provided with a protector mounting groove 120 and a chip mounting groove 110, the protector mounting groove 120 and the chip mounting groove 110 both have an opening covered by a rewiring layer 400, an overload protector 300 is disposed in the protector mounting groove 120, and a chip 200 is disposed in the chip mounting groove 110. The chip mounting groove 110 may be filled with a molding body 112 to fix the chip 200. The line 410 of the rewiring layer 400 extends to the side of the rewiring layer 400 adjacent to the base material 100, and is electrically connected to the chip 200 and the overload protector 300. In the present embodiment, the chip 200 is a wafer having fabricated integrated circuits thereon. The re-Routing (RDL) is to change the contact position (I/Opad) of the originally designed integrated circuit 410 on the chip 200 by the wafer level metal routing process and the bump process, so that the integrated circuit can be applied to different packaging forms. The rewiring layer 400 is composed of a dielectric material 420 and a wire 410 buried in the dielectric material 420.

In this embodiment, the substrate 100 may be made of silicon, silicon dioxide, polymer, or the like. The substrate 100 has a first side (upper side in fig. 1) and a second side (lower side in fig. 1) opposite to each other, the rewiring layer 400 is provided on the first side of the substrate 100, the protector mounting groove 120 penetrates the substrate 100, and the mounting groove is filled with the blocking portion 122. The overload protector 300 is positioned adjacent to a first side of the substrate 100 relative to the blocking portion 122.

In the present embodiment, one end of the overload protector 300 abuts against the blocking portion 122, and the other end is connected to the line 410 of the rewiring layer 400, so that the overload protector 300 does not fall out of the protector mounting groove 120 from the first side to the second side of the base material 100 by the blocking action of the blocking portion 122. The blocking portion 122 is made of thermoplastic glue, and blocks the opening of the mounting groove on the second side of the substrate 100. By filling a part of the protector mounting groove 120 with thermoplastic glue as the blocking portion 122, it is possible to soften the thermoplastic glue by heating when the overload protector 300 needs to be replaced, that is, to take out the overload protector 300 from the second side of the base material 100. Particularly for one type of overload protector 300, after chip 200 is protected, it needs to be replaced to maintain protection of chip 200. It should be appreciated that the strength of the connection between the overload protector 300 and the lines 410 of the rewiring layer 400 is relatively small, and the overload protector 300 can be directly peeled off when replaced.

Of course, in the embodiment of the present application, the blocking portion 122 plays a role of supporting the overload protector 300 and preventing the overload protector 300 from falling out, and the overload protector 300 can be replaced conveniently by using the thermoplastic adhesive. In other embodiments of the present application, the installation position of the blocking portion 122 may also be located at the middle of the protector installation groove 120, not necessarily near the second side of the substrate 100. The blocking portion 122 may be made of a material that is not selected from thermoplastic adhesives, and may be a shaped detachable member to support the overload protector 300.

Optionally, the overload protector 300 is a temperature protector, a current protector, or a voltage protector. Correspondingly, when the current (voltage) in the line 410 exceeds a predetermined value, or the temperature of the area exceeds a predetermined value, the overload protector 300 is open, so that the line 410 stops supplying power to the chip 200 to protect the chip 200 from being damaged by the excessive current/voltage, or the chip 200 stops generating high heat. Thus, line 410 may be a power line, and chip 200 is connected to a power source (not shown) via line 410, and when the power line exhibits an open circuit due to overload protector 300 being open, chip 200 is no longer energized and generating heat.

In the present embodiment, a plurality of solder balls 500 are disposed on a side of the redistribution layer 400 away from the substrate 100. The redistribution layer 400 may have a plurality of metal pillars 430 on a side thereof away from the substrate 100, the metal pillars 430 may serve as ball-planting points, and the metal pillars 430 are connected to pins on the chip 200 through the wires 410. It is understood that the pins on chip 200 are rearranged, corresponding to metal studs 430. Furthermore, the solder balls 500 are connected to the wires 410, and at least two wires 410 between the solder balls 500 connect the overload protector 300 and the chip 200 in series, so that whether the overload protector 300 is normal can be tested by the two solder balls 500 (or the metal posts 430 on which the two solder balls 500 are mounted).

The chip package structure 010 provided by the embodiment of the application can protect the chip 200 through the overload protector 300, so that the chip 200 is not easy to damage, and the maintenance cost is reduced. By disposing the overload protector 300 within the substrate 100, the overload protector 300 is prevented from occupying additional space. The blocking portion 122 made of thermoplastic glue functions to support the overload protector 300 and also facilitates the replacement of the overload protector 300.

Fig. 2 is a flowchart illustrating a method for fabricating a chip package structure according to an embodiment of the present disclosure; fig. 3 to 8 are schematic diagrams illustrating different aspects of a chip package structure in a manufacturing process according to an embodiment of the present application. The manufacturing method of the chip packaging structure provided by the embodiment of the application comprises the following steps:

and S100, forming a chip mounting groove and a protector mounting groove in the base material.

Taking the chip package structure 010 provided in the embodiment of the present application as an example, when the groove is formed, the substrate 100 is first placed on the temporary carrier 020, and the temporary carrier 020 plays a role in temporary support. The temporary carrier 020 can be made of glass, silicon oxide, metal, etc. The temporary carrier plate 020 is supported on a second side of the substrate 100, i.e. the side facing away from the redistribution layer 400 to be laid. Then, etching the chip mounting groove 110 and the protector mounting groove 120 on the base material 100 by using an etching process, as shown in fig. 3; wherein the areas not requiring etching are protected by a protective film. In the embodiment, the chip mounting groove 110 has only one opening, and the protector mounting groove 120 penetrates through the first side and the second side of the substrate 100, and the opening on the second side is blocked by the temporary carrier plate 020.

And S200, fixing the chip in the chip mounting groove, and fixing the overload protector in the protector mounting groove.

Take the fabrication of the chip package structure 010 provided in the embodiments of the present application as an example. When mounting the chip 200, the chip 200 is first mounted to the bottom of the chip mounting groove 110, and then the gap between the chip mounting groove 110 and the chip 200 is filled with the molding body 112, thereby fixing the chip 200. As shown in fig. 4, the pins of the chip 200 face upward, and the upper surface of the chip 200 is substantially flush with the surface of the substrate 100, so as to facilitate the connection of the lines 410 of the redistribution layer 400 to the chip 200.

When the overload protector 300 is installed, firstly, thermoplastic glue is filled in one end of the protector installation groove 120 close to the temporary carrier plate 020 to form a blocking portion 122, as shown in fig. 5; the overload protector 300 is then installed on the blocking portion 122 as shown in fig. 6. Specifically, the amount of thermoplastic adhesive should be suitable so that the upper surface of the overload protector 300 is substantially flush with the surface of the substrate 100 after installation to facilitate connection of the lines 410 of the redistribution layer 400 to the overload protector 300 for subsequent fabrication. In the process of filling the thermoplastic glue to form the blocking portion 122, the temporary carrier plate 020 plays a role of supporting the thermoplastic glue, so that after the blocking portion 122 is molded, it blocks the opening of the protector installation groove 120 at the second side of the substrate 100 and is flush with the surface of the second side of the substrate 100.

Step S300 is to form a redistribution layer 400 on the substrate 100, wherein the redistribution layer 400 covers the openings of the chip mounting groove 110 and the protector mounting groove 120, and the chip 200 and the overload protector 300 are connected in series by a line 410 in the redistribution layer 400.

In this embodiment, a dielectric layer is first laid on the surface of the first side (upper side in fig. 7) of the substrate 100, and the pins of the chip 200 and the ports of the overload protector 300 are exposed, as shown in fig. 7; wiring then takes place, including forming wires 410 that connect overload protector 300 and chip 200 in series. In the present embodiment, the fabrication of the redistribution layer 400 further includes forming metal pillars 430 by an electro-coppering process, which are exposed on the surface of the redistribution layer 400 and serve as ball-planting points, as shown in fig. 8. When the rewiring layer 400 has a plurality of layers of wires 410, it can be manufactured by a method of laying the dielectric material 420 a plurality of times and a plurality of times. The specific process of fabricating the rewiring layer 400 may refer to an existing RDL process, and will not be described in detail here.

After the redistribution layer 400 is fabricated, ball mounting is performed to form solder balls 500 connected to the metal pillars 430, and finally the temporary carrier plate 020 is removed to obtain the chip package structure 010 shown in fig. 1.

In addition, an electronic device (not shown in the drawings) including the chip package structure 010 of the foregoing embodiment or including the chip package structure manufactured by the manufacturing method of the foregoing embodiment is also provided in the embodiments of the present application. The electronic device adopts the chip packaging structure 010, so that the chip 200 can be well protected, the service life is long, and the maintenance cost is low.

In summary, the embodiment of the present application provides a chip package structure 010, a manufacturing method thereof, and an electronic device. The chip package structure 010 of the present application is configured with the overload protector 300 on the substrate 100 carrying the chip 200, and connects the overload protector 300 and the chip 200 in series through the line 410 of the rewiring layer 400, so that the chip 200 can be protected by the overload protector 300 to avoid damage during operation. The type of overload protector 300, such as a current overload protector, a temperature overload protector, is selected as desired. When the current or temperature exceeds a preset value, the overload protector 300 is opened, so that the chip 200 with higher cost is protected. The overload protector 300 and the chip 200 are disposed in the corresponding mounting grooves, so that the package size can be remarkably reduced, and the overload protector 300 and the chip 200 are more stable.

The manufacturing method provided by the embodiment of the application is used for manufacturing the chip packaging structure 010 provided by the embodiment of the application. The electronic device provided by the application adopts the chip packaging structure 010 provided by the embodiment of the application or the chip packaging structure manufactured by the manufacturing method provided by the application, so that the problems of long service life and low maintenance cost are solved.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.