Semiconductor device and method for manufacturing the same
阅读说明:本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 杜卫星 张玉龙 欧阳爵 张铭宏 于 2020-04-10 设计创作,主要内容包括:本公开提供一种半导体装置及其制造方法。所述半导体装置包含衬底、安置于所述衬底上的III-V族层、安置于所述III-V族层上的电介质层,以及从所述电介质层延伸到所述衬底的倾斜侧壁。其中所述衬底包括与所述倾斜侧壁相对地朝向的相对粗糙表面。(The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and sloped sidewalls extending from the dielectric layer to the substrate. Wherein the substrate comprises a relatively rough surface facing opposite the sloped sidewalls.)
1. A semiconductor device, comprising:
a substrate;
a III-V layer disposed on the substrate;
a dielectric layer disposed on the III-V layer; and
a sloped sidewall extending from the dielectric layer to the substrate, wherein the substrate comprises a relatively rough surface facing opposite the sloped sidewall.
2. The semiconductor device of claim 1, further comprising a passivation layer covering the sloped sidewalls, wherein the passivation layer comprises an uneven surface facing opposite the sloped sidewalls.
3. The semiconductor device of claim 1, further comprising a passivation layer covering the sloped sidewalls, wherein the passivation layer comprises a relatively smooth surface facing opposite the sloped sidewalls.
4. The semiconductor device of claim 1, wherein a surface of the substrate and the sloped sidewalls define a first angle, and wherein the first angle is in a range of 90 degrees to 150 degrees.
5. The semiconductor device of claim 2, wherein the passivation layer covers an interface between the substrate and the III-V layer.
6. The semiconductor device of claim 2, wherein the uneven surface of the passivation layer is adjacent to an interface between the substrate and the III-V layer.
7. The semiconductor device of claim 2, wherein the first surface of the passivation layer is not coplanar with an interface between the substrate and the III-V layer.
8. The semiconductor device of claim 1, wherein the first surface of the substrate is not coplanar with an interface between the substrate and the III-V layer.
9. The semiconductor device of claim 1, wherein the relatively rough surface of the substrate is oppositely facing an interface between the substrate and the III-V layer.
10. The semiconductor device of claim 2, wherein the uneven surface of the passivation layer is oriented opposite an interface between the substrate and the III-V layer.
11. A semiconductor structure, comprising:
a substrate;
a III-V layer disposed on the substrate;
a dielectric layer disposed on the III-V layer;
a first sidewall extending from the dielectric layer to the substrate; and
a second sidewall disposed opposite the first sidewall and extending from the dielectric layer into the substrate,
wherein the first sidewall and the second sidewall define a groove.
12. The semiconductor structure of claim 11, further comprising a passivation layer, wherein the passivation layer comprises a first portion and a second portion, the first portion covering the first sidewall and the second portion covering a portion of a surface of the substrate.
13. The semiconductor structure of claim 12, wherein the second portion of the passivation layer exposes a portion of a surface of the substrate.
14. The semiconductor structure of claim 12, wherein a first surface of the first portion is not coplanar with an interface between the substrate and the III-V layer.
15. The semiconductor structure of claim 12, wherein the first surface of the substrate is not coplanar with an interface between the substrate and the III-V layer.
16. The semiconductor structure of claim 12, the surface of the substrate and the first sidewall defining a first angle, wherein the first angle is in a range of 90 degrees to 150 degrees.
17. The semiconductor structure of claim 12, the passivation layer further comprising a third portion and a fourth portion, the third portion covering the second sidewall and the fourth portion covering a portion of the surface of the substrate.
18. The semiconductor structure of claim 17, wherein the second portion and the fourth portion define an opening that exposes a portion of the surface of the substrate.
19. A method for fabricating a semiconductor device, comprising:
providing a semiconductor structure having a substrate, a group III-V layer, and a dielectric layer;
forming a recess extending from the dielectric layer to the substrate;
forming a metal layer covering the dielectric layer and the groove;
forming a photoresist layer on the metal layer; and
performing a first photolithography process and a second photolithography process on the photoresist layer; wherein
The focus setting of the first lithography process is different from the focus setting of the second lithography process.
20. The method of claim 19, further comprising:
forming a patterned metal layer; and
forming a passivation layer overlying the patterned metal layer, wherein the passivation layer covers sidewalls of the recess and a portion of the surface of the substrate.
21. The method of claim 20, further comprising:
a singulation process is performed along the grooves, wherein the singulation process passes through the passivation layer.
22. The method of claim 20, wherein the focus setting of the first lithography process is selected according to a top of the groove.
23. The method of claim 20, wherein the focus setting of the second lithography process is selected according to a bottom of the groove.
Technical Field
The present disclosure relates to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices having group III-V layers.
Background
Semiconductor components that include direct bandgap semiconductor materials, such as group III-V materials or group III-V compounds (class: III-V compounds), can operate under a variety of conditions, such as at different voltages and frequencies, due to their properties.
The semiconductor device may include a Heterojunction Bipolar Transistor (HBT), a Heterojunction Field Effect Transistor (HFET), a High Electron Mobility Transistor (HEMT), a modulation-doped fet (modfet), and the like.
Gallium nitride (GaN) is a compound of nitrogen and gallium and is a III-V material that may be used to fabricate III-V semiconductor devices. III-V semiconductor devices may have better electronic properties in terms of saturated electron velocity, high electron mobility, etc.
Disclosure of Invention
In some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and sloped sidewalls extending from the dielectric layer to the substrate. Wherein the substrate comprises a relatively rough surface opposite the sloped sidewalls.
In some embodiments of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate; a III-V layer disposed on a substrate; and a dielectric layer disposed on the III-V layer. The semiconductor structure includes a first sidewall extending from a dielectric layer into a substrate; and a second sidewall disposed opposite the first sidewall and extending from the dielectric layer into the substrate, wherein the first sidewall and the second sidewall define a recess.
In some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes providing a semiconductor structure having a substrate, a III-V layer, and a dielectric layer. The method includes forming a recess extending from a dielectric layer to a substrate, and forming a metal layer overlying the dielectric layer and the recess. The method includes forming a photoresist layer on a metal layer. The method includes performing a first photolithography process and a second photolithography process on a photoresist layer. The focus setting of the first lithography process is different from the focus setting of the second lithography process.
Drawings
Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Figure 1A is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure.
Figure 1B is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure.
Figure 1C is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H illustrate methods of fabricating semiconductor structures according to some embodiments of the present disclosure.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I-1, and 2J-1 illustrate methods of fabricating semiconductor structures according to some embodiments of the present disclosure.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I-2, and 2J-2 illustrate methods of fabricating semiconductor structures according to some embodiments of the present disclosure.
Fig. 3A shows a simplified schematic diagram of a plan view of a portion of a wafer including a plurality of semiconductor devices and pre-cut trenches, in accordance with certain embodiments of the present disclosure.
Figure 3B is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure.
Figure 3C shows a portion of a semiconductor device, according to certain embodiments of the present disclosure.
Figure 3D shows a portion of a semiconductor device, according to certain embodiments of the present disclosure.
Figure 3E shows a portion of a semiconductor device, according to certain embodiments of the present disclosure.
Fig. 4A shows a simplified schematic diagram of a plan view of a portion of a wafer including a plurality of semiconductor devices and pre-cut trenches, according to certain comparative embodiments of the present disclosure.
Figure 4B is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain comparative embodiments of the present disclosure.
Figure 4C shows a portion of a semiconductor device, according to certain comparative embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, references in the following description to the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The particular embodiments discussed are merely illustrative and do not limit the scope of the disclosure.
Direct bandgap materials such as III-V compounds may include, but are not limited to, materials such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), aluminum gallium arsenide (InAlAs), and the like.
Figure 1A is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure.
Fig. 1A shows a
The III-V layers 12 and 14 may be disposed on the
III-V layers 12 and 14 may include, but are not limited to, for example, doped gallium nitride (doped GaN), doped aluminum gallium nitride (doped AlGaN), doped indium gallium nitride (doped InGaN), and other doped III-V compounds. The III-V layers 12 and 14 may include, but are not limited to, for example, p-type dopants, n-type dopants, or other dopants. In some embodiments, exemplary dopants may include, for example (but not limited to), magnesium (Mg), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), and the like.
The dielectric layers 16, 18, and 20 may comprise, but are not limited to, for example, an oxide or nitride, such as silicon nitride (SiN), silicon oxide (SiO2), and the like. The dielectric layers 16, 18 and 20 may comprise, for example, but not limited to, a composite layer of oxides and nitrides, such as Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2And the like.
In some embodiments, the
A
A
Referring to fig. 1A, a
The
The
Each of the interlayer connection elements 18v1, 18v2, 20v1, and 20v2 may be referred to as a through hole.
Referring to fig. 1A, a
Techniques that may be used to cut/saw the
The
The structure comprising the metal contact 18C1, the interlayer connection element 18v1, the metal contact 20C1, the interlayer connection element 20v1, and the
The structure comprising the metal contact 18C2, the interlayer connection element 18v2, the metal contact 20C2, the interlayer connection element 20v2, and the
A relatively thin portion (not shown in fig. 1A) below the
The relatively thin portion (not shown in fig. 1A) under the
The lattice mismatch between the
Figure 1B is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure.
Fig. 1B shows a semiconductor structure 100' in accordance with certain embodiments of the present disclosure. As shown in fig. 1B, semiconductor structure 100 'includes
The semiconductor structure 100' shown in fig. 1B is similar to the
Referring to fig. 1B, the passivation layer 24' includes a portion 24a disposed on the
The semiconductor structure 100' may be cut/sawed along the opening 24h 1. Cutting/sawing the semiconductor structure 100' along the opening 24h1 may provide a number of benefits. For example, the portion of the
Furthermore, cutting/sawing the semiconductor structure 100' along the opening 24h1 involves only cutting/sawing the
In some embodiments, the opening 24h1 may be utilized as an alignment mark during a pre-cutting procedure of the semiconductor structure 100'. In some embodiments, the openings 24h1 may increase the accuracy of the pre-cutting procedure. In some embodiments, the opening 24h1 may increase the speed of the pre-cutting procedure. In some embodiments, the openings 24h1 may improve the yield of the semiconductor structure 100'.
Reference is now made to the dotted circle a shown in fig. 1B. In some embodiments, portion 24a covers corner 100r of
Figure 1C is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure.
Fig. 1C shows a
The
The
The
The opening 24h2 exposes the
The
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H illustrate methods of fabricating semiconductor structures according to some embodiments of the present disclosure.
The operations shown in fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H may be used to produce a semiconductor structure similar to the
Referring to fig. 2A, a
Referring to fig. 2B, portions of
In some embodiments, the
An angle θ exists between the
In some embodiments, the angle θ is in the range of 90 degrees to 100 degrees. In some embodiments, the angle θ is in the range of 100 degrees to 110 degrees. In some embodiments, the angle θ is in the range of 110 degrees to 120 degrees. In some embodiments, the angle θ is in the range of 120 degrees to 130 degrees. In some embodiments, the angle θ is in the range of 130 degrees to 140 degrees. In some embodiments, the angle θ is in the range of 140 degrees to 150 degrees. In some embodiments, the angle θ is in the range of 90 degrees to 150 degrees.
Referring to fig. 2C, a
In some embodiments, the
Referring to fig. 2D, a
Referring to fig. 2E, a photolithography process is performed to remove certain portions of the
Among the portions 31a, 31b, 31c and 31d, the portions 31a and 31b are required, while the portions 31b and 31c should be removed.
If the portions 31b and 31c are not removed, the portions of the
The portions 31b and 31c may result from the focus setting of the lithographic apparatus used. That is, because the
To create a patterned photoresist layer extending from the top to the bottom of the groove, a two-step photolithography process is proposed (that is, the operations shown in fig. 2E and 2F).
Referring to fig. 2F, a photolithography process is performed to remove portions 31b and 31 c. The remaining portions 31a and 31d may be referred to as a
In some embodiments, the focus used in the operation shown in fig. 2E is selected according to the distance between the top of the
Referring to fig. 2G, a portion of the
Referring to fig. 2H, a
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I-1, and 2J-1 illustrate methods of fabricating semiconductor structures according to some embodiments of the present disclosure.
The operations shown in fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I-1, and 2J-1 may be used to produce a semiconductor structure similar to the
The operations shown in FIG. 2I-1 may be performed after the operations shown in FIG. 2H. Referring to fig. 2I-1, a patterned photoresist layer 32 is formed on the
The operations shown in FIG. 2J-1 may be performed after the operations shown in FIG. 2I-1. Referring to fig. 2J-1, a portion of
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I-2, and 2J-2 illustrate methods of fabricating semiconductor structures according to some embodiments of the present disclosure.
The operations shown in fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I-2, and 2J-2 may be used to produce a semiconductor structure similar to the
The operations shown in fig. 2I-2 may be performed after the operations shown in fig. 2H. Referring to fig. 2I-2, a patterned photoresist layer 32 is formed on the
The operations shown in fig. 2J-2 may be performed after the operations shown in fig. 2I-2. Referring to fig. 2J-2, a portion of the
Fig. 3A shows a simplified schematic diagram of a plan view of a portion of a wafer including a plurality of semiconductor devices and pre-cut trenches, in accordance with certain embodiments of the present disclosure.
Referring to fig. 3A, a wafer 40 includes semiconductor devices 42d1, 42d2, 42d3, and 42d 4. The semiconductor device 42d1 includes a seal ring 42s1 around the perimeter of the semiconductor device 42d 1. The semiconductor device 42d2 includes a seal ring 42s2 around the perimeter of the
The
In some embodiments, the
Figure 3B is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain embodiments of the present disclosure. The
Figure 3C shows a portion of a semiconductor device, according to certain embodiments of the present disclosure.
Fig. 3C shows a portion of a semiconductor device 42d 1. The semiconductor device 42d1 may be singulated from the wafer 40. In some embodiments, the semiconductor devices 42d1 may be singulated from the wafer 40 using a metal blade. In some embodiments, the semiconductor device 42d1 may be singulated from the wafer 40 using a water-cooled circular saw with diamond tines.
Referring to dotted circle B shown in fig. 3C, the upper surface 24s of the
Referring again to the dotted circle B shown in fig. 3C, a blade or saw used to singulate the semiconductor devices 42d1 may pass through the
As shown in dotted circle B, the
The
Figure 3D shows a portion of a semiconductor device, according to certain embodiments of the present disclosure. Fig. 3D shows a portion of a semiconductor device 42D 1'. The semiconductor device 42d1' may be singulated from the wafer 40.
Referring to the dotted circle C shown in fig. 3D, a blade or saw used to divide the semiconductor device 42D1' introduces an uneven edge to the
As shown in dotted circle C, the
The
Figure 3E shows a portion of a semiconductor device, according to certain embodiments of the present disclosure. Fig. 3E shows a portion of the semiconductor device 42d1 ". The semiconductor device 42d1 "may be singulated from the wafer 40.
Referring to the dotted circle D shown in fig. 3E, a blade or saw used to divide the semiconductor device 42D1' may introduce uneven edges to the
Fig. 4A shows a simplified schematic diagram of a plan view of a portion of a wafer including a plurality of semiconductor devices and pre-cut trenches, according to certain comparative embodiments of the present disclosure.
Referring to fig. 4A, a wafer 60 includes semiconductor devices 62d1, 62d2, 62d3, and 62d 4. The semiconductor device 62d1 includes a seal ring 62s1 around the perimeter of the semiconductor device 62d 1. The semiconductor device 62d2 includes a seal ring 62s2 around the perimeter of the
The groove 62t1 surrounds the periphery of the seal ring 62s 1. The groove 62t2 surrounds the periphery of the
Figure 4B is a simplified schematic cross-sectional view of a portion of a semiconductor wafer, according to certain comparative embodiments of the present disclosure.
Fig. 4B shows a
Referring to
Referring to both fig. 4A and 4B, the groove 62t1 shown in fig. 4A may correspond to the groove 200t1 shown in fig. 4B. The groove 62t3 shown in fig. 4A may correspond to the groove 200t2 shown in fig. 4B. The seal rings 62s1 and 62s3 shown in fig. 4A may correspond to the
In some embodiments, grooves 200t1,
Due to the widths of groove 200t1,
Figure 4C shows a portion of a semiconductor device, according to certain comparative embodiments of the present disclosure.
Fig. 4C shows a portion of the semiconductor device 62d 1. The semiconductor device 62d1 may be singulated from the wafer 60. In some embodiments, the semiconductor devices 62d1 may be singulated from the wafer 60 using a blade, saw, or laser. Referring to fig. 4C, the semiconductor device 62d1 includes a groove 200t 1. The
As used herein, spatial relationship terms, such as "below," "lower," "above," "upper," "lower," "left," "right," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as shown in the figures. The spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as well. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
As used herein, the terms "approximately," "substantially," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to the exact occurrence of the event or circumstance as well as the fact that the event or circumstance occurs in close proximity. As used herein with respect to a given value or range, the term "about" generally means within ± 10%, ± 5%, ± 1%, or ± 0.5% of the given value or range. Ranges may be expressed herein as from one end point to the other end point or between the two end points. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints. The term "substantially coplanar" may refer to two surfaces located within a few micrometers (μm) along the same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm located along the same plane. When referring to "substantially" the same numerical value or property, the term can refer to a value that is within ± 10%, ± 5%, ± 1%, or ± 0.5% of the mean of the stated values.
The foregoing has outlined features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the present disclosure.