阅读说明：本技术 覆晶薄膜封装结构及显示装置 (Chip on film package structure and display device ) 是由 傅晓立 于 2020-05-08 设计创作，主要内容包括：本申请公开一种覆晶薄膜封装结构及显示装置,所述覆晶薄膜封装结构包括柔性基板,所述柔性基板具有相对的第一表面以及第二表面,所述第一表面上设置有多个第一信号引脚以及覆盖所述第一信号引脚的第一保护层；散热层,所述散热层设置在所述第二表面上；芯片,所述芯片设置在所述第一保护层上,所述芯片上设置有多个输出引脚和至少一虚拟引脚；其中,所述输出引脚和所述第一信号引脚一一对应连接,所述虚拟引脚通过贯穿所述第一保护层和所述柔性基板的过孔与所述散热层连接。该方案能够有效的散热,进而降低覆晶薄膜封装结构的温度。(The application discloses a chip on film packaging structure and a display device, wherein the chip on film packaging structure comprises a flexible substrate, the flexible substrate is provided with a first surface and a second surface which are opposite, and a plurality of first signal pins and a first protection layer covering the first signal pins are arranged on the first surface; a heat dissipation layer disposed on the second surface; the chip is arranged on the first protective layer, and a plurality of output pins and at least one virtual pin are arranged on the chip; the output pins are connected with the first signal pins in a one-to-one correspondence mode, and the virtual pins are connected with the heat dissipation layer through via holes penetrating through the first protective layer and the flexible substrate. The scheme can effectively dissipate heat, and further reduce the temperature of the chip on film packaging structure.)

1. A chip on film package structure, comprising:

the flexible substrate is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of first signal pins and a first protective layer which covers the first signal pins;

a heat dissipation layer disposed on the second surface;

the chip is arranged on the first protective layer, and a plurality of output pins and at least one virtual pin are arranged on the chip; wherein the content of the first and second substances,

the output pins are connected with the first signal pins in a one-to-one correspondence mode, and the virtual pins are connected with the heat dissipation layer through via holes penetrating through the first protective layer and the flexible substrate.

2. The chip on film package structure of claim 1, wherein the heat spreading layer extends to the via and is connected to the dummy pin.

3. The chip on film package structure of claim 1, wherein the via hole is disposed therein with a thermal conductive block, and the dummy pin is connected to the heat sink layer through the thermal conductive block.

4. The chip on film package structure of claim 1, wherein the heat dissipation layer is disposed corresponding to the chip, and a projection of the heat dissipation layer on the flexible substrate coincides with a projection of the chip on the flexible substrate.

5. The chip on film package structure of claim 1, wherein the heat dissipation layer completely covers the second surface.

6. The chip on film package structure of claim 1, wherein the heat dissipation layer is formed on the second surface by deposition and etching.

7. The chip on film package structure of claim 1, wherein a plurality of second signal pins and a second passivation layer covering the second signal pins are disposed on the second surface;

the output pins comprise a first output pin and a second output pin, the first output pin is connected with the corresponding first signal pin, and the second output pin is connected with the corresponding second signal pin.

8. The chip on film package structure of claim 7, wherein the projection of the heat dissipation layer on the flexible substrate and the projection of the second passivation layer on the flexible substrate are staggered.

9. The chip on film package structure of claim 8, wherein the heat spreading layer and the second signal pin are formed by the same process.

10. A display device comprising the chip on film package structure according to any one of claims 1 to 9.

Technical Field

The application relates to the technical field of display, in particular to a chip on film packaging structure and a display device.

Background

Chip On Film (COF) packaging generally refers to bonding a chip to a substrate through a metal conductor in an active-surface-down manner after the chip is turned over. When the flexible substrate is applied, the chip can be fixed on the film and is electrically connected with the flexible substrate only by the metal conductor. As electronic products are being developed to have features such as miniaturization, high speed, and high pin count, the packaging technology of chips is being developed, and the driving chips on the display screen are no exception.

However, as the image quality of the display screen is required to be higher and higher by the terminal customer, the resolution of the display screen is also higher and higher, and the higher the resolution is, the more the output channels of the chip are, the higher the response power consumption is, and the increase of the power consumption is usually accompanied by the increase of the temperature of the flip-chip package structure, so that the problem of the too high temperature of the flip-chip package structure often occurs.

Disclosure of Invention

The embodiment of the application provides a chip on film package structure and a display device, so as to solve the technical problem of over-high temperature of the chip on film package structure.

The application provides a chip on film packaging structure, it includes:

the flexible substrate is provided with a first surface and a second surface which are opposite, and the first surface is provided with a plurality of first signal pins and a first protective layer which covers the first signal pins;

a heat dissipation layer disposed on the second surface;

the chip is arranged on the first protective layer, and a plurality of output pins and at least one virtual pin are arranged on the chip; wherein the content of the first and second substances,

the output pins are connected with the first signal pins in a one-to-one correspondence mode, and the virtual pins are connected with the heat dissipation layer through via holes penetrating through the first protective layer and the flexible substrate.

In the chip on film package structure provided by the present application, the heat dissipation layer extends to the via hole and is connected to the dummy pin.

In the chip on film packaging structure provided by the application, the through hole is provided with the heat conduction block, and the virtual pin is connected with the heat dissipation layer through the heat conduction block.

In the chip on film package structure provided by the application, the heat dissipation layer corresponds to the chip, and the projection of the heat dissipation layer on the flexible substrate coincides with the projection of the chip on the flexible substrate.

In the chip on film package structure provided by the present application, the heat dissipation layer completely covers the second surface.

In the chip on film package structure provided by the application, the heat dissipation layer is formed on the second surface in a deposition and etching manner.

In the chip on film package structure provided by the present application, a plurality of second signal pins and a second protection layer covering the second signal pins are disposed on the second surface;

the output pins comprise a first output pin and a second output pin, the first output pin is connected with the corresponding first signal pin, and the second output pin is connected with the corresponding second signal pin.

In the chip on film package structure provided by the application, the projection of the heat dissipation layer on the flexible substrate and the projection of the second protection layer on the flexible substrate are arranged in a staggered manner.

In the chip on film package structure provided by the present application, the heat dissipation layer and the second signal pin are formed by the same process.

Correspondingly, the application also provides a display device which comprises the chip on film packaging structure.

The application provides a chip on film packaging structure and display device, and this chip on film packaging structure sets up the heat dissipation layer through keeping away from the second surface of chip at flexible substrate to be connected at least a virtual pin of chip and this heat dissipation layer, increase the heat dissipation route of chip, can effectual heat dissipation, thereby reduce chip on film packaging structure's temperature.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a first structural schematic diagram of a chip on film package structure according to an embodiment of the present disclosure;

fig. 2 is a second structural schematic diagram of a chip on film package structure according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a third structure of a chip on film package structure according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second", etc. may explicitly or implicitly include one or more of the described features and are therefore not to be construed as limiting the application.

Referring to fig. 1, fig. 1 is a first structural schematic diagram of a chip on film package structure according to an embodiment of the present disclosure. As shown in fig. 1, the chip on film package structure 100 includes a flexible substrate 10, a chip 20 and a heat dissipation layer 30. The flexible substrate 10 has a first surface 101 and a second surface 102 opposite to each other; the first surface 101 is provided with a plurality of first signal pins 11 and a first protective layer 12 covering the first signal pins 11. The heat dissipation layer 30 is disposed on the second surface 102. The chip 20 is disposed on the first protective layer 12. The chip 20 is provided with a plurality of output pins 21 and at least one dummy pin 22. The output pins 21 are connected with the first signal pins 11 in a one-to-one correspondence manner; the dummy leads 22 are connected to the heat dissipation layer 30 through vias 120 that penetrate the first protective layer 12 and the flexible substrate 10.

The material of the flexible substrate 10 may be any one of polyimide, polyester, polysulfone, and polytetrafluoroethylene. Due to the thin thickness of the flexible substrate 10, heat generated by the chip 20 during operation can be diffused to the heat dissipation layer 30 through the flexible substrate 10.

One side of the chip 20, on which the plurality of output pins 21 and the at least one dummy pin 22 are disposed, faces the flexible substrate 10. The first passivation layer 12 is formed on the first signal leads 11 for protecting the whole circuit structure and ensuring the insulation between the first signal leads 11. The first protective layer 12 may be a green paint protective layer. In addition, in practical applications, the peripheries of the output pins 21 and the dummy pins 22 may be filled with an insulating material to fix the chip 20 and further provide an insulating function. In practical applications, the chip 20 may be a driving chip of a liquid crystal display, and is used to drive the liquid crystal molecules of the liquid crystal display panel to rotate by an angle, which is not particularly limited in this application.

The material of the first signal pin 11, the output pin 21 and the dummy pin 22 may be metal or alloy with good conductivity, such as copper, aluminum and indium tin oxide. The material of the heat dissipation layer 30 may be a metal having good heat dissipation properties, such as copper, aluminum, or silver. The first signal pin 11, the output pin 21, the dummy pin 22, and the heat dissipation layer 30 may be made of the same material or different materials, which is not particularly limited in this application. In addition, since metals such as copper and aluminum have heat dissipation properties, the heat dissipation path of the chip 20 is increased by connecting the dummy pins 22 and the heat dissipation layer 30, and the heat dissipation efficiency is improved.

Further, in the embodiment of the present application, the size of the dummy pin 22 may be larger than that of the output pin 21, so as to increase the heat dissipation area, which is beneficial to heat dissipation of the chip 20. In addition, the dummy pins 22 may be alternatively disposed between the output pins 21, or disposed on the periphery of the output pins 21, which is not limited in the present application.

The chip on film package structure 100 provided in the embodiment of the application is configured with the heat dissipation layer 30 on the second surface 102 of the flexible substrate 10, and connects at least one dummy pin 22 of the chip 20 with the heat dissipation layer 30 through the via 120 penetrating through the first protection layer 12 and the flexible substrate 10, so as to increase the heat dissipation path of the chip 20, so that the chip 20 dissipates heat through the dummy pin 22 and the heat dissipation layer 30 during operation, thereby effectively reducing the temperature of the chip on film, and alleviating the problem of the chip on film having an excessively high temperature in the prior art.

In some embodiments, with continued reference to fig. 1, the heat spreading layer 30 may extend to the vias 120 and connect to the dummy leads 22. In other embodiments, a heat conducting block or a heat conducting material filled with carbon particles or the like may be disposed in the via 120, and the dummy pin 22 is connected to the heat dissipation layer 30 through the heat conducting block or the heat conducting material. The scheme can ensure sufficient contact between the virtual pins 22 and the heat dissipation layer, and improves the heat dissipation effect.

In addition, in the embodiment of the present application, the heat dissipation layer 30 may be formed on the second surface 102 of the flexible substrate 10 by deposition etching. Compared with the process of adhering the heat dissipation layer 30 to the second surface 102 by using a double-sided adhesive tape in the prior art, the heat dissipation layer 30 is directly formed on the second surface 102 by using a deposition and etching process, so that the double-sided adhesive tape is omitted, the overall thickness of the chip on film packaging structure 100 is reduced, and the heat dissipation effect is better.

It should be noted that the distribution of the heat dissipation layer 30 on the second surface 102 can be set according to actual requirements. For example, referring to fig. 1, in some embodiments, the heat dissipation layer 30 may completely cover the second surface 102, so as to increase a contact area between the heat dissipation layer 30 and the flexible substrate 10, thereby performing a uniform heat dissipation function, further improving a heat dissipation effect, and reducing a temperature of the chip on film package structure 100.

For another example, please refer to fig. 2, fig. 2 is a second structural schematic diagram of the chip on film package structure according to the embodiment of the present disclosure. As shown in fig. 2, the difference from the chip-on-film package structure 100 in fig. 1 is that, in the chip-on-film package structure 200 provided in the embodiment of the present application, the heat dissipation layer 30 is disposed corresponding to the chip 20, and a projection of the heat dissipation layer 30 on the flexible substrate 10 coincides with a projection of the chip 20 on the flexible substrate 10. It can be understood that, in the chip on film package structure 200, the main heat is generated by the chip 20 during operation, and therefore, the heat dissipation layer 30 is disposed corresponding to the chip 20, so as to achieve the purposes of saving material and reducing the weight of the chip on film package structure 200 while ensuring that the heat generated by the chip 20 can be effectively dissipated.

Referring to fig. 3, fig. 3 is a third structural schematic diagram of a chip on film package structure according to an embodiment of the present disclosure. As shown in fig. 3, in the chip on film package structure 300 provided in the embodiment of the present disclosure, a plurality of second signal pins 13 and a second passivation layer 14 covering the second signal pins 13 are disposed on the second surface 102 of the flexible substrate 10. The output pin 21 includes a first output pin 211 and a second output pin 212. The first output pins 211 are connected to the corresponding first signal pins 11. The second output pins 212 are connected to the corresponding second signal pins 13.

The second signal pin 13 and the first signal pin 11 are made of the same material, and may be made of metal or alloy with good conductivity, such as copper, aluminum, and indium tin oxide. The first output pin 211 and the second output pin 212 have the same specification and are used for outputting signals. The first signal pin 11 and the second signal pin 13 have the same specification and are used for receiving signals respectively output by the first output pin 211 and the second output pin 212. Different from the above, the second signal pins 13 are disposed on the second surface 102 of the flexible substrate 10, such that the second signal pins 13 are disposed outside the chip on film package structure 300, and heat generated by the chip 20 during operation can be transmitted to the second signal pins 13 through the second output pins 212, and then dissipated from the chip on film package structure 300. And the second output pins 212 are numerous and many-point-and-multiple-surface wide. The plurality of second output pins 212 have a large heat transfer area as a whole, and have a fast heat transfer rate. When the chip 20 is in operation, heat can be rapidly conducted through the second output pins 212 and the dummy pins 22 without accumulating heat.

In addition, since the chip 20 outputs signals through the first output pin 211 and the second output pin 212, the signals can be divided into two groups in time for transmission in a staggered manner, so that energy can be dispersed, and the temperature of the chip on film package structure 300 can be further reduced. It should be noted that the number of the first output pins 211 and the second output pins 212 may be the same or different, and this is not specifically limited in this application.

It should be noted that the second transmission pins 212 are also connected to the second signal pins 13 through via holes (not labeled in the figures) penetrating through the first protective layer 12 and the flexible substrate 10, and specific reference may be made to the above description of the connection manner of the dummy pins 22 and the heat dissipation layer 30, which is not described herein again.

In the embodiment of the present application, the projection of the heat dissipation layer 30 on the flexible substrate 10 and the projection of the second protective layer 14 on the flexible substrate 10 are staggered. Specifically, the heat dissipation layer 30 and the second signal pins 13 are disposed on the second surface 102. The heat dissipation layer 30 is disposed around the periphery of the second signal pin 13. When the second signal pin 13 dissipates the heat generated by the second transmission pin 212, the heat dissipation layer 30 can further dissipate the heat at other positions of the chip on film package 300.

It should be noted that, in some embodiments, the heat dissipation layer 30 may contact the second protection layer 14, so as to conduct the heat dissipated by the second signal pin 13.

Further, the heat dissipation layer 30 and the second signal pin 13 are formed by the same process. Specifically, a metal layer is deposited on the second surface 12 of the flexible substrate 10, and the heat dissipation layer 30 and the second signal pins 13 are simultaneously formed through an etching process.

Correspondingly, the present application further provides a display device, which includes the chip on film package structure according to any of the above embodiments. The embodiments of the present application are not described herein again.

The embodiment of the application provides a display device, which comprises a chip on film packaging structure, wherein the chip on film packaging structure is provided with a heat dissipation layer through one side surface of a flexible substrate far away from a chip, and at least one virtual pin of the chip is connected with the heat dissipation layer, so that the heat dissipation path of the chip is increased, the temperature of the chip on film is effectively reduced, and the problem of overhigh temperature of the existing chip on film is solved.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.