阅读说明：本技术 半导体装置以及半导体装置的制造方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 小川翔平 藤野纯司 石川悟 重本拓巳 石山祐介 于 2018-11-29 设计创作，主要内容包括：具备：绝缘基板(1),陶瓷基材(1b)和冷却用翼片(1a)成为一体；板状的布线部件(5)；以及半导体元件(3a),一面经由芯片下焊料(4)接合到绝缘基板(1)的陶瓷基材(1b)侧,另一面以使多个板状的布线部件(5)分别对应的方式经由芯片上焊料(6)接合到多个板状的布线部件(5),芯片下焊料(4)以及芯片上焊料(6)都包含0.3wt％以上且3wt％以下Ag、包含0.5wt％以上且1wt％以下Cu、以Sn为主成分,不会损害散热性而实现小型化。(The disclosed device is provided with: an insulating substrate (1) in which a ceramic base (1b) and a cooling fin (1a) are integrated; a plate-like wiring member (5); and a semiconductor element (3a) having one surface bonded to the ceramic base material (1b) side of the insulating substrate (1) via an under-chip solder (4) and the other surface bonded to the plurality of plate-like wiring members (5) via an on-chip solder (6) so that the plurality of plate-like wiring members (5) correspond to each other, wherein the under-chip solder (4) and the on-chip solder (6) each contain 0.3 wt% to 3 wt% Ag and 0.5 wt% to 1 wt% Cu, and contain Sn as a main component, thereby achieving miniaturization without impairing heat dissipation.)

1. A semiconductor device is characterized by comprising:

the base plate, the insulating member and the cooling fin are integrated;

a plate-like wiring member; and

a semiconductor element having a back surface side bonded to a wiring pattern side of the insulating member of the substrate via a first solder and a front surface side bonded to the planar wiring member via a second solder so as to correspond to the planar wiring member,

the first solder contains 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu, and Sn as a main component.

2. The semiconductor device according to claim 1,

the second solder contains 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu, and Sn as a main component.

3. The semiconductor device according to claim 1 or 2,

the substrate includes a metal film provided on the wiring pattern side of the insulating member and bonded to the back surface side of the semiconductor element via the first solder, the semiconductor element includes a metal film provided on the back surface side of the semiconductor element and bonded to the insulating member via the first solder, and at least one of the metal film provided on the back surface side of the semiconductor element and the metal film provided on the wiring pattern side of the substrate is made of Ag or Cu.

4. The semiconductor device according to claim 2 or 3,

the semiconductor device is provided with a metal film on the front surface side thereof, the metal film being bonded to the planar wiring member via the second solder, and the metal film provided on the front surface side of the semiconductor device is made of Ag or Cu.

5. The semiconductor device according to claim 1 or 2,

when an Al metal film is provided on the back surface side of the semiconductor element, the first solder contains 0.3 wt% to 2 wt% Ag, 0.5 wt% to 1 wt% Cu, and Sn as a main component.

6. The semiconductor device according to claim 5,

when an Al metal film is provided on the front surface side of the semiconductor element, the second solder contains 0.3 wt% to 2 wt% Ag, 0.5 wt% to 1 wt% Cu, and Sn as a main component.

7. The semiconductor device according to any one of claims 1 to 6,

the substrate and the semiconductor element are bonded with a spacer interposed therebetween.

8. The semiconductor device according to any one of claims 1 to 7,

the semiconductor device includes a plurality of semiconductor elements and a plurality of plate-like wiring members corresponding to the plurality of semiconductor elements, and a first plate-like wiring member and a second plate-like wiring member as the plurality of wiring members are connected to each other by a connecting member made of resin.

9. The semiconductor device according to any one of claims 1 to 8,

in the base plate, the insulating member and the cooling fin are integrated by casting.

10. The semiconductor device according to any one of claims 1 to 9,

in the substrate, the insulating member and the cooling fin are integrated by brazing.

11. The semiconductor device according to any one of claims 1 to 10,

the semiconductor element is formed of a wide band gap semiconductor material, which is any of silicon carbide, a gallium nitride-based material, and diamond.

12. A method for manufacturing a semiconductor device, comprising:

bonding the back surface side of the semiconductor element to the wiring pattern side of the insulating member of the substrate integrated with the insulating member and the cooling fin by first reflow soldering via a first solder; and

a step of bonding the front surface side of the semiconductor element and the planar wiring member by a second reflow soldering via a second solder so that the planar wiring member corresponds to the semiconductor element,

the first solder contains 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu, and Sn as a main component.

13. The method for manufacturing a semiconductor device according to claim 12,

the second solder contains 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu, and Sn as a main component.

14. The method for manufacturing a semiconductor device according to claim 12 or 13,

when an Al metal film is provided on the back surface side of the semiconductor element, the first solder contains 0.3 wt% to 2 wt% of Ag, 0.5 wt% to 1 wt% of Cu, and Sn as a main component.

15. The method for manufacturing a semiconductor device according to claim 14,

when an Al metal film is provided on the front surface side of the semiconductor element, the second solder contains 0.3 wt% to 2 wt% Ag, 0.5 wt% to 1 wt% Cu, and Sn as a main component.

16. A method for manufacturing a semiconductor device, comprising:

a step of bonding a metal film formed on the back surface side of a semiconductor element and a metal film provided on the wiring pattern side of an insulating member of a substrate in which the insulating member and a cooling fin are integrated, by first reflow soldering via a first solder; and

a step of bonding the metal film formed on the front surface side of the semiconductor element and the planar wiring member by a second reflow soldering via a second solder so that the planar wiring member corresponds to the semiconductor element,

in the step of bonding via the first solder, a solder containing 0.5 wt% or more and 1 wt% or less of Cu and having Sn as a main component is used as the first solder, and at least one of a metal film formed on a back surface side of the semiconductor element and a metal film on a front surface side of an electrode pattern provided on a wiring pattern side of an insulating member of the substrate is made of Ag, and the first solder is made of a solder containing 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu and having Sn as a main component by first reflow.

17. A method for manufacturing a semiconductor device, comprising:

a step of bonding a metal film formed on the back surface side of the semiconductor element and a metal film on the front surface side of an electrode pattern provided on the wiring pattern side of an insulating member of a substrate in which the insulating member and the cooling fin are integrated, by first reflow soldering via a first solder; and

a step of bonding the metal film formed on the front surface side of the semiconductor element and the planar wiring member by a second reflow soldering via a second solder so that the planar wiring member corresponds to the semiconductor element,

in the step of bonding via the first solder, a solder containing 0.3 wt% or more and 3 wt% or less of Ag and having Sn as a main component is used as the first solder, and at least one of a metal film formed on a back surface side of the semiconductor element and a metal film on a front surface side of an electrode pattern provided on a wiring pattern side of an insulating member of the substrate is made of Cu, so that the first solder is made of a solder containing 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu and having Sn as a main component by first reflow.

18. The method for manufacturing a semiconductor device according to any one of claims 12 to 17,

the semiconductor device includes a plurality of semiconductor elements and a plurality of plate-like wiring members corresponding to the plurality of semiconductor elements, and a first plate-like wiring member and a second plate-like wiring member as the plurality of wiring members are connected to each other by a connecting member made of resin.

19. The method for manufacturing a semiconductor device according to any one of claims 12 to 18,

the step of bonding by the first solder and the step of bonding by the second solder are performed simultaneously.

20. The method for manufacturing a semiconductor device according to any one of claims 12 to 19,

the step of bonding via the first solder is performed simultaneously with the step of bonding the case to the substrate.

21. The method for manufacturing a semiconductor device according to any one of claims 12 to 20,

in the step of bonding via the second solder, bonding is performed by spot heating using a laser instead of the second reflow soldering.

Technical Field

The present invention relates to a semiconductor device having a structure in which a planar wiring member is bonded to a chip, and a method for manufacturing the semiconductor device.

Background

In a power semiconductor device, a chip is directly soldered to an insulating substrate integrated with fins for cooling, thereby reducing thermal resistance. Further, the module is miniaturized by adopting a structure in which wires are not wire-bonded but wire-bonded to the wiring on the chip.

Patent document 1 discloses a module including: by mounting the chip on the insulating substrate integrated with the cooling fin, thermal resistance can be reduced and miniaturization can be achieved as compared with the case where the substrate and the fin are brought into contact with each other through grease. Patent documents 1 and 2 disclose modules that include: by providing the wiring on the chip with a structure in which a plate-like wiring member is soldered, the current density can be increased and the size can be reduced as compared with the case of wire bonding. Patent documents 2 and 3 disclose modules that include: sn — Ag — Cu solder is used for bonding a chip to a substrate and a chip to a wire.

Disclosure of Invention

In the case of using the structures of patent documents 1 to 3, when the chip is soldered to the insulating substrate, the heat capacity increases due to the cooling fins, and the contact area with the cooling plate decreases due to the fins, so that the cooling rate is reduced as compared with the case of a flat plate, and there are cases where a void such as a sink hole is generated in the solder between the chip and the insulating substrate integrated with the cooling fins, and when the void is present, the heat dissipation is impaired.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can be miniaturized without impairing heat dissipation.

The disclosed semiconductor device is characterized by being provided with: the base plate, the insulating member and the cooling fin are integrated; a plate-like wiring member; and a semiconductor element, a back side of which is bonded to a wiring pattern side of the insulating member of the substrate via a first solder, and a front side of which is bonded to the planar wiring member via a second solder so as to correspond to the planar wiring member, wherein the first solder contains 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu, and contains Sn as a main component.

The method for manufacturing a semiconductor device disclosed in the present application is characterized by comprising: bonding the back surface side of the semiconductor element to the wiring pattern side of the insulating member of the substrate integrated with the insulating member and the cooling fin by first reflow soldering via a first solder; and a step of bonding the front surface side of the semiconductor element and the plate-like wiring member by a second reflow soldering via a second solder so that the plate-like wiring member corresponds to the semiconductor element, wherein the first solder contains 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu, and contains Sn as a main component.

Further, a method for manufacturing a semiconductor device disclosed in the present application is characterized by including: a step of bonding a metal film formed on the back surface side of a semiconductor element and a metal film provided on the wiring pattern side of an insulating member of a substrate in which the insulating member and a cooling fin are integrated, by first reflow soldering via a first solder; and a step of bonding a metal film formed on a front surface side of the semiconductor element and a planar wiring member by a second reflow soldering via a second solder so that the planar wiring member corresponds to the semiconductor element, wherein in the step of bonding via the first solder, a solder containing 0.5 wt% or more and 1 wt% or less of Cu and containing Sn as a main component is used as the first solder, and the first solder is made of Ag by setting at least one of the metal film formed on a back surface side of the semiconductor element and the metal film on a front surface side of an electrode pattern provided on a wiring pattern side of an insulating member of the substrate, and is made of a solder containing 0.3 wt% or more and 3 wt% or less of Ag and containing 0.5 wt% or more and 1 wt% or less of Cu and containing Sn as a main component by the first reflow soldering.

Further, a method for manufacturing a semiconductor device disclosed in the present application is characterized by including: a step of bonding a metal film formed on the back surface side of the semiconductor element and a metal film on the front surface side of an electrode pattern provided on the wiring pattern side of an insulating member of a substrate in which the insulating member and the cooling fin are integrated, by first reflow soldering via a first solder; and a step of bonding a metal film formed on a front surface side of the semiconductor element and a planar wiring member by a second reflow soldering via a second solder so that the planar wiring member corresponds to the semiconductor element, wherein in the step of bonding via the first solder, a solder containing 0.3 wt% or more and 3 wt% or less of Ag and containing Sn as a main component is used as the first solder, and the first solder is made of Cu by setting at least one of the metal film formed on a back surface side of the semiconductor element and the metal film on a front surface side of an electrode pattern provided on a wiring pattern side of an insulating member of the substrate, and is made of a solder containing 0.3 wt% or more and 3 wt% or less of Ag, containing 0.5 wt% or more and 1 wt% or less of Cu and containing Sn as a main component by the first reflow soldering.

According to the present application, by using a solder containing 0.3 wt% or more and 3 wt% or less of Ag, 0.5 wt% or more and 1 wt% or less of Cu, and Sn as a main component for bonding a semiconductor element, shrinkage cavities can be suppressed, and miniaturization can be achieved without impairing heat dissipation properties.

Drawings

Fig. 1 is a schematic plan view showing a configuration of a main part of a semiconductor device according to embodiment 1.

Fig. 2 is a schematic cross-sectional view showing a configuration of a main part of the semiconductor device according to embodiment 1.

Fig. 3 is a schematic cross-sectional view showing a structure of a chip in the semiconductor device according to embodiment 1.

Fig. 4 is a schematic plan view showing a state of a crater in solder in a conventional semiconductor device.

Fig. 5 is a diagram for explaining the composition of solder used in the semiconductor device according to embodiment 1.

Fig. 6 is a flowchart showing a state in which a solder composition other than the composition of the solder used in the semiconductor device according to embodiment 1 is used.

Fig. 7 is a flowchart showing a state in which a solder composition other than the composition of the solder used in the semiconductor device according to embodiment 1 is used.

Fig. 8 is a flowchart showing a state in which a solder composition other than the composition of the solder used in the semiconductor device according to embodiment 1 is used.

Fig. 9 is a flowchart showing a state in which a solder composition other than the composition of the solder used in the semiconductor device according to embodiment 1 is used.

Fig. 10 is a diagram illustrating a relationship between the Cu concentration and the thickness of the alloy layer in a state where a solder composition other than the composition of the solder used in the semiconductor device according to embodiment 1 is used.

Fig. 11 is a binary state diagram of Sn — Cu solder for explaining the composition of solder used in the semiconductor device according to embodiment 1.

Fig. 12 is a graph showing a relationship between vickers hardness and temperature of Ni plating for explaining a composition of solder used in the semiconductor device according to embodiment 1.

Fig. 13 is a ternary state diagram of Sn — Ag — Cu solder for explaining the composition of solder used in the semiconductor device according to embodiment 1.

Fig. 14 is a diagram for explaining a state of shrinkage cavities based on the concentration of Ag in the solder in the semiconductor device according to embodiment 1.

Fig. 15 is a diagram for explaining a state of main strain based on the concentration of Ag in the metal film in the semiconductor device according to embodiment 1.

Fig. 16 is a schematic sectional view showing a manufacturing process of a semiconductor device according to embodiment 1.

Fig. 17 is a schematic plan view and a schematic cross-sectional view showing another configuration of a main part of the semiconductor device according to embodiment 1.

Fig. 18 is a schematic plan view and a schematic cross-sectional view showing another configuration of a main part of the semiconductor device according to embodiment 1.

Fig. 19 is a schematic plan view showing a configuration of a main part of the semiconductor device according to embodiment 3.

Fig. 20 is a schematic cross-sectional view showing a configuration of a main part of a semiconductor device according to embodiment 3.

(symbol description)

1: an insulating substrate; 1 a: a cooling fin; 1 b: a ceramic substrate; 1 c: an electrode pattern; 1 d: a metal film; 2: a spacer; 3: a chip; 3 a: a semiconductor element; 3b, 3c, 3 d: a metal film; 4: under-chip solder; 5: a wiring member; 6: solder on a chip; 10: a corrosion inhibitor; 101. 102, 103: a semiconductor device is provided.

Detailed Description