阅读说明：本技术 扇出封装结构 (Fan-out packaging structure ) 是由 林耀剑 于 2020-04-17 设计创作，主要内容包括：本发明揭示了一种扇出封装结构,包括：重布线层,设置于重布线层下方的焊球,电性连接所述重布线层上方的高热芯片和低热芯片,以及填充设置于重布线层上方且包覆所述高热芯片、低热芯片的塑封料；所述高热芯片上表面裸露至所述塑封料之外,所述低热芯片的上表面包封于所述塑封料之中；于所述低热芯片的上表面设置翘曲调节保护层；或于所述低热芯片正上方的塑封料开设至少一个通孔,且所述低热芯片的部分上表面透过所述通孔曝露于所述塑封料之外。本发明通过在低热芯片的上表面设置翘曲调节保护层,或通过于所述低热芯片上方的塑封料开设至少一个通孔,增加对整个扇出封装结构的翘曲调节能力；使扇出封装结构的良率及稳定度均得到大幅提升。(The invention discloses a fan-out packaging structure, which comprises: the redistribution layer is arranged below the redistribution layer, the solder balls are electrically connected with the high-heat chip and the low-heat chip above the redistribution layer, and the plastic packaging material which is filled above the redistribution layer and coats the high-heat chip and the low-heat chip is filled above the redistribution layer; the upper surface of the high-heat chip is exposed out of the plastic package material, and the upper surface of the low-heat chip is encapsulated in the plastic package material; arranging a warpage adjusting protective layer on the upper surface of the low-heat chip; or at least one through hole is formed in the plastic packaging material right above the low-heat chip, and part of the upper surface of the low-heat chip is exposed out of the plastic packaging material through the through hole. According to the invention, the warpage adjusting protective layer is arranged on the upper surface of the low-heat chip, or at least one through hole is formed in the plastic package material above the low-heat chip, so that the warpage adjusting capability of the whole fan-out packaging structure is improved; the yield and the stability of the fan-out packaging structure are greatly improved.)

1. A fan-out package structure, comprising: the redistribution layer is arranged below the redistribution layer, the solder balls are electrically connected with the high-heat chip and the low-heat chip above the redistribution layer, and the plastic packaging material which is filled above the redistribution layer and coats the high-heat chip and the low-heat chip is filled above the redistribution layer; the upper surface of the high-heat chip is exposed out of the plastic package material, and the upper surface of the low-heat chip is encapsulated in the plastic package material;

the low-heat chip is characterized in that a warpage adjusting protective layer is arranged on the upper surface of the low-heat chip;

or at least one through hole is formed in the plastic packaging material right above the low-heat chip, and part of the upper surface of the low-heat chip is exposed out of the plastic packaging material through the through hole.

2. The fan-out package structure of claim 1, wherein when a warpage adjusting protection layer is disposed on the upper surface of the low-heat chip, the upper surface of the warpage adjusting protection layer is exposed outside the molding compound;

or the plastic packaging material extends to the upper part of the warpage adjusting protective layer and coats the upper surface of the warpage adjusting protective layer.

3. The fan-out package structure of claim 1, wherein when the molding compound directly above the low-thermal chip is provided with the through hole, the fan-out package structure further comprises: and arranging a warpage adjusting protective layer on the upper surface of the low-heat chip, wherein the through hole penetrates through the warpage adjusting protective layer.

4. The fan-out packaging structure of claim 1 or 3, wherein a groove is formed downwards from the upper surface of the plastic packaging material on the plastic packaging material of the low-heat chip adjacent to the high-heat chip, the groove is not connected with the adjacent chip, and the bottom of the groove is not lower than the upper surface of the low-heat chip; the chip includes: a high heat chip and/or a low heat chip.

5. The fan-out packaging structure of claim 1 or 3, wherein the opening size of the through hole is kept unchanged or sequentially decreased in the extending direction from the upper surface of the molding compound to the low-heat chip.

6. The fan-out package structure of claim 1 or 3, wherein at least one through hole is arranged in a long strip shape along the edge of the low heat chip close to the high heat chip, and/or at least 2 through holes and more than 2 through holes are arranged in a long strip shape along the edge of the low heat chip close to the high heat chip.

7. The fan-out package structure of claim 1, wherein the high heat chip and the low heat chip are both electrically connected to the redistribution layer through solder balls.

8. The fan-out package structure of claim 1, further comprising: and the plastic packaging material is used for coating and filling the underfill layer arranged above the rewiring layer, and the underfill layer coats the end part of one side, close to the rewiring layer, of the high-heat chip and/or the low-heat chip.

9. The fan-out package structure of claim 8, wherein the underfill layer further encapsulates sidewalls of high heat chips and/or low heat chips.

10. The fan-out package structure of claim 1, further comprising: and the polymer medium layer is attached to the lower surface of the low-heat chip.

11. The fan out package structure of any of claims 1 to 3,

the warpage-regulating protective layer has a thickness >10 um and a coefficient of thermal expansion >10 ppm/K.

Technical Field

The invention belongs to the field of semiconductor manufacturing, and particularly relates to a fan-out packaging structure.

Background

The exposed packaging structure with the rewiring firstly has thicker rewiring and an underfill/plastic package combination layer on the front surface of the chip, and the combination layer has higher thermal expansion coefficient. With the requirement of reducing the fan degree of the thick chip of the packaging structure, the exposed packaging structure has obvious warpage, the subsequent flip-chip process is influenced, and the problems of process and reliability failure exist.

Disclosure of Invention

The invention aims to provide a fan-out packaging structure for solving the technical problem.

In order to achieve one of the above objects, an embodiment of the present invention provides a fan-out package structure, including: the redistribution layer is arranged below the redistribution layer, the solder balls are electrically connected with the high-heat chip and the low-heat chip above the redistribution layer, and the plastic packaging material which is filled above the redistribution layer and coats the high-heat chip and the low-heat chip is filled above the redistribution layer; the upper surface of the high-heat chip is exposed out of the plastic package material, and the upper surface of the low-heat chip is encapsulated in the plastic package material;

arranging a warpage adjusting protective layer on the upper surface of the low-heat chip;

or at least one through hole is formed in the plastic packaging material right above the low-heat chip, and part of the upper surface of the low-heat chip is exposed out of the plastic packaging material through the through hole.

As a further improvement of an embodiment of the present invention, when a warpage-adjusting protection layer is disposed on the upper surface of the low-heat chip, the upper surface of the warpage-adjusting protection layer is exposed outside the molding compound;

or the plastic packaging material extends to the upper part of the warpage adjusting protective layer and coats the upper surface of the warpage adjusting protective layer.

As a further improvement of an embodiment of the present invention, when a through hole is formed in the molding compound directly above the low-thermal chip, the fan-out package structure further includes: and arranging a warpage adjusting protective layer on the upper surface of the low-heat chip, wherein the through hole penetrates through the warpage adjusting protective layer.

As a further improvement of one embodiment of the present invention, a groove is formed downward from the upper surface of a plastic package material on which a low-heat chip is adjacent to a high-heat chip, the groove is not connected to an adjacent chip, and the bottom of the groove is not lower than the upper surface of the low-heat chip; the chip includes: a high heat chip and/or a low heat chip.

As a further improvement of an embodiment of the present invention, in an extending direction from the upper surface of the molding compound to the low thermal chip, the opening sizes of the through holes are kept unchanged or gradually decreased.

As a further improvement of an embodiment of the present invention, at least one through hole is provided in an elongated shape along an edge of the low heat chip close to the high heat chip, and/or at least 2 and 2 or more through holes are arranged in an elongated shape along an edge of the low heat chip close to the high heat chip.

As a further improvement of an embodiment of the present invention, the high heat chip and the low heat chip are both electrically connected to the redistribution layer through solder balls.

As a further improvement of an embodiment of the present invention, the fan-out package structure further includes: and the plastic packaging material is used for coating and filling the underfill layer arranged above the rewiring layer, and the underfill layer coats the end part of one side, close to the rewiring layer, of the high-heat chip and/or the low-heat chip.

As a further improvement of an embodiment of the present invention, the underfill layer also covers the sidewalls of the high heat chip and/or the low heat chip.

As a further improvement of an embodiment of the present invention, the fan-out package structure further includes: and the polymer medium layer is attached to the lower surface of the low-heat chip.

As a further improvement of an embodiment of the present invention, the thickness of the warpage-regulating protective layer >10 um, and the thermal expansion coefficient >10 ppm/K.

Compared with the prior art, the fan-out packaging structure has the advantages that the warping adjusting protective layer is arranged on the back surface of the low-heat chip, or at least one through hole is formed in the plastic packaging material above the low-heat chip, so that the warping adjusting capacity of the whole fan-out packaging structure is improved; the yield and the stability of the fan-out packaging structure are greatly improved.

Drawings

FIG. 1 is a schematic structural diagram of a fan-out package structure according to a first embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a fan-out package structure according to a second embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a fan-out package structure according to a third embodiment of the present invention;

FIGS. 3A, 3B, and 3C are schematic top views of the through holes with different structures in the embodiment of FIG. 3;

FIG. 4 is a schematic top view of a fan-out package according to a fourth embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a fan-out package structure according to a fifth embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a fan-out package structure according to a sixth embodiment of the present invention;

fig. 7 is a flow chart illustrating a packaging method of a fan-out package structure according to a fifth embodiment of the present invention;

fig. 8 is a schematic step diagram of the packaging method shown in fig. 7 according to the present invention.

Detailed Description

The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.

It is noted that terms used herein such as "upper", "lower", and the like, which refer to relative spatial positions, are used for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative positional terms may be intended to encompass different orientations of the package structure in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the "bottom" surface of other elements or features would then be on the "top" surface of the other elements or features. Thus, the exemplary term "inferior surface" may encompass both an orientation of an upper surface and a lower surface. The package structure may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Referring to fig. 1, fig. 2, fig. 3, fig. 4, and fig. 5, the fan-out package structure according to the embodiment of the present invention includes: the redistribution layer 30 is provided with solder balls 80 arranged below the redistribution layer 30, a high-heat chip 41 and a low-heat chip 42 which are electrically connected with each other above the redistribution layer 30, and a plastic package material 70 which is filled above the redistribution layer 30 and covers the high-heat chip 41 and the low-heat chip 42; the upper surface of the high heat chip 41 is exposed to the outside of the molding compound 70, and the upper surface of the low heat chip 42 is encapsulated in the molding compound 70.

The high heat chip 41 is typically an SOC chip and the low heat chip 42 is typically a memory chip.

Specifically, referring to fig. 1, the fan-out package structure according to the first embodiment of the present invention further includes: a warpage adjusting protection layer 50 disposed on the upper surface of the low thermal chip 42, wherein the upper surface of the warpage adjusting protection layer 50 is exposed outside the molding compound 70; at least one polymer dielectric layer 43 attached to the lower surface of the low-heat chip 42; the underfill layer 60 arranged above the redistribution layer 30 is coated and filled with a plastic package material 70, the underfill layer 60 extends upwards from the upper surface of the redistribution layer 30, coats the side walls of the high heat chip 41 and the low heat chip 42, and extends to be in the same plane with the upper surface of the package structure; in addition, the high heat chip 41 and the low heat chip 42 are both electrically connected to the redistribution layer 30 through solder balls 80; the solder balls 80 may be solder balls or metal bumps with tin caps, and may also be other types of electrical connectors.

Referring to fig. 2, the fan-out package structure according to the second embodiment of the present invention further includes: a warpage adjusting protection layer 50 disposed on the upper surface of the low-heat chip 42, wherein the molding compound 70 extends above the warpage adjusting protection layer 50 and covers the upper surface of the warpage adjusting protection layer 50; at least one polymer dielectric layer 43 attached to the lower surface of the low-heat chip 42; the underfill layer 60 arranged above the redistribution layer 30 is coated and filled with a plastic package material 70, the underfill layer 60 extends upwards from the upper surface of the redistribution layer 30, coats the whole side wall of the low-heat chip 42 and coats part of the side wall of the high-heat chip 41, and the underfill layer 60 extends to be on the same plane with the upper surface of the low-heat chip 42; in addition, the high heat chip 41 and the low heat chip 42 are electrically connected to the redistribution layer 30 through solder balls 80.

Preferably, in any of the above and below embodiments, if the warpage-adjusting protective layer 50 is provided in this embodiment, the warpage-adjusting protective layer 50 preferably has a thickness >10 um and a thermal expansion coefficient >10 ppm/K. Further, the coefficient of thermal expansion of the warpage-regulating protective layer 50 is selected to be >20 ppm/K. The material of the warpage-adjusting protection layer 50 may be epoxy resin, silica gel, P I, PBO, BCB, epoxy resin filler composite material, other polymer composite material, and the like, which are not described herein again.

Preferably, in the first embodiment of the present invention, when the warpage-regulating protective layer 50 is selected, the thermal expansion coefficient is selected to be >20 ppm/K.

In the fan-out package structures of the first and second embodiments of the present invention, the warpage adjusting protection layer 50 is disposed on the upper surface of the low thermal chip 42, so as to increase the warpage adjusting capability of the entire fan-out package structure, and greatly improve the yield and stability of the fan-out package structure.

Referring to fig. 3, a fan-out package structure provided by a third embodiment of the present invention further includes: at least one through hole 71 is formed in the plastic package material 70 right above the low-heat chip 42, and a part of the upper surface of the low-heat chip 42 is exposed outside the plastic package material 70 through the through hole 71; an underfill layer 60 coated by a molding compound 70 and filled above the redistribution layer 30, wherein the underfill layer 60 extends upward from the upper surface of the redistribution layer 30 and coats partial sidewalls of the high thermal chip 41 and the low thermal chip 42; in addition, the high heat chip 41 and the low heat chip 42 are electrically connected to the redistribution layer 30 through solder balls 80.

Preferably, as shown in fig. 3A, 3B, and 3C, the size, shape, number, ratio of the chips to the through holes 71, and arrangement mode of the through holes can be specifically set as required; for example: the number of the through holes 71 is set to 1 or more; the opening of the through hole 71 is in the shape of a strip, a circle, a polygon, a runway, a polygon with an arc chamfer, or the like; when the plurality of through holes 71 are arranged, the arrangement mode is linear arrangement, staggered arrangement, irregular arrangement avoiding a chip heat sensitive area and the like; the area of the opening is, for example, 0.5% -99.5% of the area of the low-heat chip 42 below the opening, and the position and size of the opening can be adjusted according to the heat dissipation and warpage.

In the preferred embodiment of the present invention, the opening size of the through hole 71 is kept constant or gradually decreased in the extending direction from the upper surface of the molding compound 70 to the low thermal chip 42.

In addition, in the preferred embodiment of the present invention, the through holes 71 are prevented from crossing the edge of the low thermal chip 42.

With regard to the arrangement of the through holes 71, in the preferred embodiment of the present invention, as shown in fig. 3A, at least one through hole 71 is provided; further, at least one of the through holes 71 is arranged in a long strip shape along the edge of the low heat chip 42 close to the high heat chip 41; in this specific example, it is preferable that the corners of the through-hole 71 are provided in a chamfered shape with a circular arc; preferably, the opening width of the through hole 71 on the upper surface of the fan-shaped package structure is greater than or equal to 50 μm, and the aspect ratio of the through hole 71 is between 1:1 and 1: 10.

As shown in fig. 3B and 3C, the through holes 71 are at least 2, and 2 or more through holes 71 are arranged in a long strip shape along the edge of the low thermal chip 42 close to the high thermal chip 41; in the example shown in fig. 3B, the radial section of each through-hole 71 is provided in an elongated shape; in the example shown in fig. 3C, each through-hole 71 is provided in a circular shape in radial section.

Preferably, when the number of the through holes 71 is set to plural, the minimum interval between the adjacent through holes 71 is not less than 50 μm.

Preferably, the low heat chip 42 is disposed near the through hole 71 at the edge of the high heat chip 41, and the distance between the through hole 71 and the edge of the adjacent low heat chip 42 is greater than or equal to 50 μm.

Preferably, the low thermal chip 42 is disposed near the edge of the high thermal chip 41 with the through hole 71 being generally centered, and the straight line distance of the through hole 71 disposed near the edge of the high thermal chip 41 is greater than 1/2 of its neighboring chip.

With reference to fig. 4, the fan-out package structure of the fourth embodiment shown in fig. 4 is improved on the basis of the fan-out package structure of the third embodiment, and is different from the third embodiment in that a groove 72 is formed downward from the upper surface of a plastic package material on a low-heat chip 42 adjacent to a high-heat chip 41, the groove 72 is not connected to an adjacent chip, and the bottom of the groove 72 is not lower than the upper surface of the low-heat chip 42; the chip includes: a high heat chip 41 and/or a low heat chip 42. Note that the groove 72 of this embodiment is typically formed in the molding compound near the low thermal chip 42, and the groove 72 is not connected to any chip in the planar extension direction of the chip.

Fig. 4 is only marked based on fig. 3C, and other structures are not further described in detail.

With reference to fig. 5, the fan-out package structure of the fifth embodiment shown in fig. 5 of the present invention is improved on the basis of the fan-out package structure of the third embodiment or the fourth embodiment, and is different from the third embodiment or the fourth embodiment in that the fan-out package structure further includes: a warpage adjusting protection layer 50 is disposed on the upper surface of the low thermal chip 42, and the through hole 71 penetrates through the warpage adjusting protection layer 50. The material, thickness, and thermal expansion coefficient of the warpage adjusting protection layer 50 in the fifth embodiment can refer to the foregoing embodiments, and are not further described herein.

In the fan-out package structure of the third, fourth and fifth embodiments of the present invention, at least one through hole 71 is formed in the molding compound 70 above the low-heat chip 42, so that a window directly contacting with a thermal interface material can be provided for the low-heat chip while increasing the warpage adjustment capability of the whole fan-out package structure, and the heat dissipation capability of the chip and the overall stability of the chip spacing are improved; the yield and the stability of the fan-out packaging structure are greatly improved.

In another embodiment of the present invention, in addition to any of the above embodiments, the manner of electrically connecting the redistribution layer 30 between the high heat chip 41 and the low heat chip 42 may be adjusted according to the prior art, that is, the redistribution layer 30 may be directly or indirectly electrically connected through the solder balls 80 as shown in the above drawings, or may be connected through wire bonding, which is not illustrated herein. In addition, for at least one polymer dielectric layer 43 disposed on the lower surface of the low heat chip 42, for each of the above embodiments, the polymer dielectric layer can be selectively added or removed; in each of the above embodiments, the underfill layer 60 covering the periphery of the chip may selectively cover any one of the chips, or may not cover any of the chips, and may cover only the solder balls 80 below the chip from the gravity wiring layer 30 upwards, or cover the lower end of the chip from the gravity wiring layer 30 upwards, or cover the side wall of the chip from the gravity wiring layer 30 upwards to a position flush with the upper surface of the chip.

Referring to fig. 6, a fan-out package structure according to a sixth embodiment of the present invention includes: the redistribution layer 30 is arranged below the redistribution layer 30, a solder ball 80 is electrically connected with the high-heat chip 41 and the low-heat chip 42 above the redistribution layer 30, and at least one polymer dielectric layer 43 arranged on the lower surface of the low-heat chip 42 in a bonding mode; and a plastic package material 70 filled above the redistribution layer 30 and covering the high heat chip 41 and the low heat chip 42; the upper surface of the high heat chip 41 is exposed to the outside of the plastic package material 70, and the upper surface of the low heat chip 42 is encapsulated in the plastic package material 70; wherein, fan-out packaging structure still includes: and the underfill layer 60 arranged above the redistribution layer 30 is coated and filled by the molding compound 70, and the underfill layer 60 extends upwards from the upper surface of the redistribution layer 30, and only coats the lower end part of the high-heat chip 41 and/or only coats the high-density solder ball part.

In addition, in the sixth embodiment, the high heat chip 41 and the low heat chip 42 are both electrically connected to the redistribution layer 30 through solder balls 80; the solder balls 80 may be solder balls or metal bumps with solder caps, or other types of electrical connectors; the polymer dielectric layer 43 can be selectively added or removed, and is not further described herein.

Referring to fig. 7 and 8, an embodiment of the present invention provides a packaging method for the fan-out package structure shown in fig. 5, where the packaging method includes:

s1, providing a carrier board 10, and coating a single-layer or multi-layer temporary bonding protective layer 20 on the upper surface of the carrier board 10, wherein the temporary bonding protective layer 20 is used for protecting the redistribution layer 30 disposed above the temporary bonding protective layer 20; the temporary bonding protective layer 20 may be a polymer layer or a tape-shaped adhesive layer, both sides of which are generally provided with an adhesive tape such as a die attach film or a non-conductive film or the like, or an adhesive paste made by a spin coating process, or the like; adhesive glues such as: UV tapes which are easily peeled off after UV light (ultraviolet light) irradiation, Epoxy resins (Epoxy), silicone rubbers (si l i cone rubber), polyimides (P I), Polybenzoxazole (PBO), benzocyclobutene (BCB), and the like, which are removed by wet etching, chemical mechanical polishing, and the like.

It should be noted that the temporary bonding protection layer 20 in step S1 may be selectively disposed, that is, the redistribution layer 30 may be directly disposed on the carrier board 10 provided in step S1, which is not further described herein.

S2, disposing a redistribution layer 30 above the temporary bonding protection layer 20, the redistribution layer 30 being composed of multiple wiring stacks, which may be a wafer-level or board-level redistribution stack layer, or a multi-layer wired organic substrate.

S3, flip-chip mounting the high heat chip 41 and the low heat chip 42 on the rewiring layer 30; in this step, for the low-heat chip 42, if it is necessary to dispose the polymer dielectric layer 43 on the lower surface of the low-heat chip 42 and/or dispose the warpage-adjusting protective layer 50 on the upper surface of the low-heat chip 42, it is flip-chip mounted on the redistribution layer 30 in step S4 after being packaged with the low-heat chip 42 before step S3.

S4, underfill the high thermal chip 41 and/or the low thermal chip to form an underfill layer 60 above the redistribution layer 30, where the underfill layer 60 may cover only the under-chip metal bumps 80 with tin caps, may extend up to the side walls of the chip, or may extend to be flush with the upper surface of the low thermal chip 42, or may extend to be flush with the upper surface of the high thermal chip 41, and in this specific example, the underfill layer 60 extends to be flush with the upper surface of the low thermal chip 42.

It should be noted that step S5 can be performed alternatively, i.e., after step S4 is performed, the process goes directly to step S6.

S5, plastic packaging is carried out above the rewiring by adopting a plastic packaging material 70, and all chips are embedded into the plastic packaging material 70; the step can adopt a mode of plastic package or printing/sticking and pressing a high polymer composite material to completely protect the chip.

S6, removing the temporary bonding protective layer 20 and the carrier plate below the redistribution layer 30, and forming a metal bump 80 with a tin cap below the redistribution layer 30; the removal method of the temporary bonding protection layer 20 and the substrate is selected according to the material of the temporary bonding protection layer 20, and will not be further described herein.

S7, thinning the back to expose the upper surface of the high thermal chip 41 outside the molding compound 70, where the upper surface of the high thermal chip 41 is the upper surface of the entire fan-out package structure.

S8, forming a through hole 71 at a predetermined position above the low thermal chip 42, so that a part of the upper surface of the low thermal chip 42 is exposed outside the molding compound 70 through the through hole 71, thereby forming a final fan-shaped package structure. The hole forming method, such as UV laser hole forming, will not be further described herein.

In summary, in the fan-out package structure of the present invention, the warpage adjusting protection layer is disposed on the upper surface of the low-heat chip, or at least one through hole 71 is formed in the plastic package material above the low-heat chip, so as to increase the warpage adjusting capability of the whole fan-out package structure; the yield and the stability of the fan-out packaging structure are greatly improved.

It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.

The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.