Semiconductor interconnection structure and preparation method thereof
阅读说明：本技术 半导体互连结构及其制备方法 (Semiconductor interconnection structure and preparation method thereof ) 是由 不公告发明人 于 2018-09-05 设计创作，主要内容包括：本发明提供一种半导体互连结构及其制备方法,包括如下步骤：1)提供一基底,基底上形成有介电层,于介电层内形成接触孔；2)以低温化学气相沉积的方式至少于接触孔的底部和侧壁形成第一金属层,第一金属层包括成核层；3)以包含低电流密度电镀的电镀方式于第一金属层上形成第二金属层,第二金属层包括种子层,第二金属层的电阻率小于第一金属层的电阻率。本发明通过先于接触孔内低温形成第一金属层后再形成第二金属层,可以避免在接触孔内填充的金属层内部形成孔洞,从而可以有效降低填充的整体金属层的电阻值；第二金属层的电阻率小于第一金属层的电阻率,可以进一步降低填充的整体金属层的电阻值。(The invention provides a semiconductor interconnection structure and a preparation method thereof, comprising the following steps: 1) providing a substrate, forming a dielectric layer on the substrate, and forming a contact hole in the dielectric layer; 2) forming a first metal layer at least at the bottom and the side wall of the contact hole in a low-temperature chemical vapor deposition mode, wherein the first metal layer comprises a nucleating layer; 3) and forming a second metal layer on the first metal layer by an electroplating method including low current density electroplating, wherein the second metal layer comprises a seed layer, and the resistivity of the second metal layer is smaller than that of the first metal layer. According to the invention, the first metal layer is formed in the contact hole at a low temperature before the second metal layer is formed, so that a hole can be prevented from being formed in the metal layer filled in the contact hole, and the resistance value of the filled whole metal layer can be effectively reduced; the resistivity of the second metal layer is less than the resistivity of the first metal layer, which can further reduce the resistance of the filled bulk metal layer.)
1. A method for preparing a semiconductor interconnection structure is characterized by comprising the following steps:
1) providing a substrate, wherein a dielectric layer is formed on the substrate, and a contact hole is formed in the dielectric layer;
2) forming a first metal layer by low temperature chemical vapor deposition at least on the bottom and sidewalls of the contact hole, the first metal layer including a nucleation layer; and
3) and forming a second metal layer on the first metal layer in an electroplating mode including low current density electroplating, wherein the second metal layer comprises a seed layer, and the resistivity of the second metal layer is smaller than that of the first metal layer.
2. The method for preparing a semiconductor interconnection structure according to claim 1, wherein the contact hole formed in step 1) has an aspect ratio of more than 5.
3. The method of claim 1, wherein the material of the first metal layer deposited in step 2) comprises tungsten; the material of the second metal layer deposited in step 3) comprises copper.
4. The method of claim 3, wherein in step 2), the reaction gas for forming the first metal layer comprises tungsten hexafluoride and monosilane.
5. The method for manufacturing a semiconductor interconnect structure according to claim 1, wherein the temperature for forming the first metal layer in step 2) is not higher than 300 ℃, and the thickness of the first metal layer is between 500 and 700 angstroms.
6. The method for manufacturing a semiconductor interconnect structure according to claim 1, wherein the step 2) comprises the steps of:
2-1) forming the nucleation layer at least at the bottom and sidewalls of the contact hole; and
2-2) forming a body layer of the first metal layer on the surface of the nucleation layer, wherein the material of the nucleation layer is the same as the material of the body layer of the first metal layer.
7. The method for preparing a semiconductor interconnection structure according to claim 6, wherein the deposition period of the nucleation layer is between 8 and 10.
8. The method of claim 7, wherein the diborane and tungsten hexafluoride are used as reactive gases to deposit the semiconductor interconnect structure at a temperature of no greater than 300 ℃ for a deposition cycle; and depositing for 7-9 deposition cycles at a temperature not higher than 300 ℃ by using monosilane and tungsten hexafluoride as reaction gases.
9. The method for manufacturing a semiconductor interconnect structure according to claim 1, wherein the step 3) comprises the steps of:
3-1) forming the seed layer in the contact hole, wherein the seed layer is positioned on the upper surface of the first metal layer;
3-2) electroplating a first electroplating layer with a first thickness in the contact hole from the upper surface of the seed layer to the upper part under the condition of first current density; and
3-3) continuing to electroplate a second electroplated layer of a second thickness on the upper surface of the first electroplated layer and the upper surface of the dielectric layer under the condition of a second current density, wherein the first current density is smaller than the second current density; wherein the content of the first and second substances,
the first electroplated layer and the second electroplated layer jointly form a main body layer of the second metal layer, and the material of the seed layer is the same as that of the main body layer of the second metal layer.
10. The method for manufacturing a semiconductor interconnect structure according to claim 9, wherein in step 3-2), the first current density is between 1.5 a and 3 a, and the first thickness is between 900 a and 1100 a; in the step 3-3), the second current density is between 20 and 40 amperes, and the second thickness is between 3500 angstroms and 4500 angstroms.
11. The method of claim 9, wherein the seed layer has a thickness of between 150 and 200 angstroms.
12. The method for preparing the semiconductor interconnection structure according to claim 1, further comprising the following steps between the step 1) and the step 2): forming an adhesion barrier layer on the bottom and the side wall of the contact hole and the upper surface of the dielectric layer; in step 2), the first metal layer is formed on the surface of the adhesion barrier layer.
13. The method for manufacturing a semiconductor interconnect structure as claimed in claim 1, wherein in step 2), the first metal layer is further formed on the upper surface of the dielectric layer; the step 3) is followed by a step of removing the first metal layer and the second metal layer on the dielectric layer.
14. The method as claimed in any one of claims 1 to 13, wherein in step 2), a ratio of a thickness of the first metal layer formed at a bottom portion in the contact hole to a depth of the contact hole is proportional to an aspect ratio of the contact hole.
15. The method for manufacturing a semiconductor interconnect structure according to any one of claims 1 to 13, wherein in step 2), the thickness of the first metal layer formed in the contact hole accounts for 10% to 70% of the depth of the contact hole.
16. A semiconductor interconnect structure, comprising:
a substrate;
the dielectric layer is positioned on the upper surface of the substrate, and a contact hole is formed in the dielectric layer;
the first metal layer is formed on the bottom and the side wall of the contact hole in a low-temperature chemical vapor deposition mode and comprises a nucleating layer; and
and a second metal layer formed on the first metal layer in an electroplating manner including low current density electroplating to fill the contact hole, the second metal layer including a seed layer, the second metal layer having a resistivity less than that of the first metal layer.
17. The semiconductor interconnect structure of claim 16, wherein the contact hole has an aspect ratio greater than 5.
18. The semiconductor interconnect structure of claim 16, wherein the first metal layer further comprises a body layer at a surface of the nucleation layer, the body layer of the first metal layer comprising a tungsten metal layer; the second metal layer further comprises a main body layer positioned on the surface of the seed layer, and the main body layer of the second metal layer comprises a copper metal layer.
19. The semiconductor interconnect structure of claim 16, wherein the first metal layer is deposited at a temperature not higher than 300 ℃ and has a thickness between 500 and 700 angstroms.
20. The semiconductor interconnect structure of claim 18, wherein the body layer of the second metal layer comprises a first electroplated layer and a second electroplated layer, the first electroplated layer being located on an upper surface of the first metal layer, the second electroplated layer being located at least on an upper surface of the first electroplated layer.
21. The semiconductor interconnect structure of claim 20, wherein the first electroplated layer is electroplated at a current density of between 1.5 a and 3 a, the first electroplated layer having a thickness of between 900 a and 1100 a; the second electroplated layer is formed by electroplating under the current density of 20-40A, and the thickness of the second electroplated layer is 3500-4500A.
22. The semiconductor interconnect structure of claim 16,
the nucleation layer is located between the dielectric layer and the body layer of the first metal layer; the material of the nucleation layer is the same as the material of the body layer of the first metal layer; and
the seed layer is positioned between the main body layer of the first metal layer and the main body layer of the second metal layer; the material of the seed layer is the same as the material of the main body layer of the second metal layer.
23. The semiconductor interconnect structure of claim 22, wherein the seed layer has a thickness of between 150 and 200 angstroms.
24. The semiconductor interconnect structure of claim 16, further comprising an adhesion barrier layer formed at least on a bottom edge and a sidewall of the contact hole and between the dielectric layer and the first metal layer.
25. The semiconductor interconnect structure of claim 24, wherein said adhesion barrier layer has a thickness between 100 and 200 angstroms.
26. The semiconductor interconnect structure of any of claims 16 to 25, wherein the first metal layer directly coats the bottom and sidewalls of the second metal layer, and wherein the second metal layer has an aspect ratio smaller than an aspect ratio of the contact hole.
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor interconnection structure and a preparation method thereof.
Background
Tungsten film deposition using Chemical Vapor Deposition (CVD) is a common process in many semiconductor manufacturing in existing semiconductor companies. In the prior art, as shown in fig. 1, a
However, as the miniaturization of the device is advanced, the size of the semiconductor interconnection structure is smaller and smaller, when the existing chemical vapor deposition process is used to fill the
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor interconnect structure and a method for manufacturing the same, which are used to solve the problem in the prior art that when the existing chemical vapor deposition process is used to form the tungsten metal layer in the contact hole in one step, a hole is formed in the filled tungsten metal layer, which causes the electromigration problem in the subsequent copper process, and causes the resistance value of the contact hole to be larger, which causes the reliability of the semiconductor device to be reduced.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor interconnect structure, the method comprising the steps of:
1) providing a substrate, wherein a dielectric layer is formed on the substrate, and a contact hole is formed in the dielectric layer;
2) forming a first metal layer by low temperature chemical vapor deposition at least on the bottom and sidewalls of the contact hole, the first metal layer including a nucleation layer; and
3) and forming a second metal layer on the first metal layer in an electroplating mode including low current density electroplating, wherein the second metal layer comprises a seed layer, and the resistivity of the second metal layer is smaller than that of the first metal layer.
As a preferred embodiment of the present invention, the aspect ratio of the contact hole formed in step 1) is greater than 5.
As a preferred aspect of the present invention, the material of the first metal layer deposited in step 2) includes tungsten; the material of the second metal layer deposited in step 3) comprises copper.
In a preferred embodiment of the present invention, in step 2), the reaction gas for forming the first metal layer includes tungsten hexafluoride and monosilane.
In a preferred embodiment of the present invention, in step 2), the temperature for forming the first metal layer is not higher than 300 ℃, and the thickness of the first metal layer is between 500 angstroms and 700 angstroms.
As a preferable aspect of the present invention, the step 2) includes the steps of:
2-1) forming the nucleation layer at least at the bottom and sidewalls of the contact hole; and
2-2) forming a body layer of the first metal layer on the surface of the nucleation layer, wherein the material of the nucleation layer is the same as the material of the body layer of the first metal layer.
In a preferred embodiment of the present invention, the deposition period of the nucleation layer is between 8 and 10.
As a preferred embodiment of the present invention, diborane and tungsten hexafluoride are used as reaction gases to deposit a deposition cycle at a temperature not higher than 300 ℃; and depositing for 7-9 deposition cycles at a temperature not higher than 300 ℃ by using monosilane and tungsten hexafluoride as reaction gases.
As a preferable aspect of the present invention, the step 3) includes the steps of:
3-1) forming the seed layer in the contact hole, wherein the seed layer is positioned on the upper surface of the first metal layer;
3-2) electroplating a first electroplating layer with a first thickness in the contact hole from the upper surface of the seed layer to the upper part under the condition of first current density; and
3-3) continuing to electroplate a second electroplated layer of a second thickness on the upper surface of the first electroplated layer and the upper surface of the dielectric layer under the condition of a second current density, wherein the first current density is smaller than the second current density; wherein the content of the first and second substances,
the first electroplated layer and the second electroplated layer jointly form a main body layer of the second metal layer, and the material of the seed layer is the same as that of the main body layer of the second metal layer.
In a preferable embodiment of the invention, in the step 3-2), the first current density is between 1.5 a and 3 a, and the first thickness is between 900 a and 1100 a; in the step 3-3), the second current density is between 20 and 40 amperes, and the second thickness is between 3500 angstroms and 4500 angstroms.
In a preferred embodiment of the present invention, the thickness of the seed layer is between 150 angstroms and 200 angstroms.
As a preferable scheme of the invention, the method also comprises the following steps between the step 1) and the step 2): forming an adhesion barrier layer on the bottom and the side wall of the contact hole and the upper surface of the dielectric layer; in step 2), the first metal layer is formed on the surface of the adhesion barrier layer.
As a preferable aspect of the present invention, in step 2), the first metal layer is further formed on an upper surface of the dielectric layer; the step 3) is followed by a step of removing the first metal layer and the second metal layer on the dielectric layer.
As a preferable aspect of the present invention, in the step 2), a ratio of a thickness of the first metal layer formed at the bottom portion in the contact hole to a depth of the contact hole is proportional to an aspect ratio of the contact hole.
In a preferred embodiment of the present invention, in the step 2), the thickness of the first metal layer formed in the contact hole is 10% to 70% of the depth of the contact hole.
The present invention also provides a semiconductor interconnect structure comprising:
a substrate;
the dielectric layer is positioned on the upper surface of the substrate, and a contact hole is formed in the dielectric layer;
the first metal layer is formed on the bottom and the side wall of the contact hole in a low-temperature chemical vapor deposition mode and comprises a nucleating layer; and
and a second metal layer formed on the first metal layer in an electroplating manner including low current density electroplating to fill the contact hole, the second metal layer including a seed layer, the second metal layer having a resistivity less than that of the first metal layer.
In a preferred embodiment of the present invention, the aspect ratio of the contact hole is greater than 5.
As a preferred aspect of the present invention, the first metal layer further includes a body layer located on a surface of the nucleation layer, the body layer of the first metal layer including a tungsten metal layer; the second metal layer further comprises a main body layer positioned on the surface of the seed layer, and the main body layer of the second metal layer comprises a copper metal layer.
In a preferred embodiment of the present invention, the deposition temperature of the first metal layer is not higher than 300 ℃, and the thickness of the first metal layer is between 500 angstroms and 700 angstroms.
In a preferred embodiment of the present invention, the main body layer of the second metal layer includes a first plating layer and a second plating layer, the first plating layer is located on an upper surface of the first metal layer, and the second plating layer is located on at least an upper surface of the first plating layer.
In a preferred embodiment of the present invention, the first plating layer is formed by plating at a current density of 1.5 to 3A, and the thickness of the first plating layer is 900 to 1100A; the second electroplated layer is formed by electroplating under the current density of 20-40A, and the thickness of the second electroplated layer is 3500-4500A.
As a preferred aspect of the present invention, the nucleation layer is located between the dielectric layer and the body layer of the first metal layer; the material of the nucleation layer is the same as the material of the body layer of the first metal layer; and
the seed layer is positioned between the main body layer of the first metal layer and the main body layer of the second metal layer; the material of the seed layer is the same as the material of the main body layer of the second metal layer.
In a preferred embodiment of the present invention, the thickness of the seed layer is between 150 angstroms and 200 angstroms.
As a preferred aspect of the present invention, the semiconductor interconnect structure further includes an adhesion barrier layer formed at least on the bottom edge and the sidewall of the contact hole and located between the dielectric layer and the first metal layer.
In a preferred embodiment of the present invention, the adhesion barrier layer has a thickness of 100 to 200 angstroms.
In a preferred embodiment of the present invention, the first metal layer directly covers the bottom and the side walls of the second metal layer, and the aspect ratio of the second metal layer is smaller than the aspect ratio of the contact hole.
As described above, the semiconductor interconnect structure and the method for manufacturing the same of the present invention have the following advantages:
according to the invention, the first metal layer is formed in the contact hole at a low temperature before the second metal layer is formed, so that a hole can be prevented from being formed in the metal layer filled in the contact hole, and the resistance value of the filled whole metal layer can be effectively reduced;
the resistivity of the second metal layer is smaller than that of the first metal layer, so that the resistance value of the filled whole metal layer can be further reduced;
the first metal layer can comprise tungsten, the second metal layer can comprise copper, a tungsten layer is formed in the contact hole, a copper layer is formed in the contact hole, the tungsten and the copper are not fused, the tungsten can play a role of a barrier layer, and the copper can be prevented from diffusing into a dielectric layer below the tungsten.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a structure obtained after filling a tungsten metal layer in a contact hole by using a chemical vapor deposition process in the prior art.
Fig. 2 is a flowchart illustrating a method for fabricating a semiconductor interconnect structure according to a first embodiment of the present invention.
Fig. 9 to 10 are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor interconnect structure according to a first embodiment of the present invention; fig. 10 is a schematic cross-sectional view of a semiconductor interconnect structure according to a second embodiment of the present invention.
Description of the element reference numerals
10' substrate
10 dielectric layer
11 contact hole
12 adhesion barrier layer
13 nucleation layer
14 tungsten metal layer
15 holes
20' substrate
20 dielectric layer
21 contact hole
22 first metal layer
221 body layer of first metal layer
23 second metal layer
231 first plating layer
232 second plating layer
233 second metal layer
24 nucleation layer
25 seed layer
26 adhesion barrier layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 10. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
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