阅读说明：本技术 集成电路芯片及熔断器的检测方法 (Integrated circuit chip and fuse detection method ) 是由 不公告发明人 于 2018-09-07 设计创作，主要内容包括：本公开是关于一种集成电路芯片及熔断器的检测方法,包括衬底、多层导电层、熔断器、介电层和闩锁电路；其中,相邻的导电层之间设置有介电层,所述衬底和与其相邻的导电层之间设置有介电层,所述介电层上设置有接触孔；熔断器位于第一介电层上的接触孔中,所述第一介电层为多层所述介电层中的任一层介电层；闩锁电路设置在所述衬底上,和所述熔断器连接。在集成电路芯片测试时,触发闩锁效应,使得闩锁电路中的电流不断增大,直至烧断熔断器,实现了对熔断器测试时的熔断。并且在测试多个熔断器时,只需顺序触发每个熔断器的闩锁电路即可,提升了测试效率,节约了测试时间。(The present disclosure relates to an integrated circuit chip and a fuse testing method, comprising a substrate, a plurality of conductive layers, a fuse, a dielectric layer and a latch circuit; a dielectric layer is arranged between the adjacent conductive layers, a dielectric layer is arranged between the substrate and the conductive layer adjacent to the substrate, and a contact hole is formed in the dielectric layer; the fuse is positioned in a contact hole on a first dielectric layer, wherein the first dielectric layer is any one of a plurality of dielectric layers; a latch circuit is disposed on the substrate and connected to the fuse. When the integrated circuit chip is tested, the latch effect is triggered, so that the current in the latch circuit is continuously increased until the fuse is blown, and the fuse is blown during the test of the fuse. And when testing a plurality of fuses, only need the latch circuit of order triggering every fuse can, promoted efficiency of software testing, practiced thrift test time.)

1. An integrated circuit chip, comprising:

a substrate;

the multilayer conducting layer, wherein, there is dielectric layer between the adjacent conducting layers, there is dielectric layer between said substrate and conducting layer adjacent to it, there are contact holes on the said dielectric layer;

the fuse is positioned in a contact hole on a first dielectric layer, and the first dielectric layer is any one of a plurality of dielectric layers;

a latch circuit disposed in the substrate and connected to the fuse.

2. The integrated circuit chip of claim 1, wherein the first dielectric layer is an uppermost one of the plurality of dielectric layers, wherein a bottom layer is proximate to the substrate and an upper layer is distal to the substrate.

3. The integrated circuit chip of claim 2, wherein the integrated circuit chip further comprises:

a connector in a contact hole in a second dielectric layer, the second dielectric layer being a dielectric layer between the first dielectric layer and the substrate.

4. The integrated circuit chip of claim 3, wherein the contact holes are via holes, and a cross-sectional area of the first contact hole is smaller than a cross-sectional area of the second contact hole.

5. The integrated circuit chip of claim 3, wherein the fuse has a resistance greater than a resistance of the connector.

6. The integrated circuit chip of claim 2, wherein a power supply is coupled to the first conductive layer for receiving a power signal, the first conductive layer being a conductive layer on a side of the first dielectric layer remote from the substrate.

7. The integrated circuit chip of claim 2, wherein a disconnection detection means is connected to the second conductive layer, said disconnection detection means being for detecting whether said fuse is blown, said second conductive layer being a conductive layer on a side of said first dielectric layer adjacent to said substrate.

8. The integrated circuit chip of claim 1, wherein the fuse is a metal fuse.

9. The integrated circuit chip of claim 1, wherein a plurality of said conductive layers and said substrate are disposed parallel to each other.

10. The integrated circuit chip of any of claims 1-9, wherein the integrated circuit chip further comprises:

and the passivation layer is positioned on one side of the first conducting layer, which is far away from the substrate, and the first conducting layer is a conducting layer on the uppermost layer in the multiple conducting layers.

11. A method of testing an integrated circuit chip fuse, comprising:

triggering the latch effect of the latch circuit and outputting fusing current;

the fusing current flows through the connector, the conductive layer, and the fuse to fuse the fuse.

12. The test method of claim 11, further comprising:

detecting whether the fuse is blown;

if the fuse is fused, outputting a first signal;

and if the fuse is not fused, outputting a second signal.