阅读说明：本技术 包括含硼绝缘图案的集成电路器件 (Integrated circuit device including boron-containing insulation pattern ) 是由 李东阁 孙渊豪 李梦燮 李昱烈 于 2019-05-09 设计创作，主要内容包括：提供了集成电路(IC)器件。IC器件包括衬底，衬底包括有源区。IC器件包括衬底上的位线。IC器件包括连接在有源区与位线之间的直接接触部。IC器件包括衬底上的接触插塞。此外，IC器件包括在接触插塞和直接接触部之间的含硼绝缘图案。(An Integrated Circuit (IC) device is provided. The IC device includes a substrate including an active region. The IC device includes a bitline on a substrate. The IC device includes a direct contact connected between the active region and the bit line. The IC device includes a contact plug on a substrate. Further, the IC device includes a boron-containing insulating pattern between the contact plug and the direct contact.)

1. An integrated circuit device, comprising:

a substrate including a first active region and a second active region spaced apart from each other;

bit lines extending in a horizontal direction on the substrate;

a direct contact connected between the first active region and the bit line;

a contact plug extending in a vertical direction on the substrate, the contact plug including an upper portion adjacent to the bit line and a lower portion contacting the second active region in the substrate; and

a boron-containing insulating pattern between a lower portion of the contact plug and the direct contact portion.

2. The integrated circuit device of claim 1, wherein the boron-containing insulating pattern comprises a silicon boron nitride (SiBN) film having a dielectric constant of 2 to 6.

3. The integrated circuit device of claim 1,

wherein the boron-containing insulating pattern comprises Si_xB_yN_z，

Wherein x is more than or equal to 0.1 and less than or equal to 0.5, y is more than or equal to 0.1 and less than or equal to 0.5, and z is more than or equal to 0.1 and less than or equal to 0.8.

4. The integrated circuit device of claim 1, wherein a lower portion of the contact plug and the direct contact are both in contact with the boron-containing insulating pattern.

5. The integrated circuit device of claim 1, further comprising: an insulation region between a lower portion of the contact plug and the boron-containing insulation pattern and between the direct contact portion and the boron-containing insulation pattern,

wherein the insulating region has a dielectric constant lower than that of the boron-containing insulating pattern.

6. The integrated circuit device of claim 5, wherein the insulating region comprises a silicon oxide film, an air spacer, or a combination thereof.

7. The integrated circuit device of claim 1, wherein the boron-containing insulating pattern is buried in the substrate.

8. The integrated circuit device of claim 1, further comprising: a boron-containing insulating fence on a sidewall of the bit line,

wherein a boron content in the boron-containing insulating fence increases toward the bit line.

9. The integrated circuit device of claim 1, further comprising: first and second insulating spacers between the contact plug and the bit line on the boron-containing insulating pattern, the first and second insulating spacers comprising different respective materials,

wherein each of the first insulating spacer and the second insulating spacer is boron-free.

10. The integrated circuit device of claim 9, wherein each of the first and second insulating spacers extends parallel to the bit line.

11. The integrated circuit device of claim 9, further comprising: an insulating fence extending in a vertical direction on the substrate, the insulating fence being aligned with the contact plug in the horizontal direction,

wherein the first and second insulating spacers extend between the bit line and the insulating fence.

12. The integrated circuit device of claim 9, wherein each of the first and second insulating spacers surrounds a perimeter of the contact plug.

13. The integrated circuit device of claim 9, further comprising: an insulating fence extending in a vertical direction on the substrate, the insulating fence being aligned with the contact plug in the horizontal direction,

wherein the first and second insulating spacers extend between the contact plug and the insulating fence.

14. The integrated circuit device of claim 13, further comprising: a boron-containing insulating fence between the bit line and the insulating fence.

15. An integrated circuit device, comprising:

a substrate including a plurality of active regions spaced apart from each other;

bit lines extending in a horizontal direction on the substrate;

a plurality of contact plugs spaced apart from each other on the substrate along a horizontal line parallel to the bit line;

a plurality of insulating fences alternating with the plurality of contact plugs in the horizontal direction;

a direct contact connected between a first active region of the plurality of active regions and the bit line; and

a boron-containing insulating pattern between a first contact plug of the plurality of contact plugs and the direct contact.

16. The integrated circuit device of claim 15,

wherein the first contact plug contacts a second active region of the plurality of active regions in the substrate, and

wherein the first contact plug and the direct contact are both in contact with the boron-containing insulating pattern.

17. The integrated circuit device of claim 15, further comprising: an insulating film between the direct contact portion and the boron-containing insulating pattern and between the first contact plug and the boron-containing insulating pattern,

wherein the insulating film has a dielectric constant lower than that of the boron-containing insulating pattern.

18. The integrated circuit device of claim 15, further comprising: a plurality of boron-containing insulating fences between the bit lines and the plurality of insulating fences.

19. The integrated circuit device of claim 15, further comprising: first and second insulating spacers extending in the horizontal direction between the bit line and the plurality of contact plugs and extending between the bit line and the plurality of insulating rails, the first and second insulating spacers including different respective materials.

20. The integrated circuit device of claim 15, further comprising: a plurality of first insulating spacers and a plurality of second insulating spacers between the bit line and the plurality of contact plugs and between the plurality of contact plugs and the plurality of insulating fences, the plurality of first insulating spacers and the plurality of second insulating spacers surrounding respective peripheries of the plurality of contact plugs.

21. An integrated circuit device, comprising:

a substrate including a plurality of active regions;

bit lines extending in a horizontal direction on the substrate;

a direct contact connected between a first active region of the plurality of active regions and the bit line;

first and second contact plugs facing each other with the bit line therebetween, wherein the first and second contact plugs are connected to second and third active regions of the plurality of active regions, respectively;

a first insulating fence and a second insulating fence facing each other, wherein the bit line is between the first insulating fence and the second insulating fence; and

a plurality of boron-containing insulation patterns including a first boron-containing insulation pattern between the direct contact and the first contact plug and a second boron-containing insulation pattern between the direct contact and the second contact plug,

wherein each of the plurality of boron-containing insulating patterns comprises a silicon boron nitride (SiBN) film.

22. The integrated circuit device of claim 21,

wherein each of the plurality of boron-containing insulating patterns has a dielectric constant of 2 to 6, and

wherein a boron content in the plurality of boron-containing insulating patterns increases toward the direct contact.

23. The integrated circuit device of claim 21,

wherein the first contact plug contacts the second active region and the first boron-containing insulation pattern, and

wherein the second contact plug contacts the third active region and the second boron-containing insulation pattern.

24. The integrated circuit device of claim 21, further comprising: an insulating film between the direct contact portion and the first boron-containing insulating pattern and between the direct contact portion and the second boron-containing insulating pattern,

wherein the insulating film has a dielectric constant lower than that of at least one of the first boron-containing insulating pattern or the second boron-containing insulating pattern.

25. The integrated circuit device of claim 21, further comprising: a plurality of boron-containing insulating fences comprising a first boron-containing insulating fence between the bit line and the first insulating fence and a second boron-containing insulating fence between the bit line and the second insulating fence.

Technical Field

The present disclosure relates to an Integrated Circuit (IC) device, and more particularly, to an IC device including a plurality of conductive patterns adjacent to each other.

Background

In recent years, as the size of TC devices is rapidly reduced, the distance between interconnection lines becomes narrower, and thus the distance between an interconnection line and a contact plug interposed between the interconnection lines is gradually reduced. Accordingly, parasitic capacitance between the contact plug and the interconnection line increases, and the possibility of an electrical short between the contact plug and the conductive region adjacent thereto also increases.

Disclosure of Invention

The present inventive concept provides an Integrated Circuit (IC) device that may have a reduced (e.g., miniaturized) unit cell size as the size of the IC device is reduced, and may reduce parasitic capacitance between a contact plug formed in a limited area and a conductive line adjacent to the contact plug, and reduce the possibility of electrical short between adjacent conductive regions to improve reliability.

According to some embodiments of the inventive concept, an IC device is provided. The IC device may include a substrate including a first active region and a second active region spaced apart from each other. The IC device may include bit lines extending in a horizontal direction on the substrate. The IC device may include a direct contact connected between the first active region and the bit line. The IC device may include a contact plug extending in a vertical direction on the substrate. The contact plug may include an upper portion adjacent to the bit line and a lower portion contacting the second active region in the substrate. Further, the IC device may include a boron-containing insulating pattern between a lower portion of the contact plug and the direct contact portion.

An IC device according to some embodiments of the inventive concept may include a substrate including a plurality of active regions spaced apart from each other. The IC device may include bit lines extending in a horizontal direction on the substrate. The IC device may include a plurality of contact plugs spaced apart from each other along a horizontal line parallel to the bit line on the substrate. The IC device may include a plurality of insulating fences alternating with the plurality of contact plugs in the horizontal direction. The IC device may include a direct contact connected between a first active region of the plurality of active regions and a bit line. Further, the IC device may include a boron-containing insulation pattern between a first contact plug of the plurality of contact plugs and the direct contact.

An IC device according to some embodiments of the inventive concept may include a substrate including a plurality of active regions. The IC device may include bit lines extending in a horizontal direction on the substrate. The IC device may include a direct contact connected between a first active region of the plurality of active regions and a bit line. The IC device may include a first contact plug and a second contact plug facing each other with the bit line therebetween. The first and second contact plugs may be connected to second and third active regions of the plurality of active regions, respectively. The TC device may include a first insulating fence and a second insulating fence facing each other with the bit line therebetween. Further, the IC device may include a plurality of boron-containing insulating patterns. The plurality of boron-containing insulation patterns may include a first boron-containing insulation pattern between the direct contact and the first contact plug and a second boron-containing insulation pattern between the direct contact and the second contact plug. Each of the plurality of boron-containing insulating patterns includes a silicon boron nitride (SiBN) film.

Drawings

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 illustrates a layout of major components of a memory cell array region of an Integrated Circuit (IC) device according to an embodiment;

fig. 2A shows a cross-sectional view of an IC device according to an embodiment;

FIG. 2B is an enlarged plan view of a portion of FIG. 2A;

fig. 3A illustrates a cross-sectional view of an IC device according to an embodiment;

FIG. 3B is an enlarged plan view of a portion of FIG. 3A;

fig. 4A shows a cross-sectional view of an IC device according to an embodiment;

FIG. 4B is an enlarged plan view of a portion of FIG. 4A;

fig. 5A shows a cross-sectional view of an IC device according to an embodiment;

FIG. 5B is an enlarged plan view of a portion of FIG. 5A;

fig. 6 is a cross-sectional view of an IC device according to an embodiment;

fig. 7A shows a cross-sectional view of an IC device according to an embodiment;

FIG. 7B is an enlarged plan view of the localized area of FIG. 7A;

fig. 8A shows a cross-sectional view of an IC device according to an embodiment;

FIG. 8B is an enlarged plan view of a portion of FIG. 8A;

fig. 9A shows a cross-sectional view of an IC device according to an embodiment;

FIG. 9B is an enlarged plan view of a portion of FIG. 9A;

fig. 10A shows a cross-sectional view of an IC device according to an embodiment;

FIG. 10B is an enlarged plan view of the localized area of FIG. 10A;

fig. 11 is a cross-sectional view of an IC device according to an embodiment;

fig. 12A to 12N are process sequence diagrams of a method of manufacturing an IC device according to an embodiment;

fig. 13A to 13D are cross-sectional views showing a process sequence of a method of manufacturing an IC device according to an embodiment;

fig. 14A to 14E are process sequence diagrams of a method of manufacturing an IC device according to an embodiment; and

fig. 15A to 15E are process sequence diagrams of a method of manufacturing an IC device according to an embodiment.

Detailed Description

Fig. 1 illustrates a layout of major components of a memory cell array region of an Integrated Circuit (IC) device 10 according to an embodiment.

Referring to fig. 1, the IC device 10 may include a plurality of active regions ACT, which may be spaced apart from each other. The plurality of active regions ACT may be arranged at an angle to each of the X direction and the Y direction on the plane, and extend in the horizontal direction. A plurality of word lines WL may cross the plurality of active regions ACT and extend parallel to each other in the X direction. The plurality of bit lines BL may be located on the plurality of word lines WL and extend parallel to each other in a Y direction crossing the X direction. The plurality of bit lines BL may be connected to the plurality of active regions ACT through one or more direct contacts DC.

A plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. A plurality of conductive landing (1) pads LP may be formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of conductive landing pads LP may be used to connect the lower electrodes of the capacitors formed on the plurality of bit lines BL with the active region ACT. At least a portion of each of the plurality of conductive landing pads LP may overlap the buried contact BC in a vertical direction.

Next, a configuration of an IC device according to an example embodiment will be described with reference to fig. 2A to 11. Each of the IC devices shown in fig. 2A through 11 may have the layout of the IC device 10 shown in fig. 1. In fig. 2A, 3A, 4A, 5A, 7A, 8A, 9A, and 10A, (a) is a sectional view of some components of a portion corresponding to a section taken along line a-a 'of fig. 1, (B) is a sectional view of some components of a portion corresponding to a section taken along line B-B' of fig. 1, and (c) is an enlarged sectional view of a portion corresponding to a dotted-line area indicated by "X1" in (a).

Fig. 2A shows a cross-sectional view of the IC device 100 according to the embodiment, and fig. 2B is an enlarged plan view of a partial region in fig. 2A.

Referring to fig. 2A and 2B, the IC device 100 may include a substrate 110 in which a plurality of active regions ACT are defined by device isolation films 112 in the substrate 110. The device isolation film 112 may be formed in a device isolation trench T1 formed in the substrate 110.

The substrate 110 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 110 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may include conductive regions, such as doped wells or doped structures.

A plurality of word line trenches T2 may be formed in the substrate 110 and extend in the first horizontal direction (X direction), and a plurality of gate dielectric films 116, a plurality of word lines 118, and a buried insulating film 120 may be formed within the plurality of word line trenches T2. The plurality of word lines 118 may correspond to the plurality of word lines WL shown in fig. 1.

A first insulating film 122 and a second insulating film 124 may be sequentially formed on the substrate 110. The first insulating film 122 and the second insulating film 124 may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the first insulating film 122 may include silicon oxide, and the second insulating film 124 may include silicon nitride. A plurality of bit lines BL may be formed on the second insulating film 124 and extend parallel to each other in the second horizontal direction (Y direction).

The direct contact DC may be formed on a local region of each of the plurality of active regions ACT. Each of the plurality of bit lines BL may be connected to the active region ACT through a direct contact DC. In some embodiments, the direct contact DC may include silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof. Thus, the direct contact DC may comprise a metallic and/or semiconducting material. In some embodiments, the direct contact DC may include an epitaxial silicon layer.

The plurality of bit lines BL may include a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134 sequentially formed on the substrate 110. Each of the plurality of bit lines BL may be covered by an insulating cap pattern 136. The top surface of the lower conductive layer 130 may be coplanar with the top surface of the direct contact DC. Although fig. 2A illustrates an example in which each of the plurality of bit lines BL has a three-layer structure including a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134, the inventive concept is not limited thereto. For example, each of the plurality of bit lines BL may be formed in a single layer, a double layer, or a multi-layer stack structure including at least four layers.

In some embodiments, the lower conductive layer 130 may include conductive polysilicon. Each of the middle conductive layer 132 and the upper conductive layer 134 may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide, or a combination thereof. For example, the middle conductive layer 132 may include TiN and/or TiSiN, and the upper conductive layer 134 may include W. The insulating capping pattern 136 may include a silicon nitride film.

A plurality of contact plugs 150 may be formed in spaces between the respective bit lines BL. Each of the plurality of contact plugs 150 may have a pillar shape extending upward in a vertical direction (Z direction) from the substrate 110. A bottom (i.e., lower) portion 150B of each of the plurality of contact plugs 150 may contact the active region ACT. The bottom 150B of each of the plurality of contact plugs 150 may be located at a lower level than the top surface of the substrate 110 and buried in the substrate 110. For example, the bottom 150B of the contact plug 150 may be lower than an upper portion of the contact plug 150 adjacent to the bit line BL (e.g., an upper portion between two bit lines BL). The plurality of contact plugs 150 may include a doped semiconductor material, a metal, a conductive metal nitride, or a combination thereof, but is not limited thereto.

In the IC device 100, one direct contact DC and a pair of contact plugs 150 facing each other with the direct contact DC therebetween may be connected to different corresponding active regions AC among the plurality of active regions AC.

The plurality of insulating fences (funce) 148 and the plurality of contact plugs 150 may be alternately arranged one by one between a pair of bit lines BL along a straight line parallel to a direction (Y direction) in which the bit lines BL extend. The plurality of contact plugs 150 may be insulated from each other by a plurality of insulating fences 148. Each of the plurality of insulating fences 148 may have a columnar shape extending in the vertical direction (Z direction) from the substrate 110. In some embodiments, the plurality of insulating rails 148 can include a silicon nitride film, but is not limited thereto.

The IC device 100 may include a boron (B) -containing insulating fill pattern 140P between the contact plug 150 and the direct contact DC. The boron-containing insulating fill pattern 140P may be in DC contact with the bottom 150B of the contact plug 150 and the direct contact. At least a portion of the boron-containing insulating fill pattern 140P may be buried in the substrate 110. The bottom height of the boron-containing insulating fill patterns 140P may be lower than the top height of the substrate 110, and the top height of the boron-containing insulating fill patterns 140P may be equal to or higher than the top height of the substrate 110. However, the pattern 140P does not necessarily completely fill a specific region, and thus may be referred to as a "boron-containing insulating pattern" herein.

The boron-containing insulating fill pattern 140P may have a dielectric constant of about 2 to 6. For example, the boron-containing insulating fill pattern 140P may have a dielectric constant of about 3 to 5. In some embodiments, the boron-containing insulating fill pattern 140P may include a silicon boron nitride (SiBN) film. The boron content of the SiBN film included in the boron-containing insulating fill pattern 140P may be about 10 atomic percent (at%) to about 50 at%. For example, the boron-containing insulating fill pattern 140P may include Si_xB_yN_z(x is more than or equal to 0.1 and less than or equal to 0.5, y is more than or equal to 0.1 and less than or equal to 0.5, and z is more than or equal to 0.1 and less than or equal to 0.8).

In the IC device 100, the boron-containing insulating fill pattern 140P having a relatively low dielectric constant may be interposed between the direct contact DC and the bottom 150B of the contact plug 150 adjacent to each other (i.e., there is no other direct contact DC or contact plug 150 between the direct contact DC and the contact plug 150). Accordingly, an undesired parasitic capacitance between the direct contact DC and the contact plug 150 may be reduced.

The IC device 100 may include a first insulating spacer 142S and a second insulating spacer 144 sequentially covering two (i.e., opposite) sidewalls of the plurality of bit lines BL. The first and second insulating spacers 142S and 144 may be interposed between the contact plug 150 and the bit line BL on the boron-containing insulating fill pattern 140P. The first and second insulating spacers 142S and 144 may include different respective materials. The first and second insulating spacers 142S and 144 may not include boron (i.e., may not include boron). In some embodiments, the first insulating spacer 142S may include a silicon oxide film, and the second insulating spacer 144 may include a silicon nitride film.

The first insulating spacer 142S may extend parallel to the bit line BL between the bit line BL and a plurality of contact plugs 150 linearly arranged in the Y direction, and the second insulating spacer 144 may extend parallel to the bit line BL between the bit line BL and a plurality of insulating fences 148 linearly arranged in the Y direction. Each of the plurality of contact plugs 150 linearly arranged in the Y direction may be spaced apart from the bit line BL with the first and second insulating spacers 142S and 144 therebetween. Further, each of the insulating fences 148 linearly arranged in the Y direction may be spaced apart from the bit line BL with the first insulating spacer 142S and the second insulating spacer 144 therebetween. The second insulating spacer 144 may include a portion having a U-shaped cross-sectional shape to cover two (i.e., opposite) sidewalls and a bottom surface of each of the plurality of insulating rails 148.

The metal silicide film 172 and the plurality of conductive landing pads LP may be sequentially formed on each of the plurality of contact plugs 150. The plurality of conductive landing pads LP may be connected to the plurality of contact plugs 150 through the metal silicide films 172, respectively. The plurality of conductive landing pads LP may extend from spaces between the plurality of insulating cap patterns 136 to the tops of the plurality of insulating cap patterns 136 and respectively overlap a portion of the plurality of bit lines BL in a vertical direction. Each of the plurality of conductive landing pads LP may include a conductive barrier film 174 and a conductive layer 176.

In some embodiments, the metal silicide film 172 may include cobalt silicide, nickel silicide, or manganese silicide, but is not limited thereto. In some embodiments, the metal silicide film 172 may be omitted. The conductive barrier film 174 may have a Ti/TiN stack structure. Conductive layer 176 may include doped polysilicon, metal silicide, conductive metal nitride, or combinations thereof. For example, the conductive layer 176 may include tungsten (W). The plurality of conductive landing pads LP may have a plurality of island pattern shapes when viewed from above. The plurality of conductive landing pads LP may be electrically insulated from each other by the insulating film 180 filling the space around the plurality of conductive landing pads LP.

Fig. 3A shows a cross-sectional view of an IC device 100A according to an embodiment, and fig. 3B is an enlarged plan view of a partial region in fig. 3A. In fig. 3A and 3B, the same reference numerals as in fig. 2A and 2B are used to denote the same elements, and are not described again.

Referring to fig. 3A and 3B, the IC device 100A may have substantially the same configuration as the IC device 100 shown in fig. 2A and 2B. However, the IC device 100A may include air spacers AS1 instead of the first insulating spacers 142S. The term "air" as used herein may refer to other gases that may be present in the atmosphere or during the manufacturing process. The air spacer AS1 may include a portion whose bottom is defined by the boron-containing insulating fill pattern 140P and a portion whose bottom is defined by the second insulating film 124.

Fig. 4A illustrates a cross-sectional view of an IC device 200 according to an embodiment, and fig. 4B is an enlarged plan view of a partial region in fig. 4A. In fig. 4A and 4B, the same reference numerals as in fig. 2A and 2B are used to denote the same elements, and are not described again.

Referring to fig. 4A and 4B, the IC device 200 may have substantially the same configuration as the IC device 100 shown in fig. 2A and 2B. However, the IC device 200 may include an inter-insulating film 242 surrounding a portion of the boron-containing insulating fill pattern 140P.

The inner insulating film 242 may conformally cover the direct contact portion DC, the plurality of bit lines BL, and the sidewalls of each of the plurality of insulating cap patterns 136, and the bottom surface and sidewalls of the boron-containing insulating fill pattern 140P. The internal insulating film 242 may be interposed between the bit line BL and the first insulating spacer 142S. The inner insulating film 242, the first insulating spacer 142S, and the second insulating spacer 144, which may be sequentially located on the sidewall of the bit line BL, may be interposed between the bit line BL and the contact plug 150 and between the bit line BL and the insulating fence 148.

The boron-containing insulating fill pattern 140P may be spaced apart from the direct contact DC and the contact plug 150 with the inter-insulating film 242 therebetween. The portion of the inner insulating film 242 surrounding the boron-containing insulating fill pattern 140P may constitute an interstitial insulating film/region. The gap insulating films/regions as a part of the inter-insulating film 242 may be interposed between the bottoms 150B of the plurality of contact plugs 150 and the boron-containing insulating fill pattern 140P and between the direct contact portion DC and the boron-containing insulating fill pattern 140P. The gap insulating film/region may have a dielectric constant lower than that of the boron-containing insulating fill pattern 140P.

The internal insulation film 242 and the boron-containing insulation filling pattern 140P may include materials having etch selectivity with respect to each other. In some embodiments, the internal insulation film 242 may include a silicon oxide film.

In the IC device 200, the boron-containing insulating fill pattern 140P and the internal insulating film 242 having a relatively low dielectric constant may be interposed between the direct contact portion DC and the bottom portion 150B of the contact plug 150 adjacent to each other. Accordingly, an undesired parasitic capacitance between the direct contact DC and the contact plug 150 may be reduced.

Fig. 5A illustrates a cross-sectional view of an IC device 200A according to an embodiment, and fig. 5B is an enlarged plan view of a partial region in fig. 5A. In fig. 5A and 5B, the same reference numerals as in fig. 4A and 4B are used to denote the same elements, and are not described again.

Referring to fig. 5A and 5B, the IC device 200A may have substantially the same configuration as the IC device 200 shown in fig. 4A and 4B. However, the IC device 200A may include the air spacer AS21 that may be disposed between the bit line BL and the second insulation spacer 144 and the inner insulation film 242G1 that may surround a portion of the boron-containing insulation filling pattern 140P at a lower height than the air spacer AS 21.

The internal insulation film 242G 1and the boron-containing insulation filling pattern 140P may include materials having etch selectivity with respect to each other. In some embodiments, the internal insulation film 242G1 may include a silicon oxide film.

The air spacer AS21 may include a portion whose bottom is defined by the boron-containing insulating fill pattern 140P and the internal insulation film 242G 1and a portion whose bottom is defined by the second insulation film 124. The air spacer AS21 may include a gap air (i.e., air gap) portion G21 that may extend toward the substrate 110 between the direct contact DC and the boron-containing insulating fill pattern 140P.

In the IC device 200A, the internal insulating film 242G 1and the gap air portion G21 may constitute a gap insulating film/region. In the IC device 200A, the boron-containing insulating fill pattern 140P having a relatively low dielectric constant, the gap air portion G21 of the air spacer AS21, and the internal insulating film 242G1 may be interposed between the direct contact DC and the bottom 150B of the contact plug 150 adjacent to each other. An undesirable parasitic capacitance between the direct contact DC and the contact plug 150 can be reduced.

Fig. 6 is a cross-sectional view of an IC device 200B according to an embodiment. Fig. 6 is an enlarged sectional view of other components of a portion corresponding to a broken line region indicated by "X1" in (a) of fig. 5A. In fig. 6, the same reference numerals as in fig. 5A and 5B are used to denote the same elements, and are not described again.

Referring to fig. 6, an IC device 200B may have substantially the same configuration as the IC device 200 shown in fig. 4A and 4B. However, the IC device 200B may include the air spacer AS22 disposed between the bit line BL and the second insulation spacer 144 and the inter-insulating film 242G2 interposed between the boron-containing insulation filling pattern 140P and the bottom 150B of the contact plug 150.

The internal insulation film 242G2 and the boron-containing insulation filling pattern 140P may include materials having etch selectivity with respect to each other. In some embodiments, the internal insulation film 242G2 may include a silicon oxide film.

Air spacer AS22 may extend into substrate 110 from the space between bit line BL and second insulating spacer 144. The air spacer AS22 may include a gap air portion G22, and the gap air portion G22 may extend between the direct contact DC and the boron-containing insulation filling pattern 140P and between the boron-containing insulation filling pattern 140P and the bottom 150B of the contact plug 150, and surround the boron-containing insulation filling pattern 140P. The gap air portion G22 of the air spacer AS22 may surround the sidewalls and the bottom surface of the boron-containing insulating fill pattern 140P. Air spacer AS22 may include a portion whose bottom is defined by second insulating film 124. In the IC device 200B, the internal insulating film 242G2 and the gap air portion G22 may constitute a gap insulating film/region.

In the IC device 200B, the boron-containing insulating fill pattern 140P having a relatively low dielectric constant, the gap air portion G22 of the air spacer AS22, and the internal insulating film 242G2 may be interposed between the direct contact DC and the bottom 150B of the contact plug 150 adjacent to each other. Accordingly, an undesired parasitic capacitance between the direct contact DC and the contact plug 150 may be reduced.

Fig. 7A shows a cross-sectional view of an IC device 300 according to an embodiment, and fig. 7B is an enlarged plan view of a partial region in fig. 7A. In fig. 7A and 7B, the same reference numerals as in fig. 2A and 2B are used to denote the same elements, and are not described again.

Referring to fig. 7A and 7B, the IC device 300 may have substantially the same configuration as the IC device 100 shown in fig. 2A and 2B. However, the IC device 300 may include a plurality of first insulating spacers 342S and a plurality of second insulating spacers 344 that may cover both (i.e., opposite) sidewalls of the plurality of bit lines BL.

As shown in fig. 7B, the plurality of first insulation spacers 342S and the plurality of second insulation spacers 344, each of which may have an annular (e.g., circular or rectangular) shape, may surround the circumference of the contact plug 150, respectively. Each of the plurality of first insulating spacers 342S and the plurality of second insulating spacers 344 may include a portion between the sidewalls of the contact plug 150 and the bit line BL on the boron-containing insulating filling pattern 140P and a portion configured to extend between the contact plug 150 and the insulating fence 348. The first insulating spacer 342S and the second insulating spacer 344 may not be interposed between the bit line BL and the insulating fence 348.

Between the bit line BL and the contact plug 150, the first insulating spacer 342S may have an L-shaped sectional shape, and the second insulating spacer 344 may be spaced apart from the second insulating film 124 with the first insulating spacer 342S therebetween.

Between the direct contact DC and the contact plug 150, the second insulation spacer 344 may be spaced apart from the boron-containing insulation filling pattern 140P with the first insulation spacer 342S therebetween.

In addition, the IC device 300 may further include a plurality of boron-containing insulating fences 140F that may be interposed between the bit line BL and a plurality of insulating fences 348 linearly arranged along the Y direction. The plurality of boron-containing insulation fences 140F may include the same material as the boron-containing insulation filling pattern 140P. Each of the plurality of boron-containing insulator rails 140F can have a U-shaped cross-sectional shape on (e.g., covering) two (i.e., opposing) side walls and a bottom surface of the insulator rail 348.

In some embodiments, each of the content of boron and the content of nitrogen in the boron-containing insulating fence 140F may be variable in the thickness direction of the boron-containing insulating fence 140F. For example, the boron content in the boron-containing insulating fence 140F may increase toward the bit line BL and may decrease toward the insulating fence 348. Further, the nitrogen content in the boron-containing insulating fence 140F may decrease toward the bit line BL, and may increase toward the insulating fence 348.

The detailed configuration of the first insulating spacer 342S, the second insulating spacer 344, and the insulating fence 348 may be substantially the same as the first insulating spacer 142S, the second insulating spacer 144, and the insulating fence 148 described with reference to fig. 2A and 2B.

Fig. 8A illustrates a cross-sectional view of an IC device 300A according to an embodiment, and fig. 8B is an enlarged plan view of a partial region in fig. 8A. In fig. 8A and 8B, the same reference numerals as in fig. 7A and 7B are used to denote the same elements, and are not described again.

Referring to fig. 8A and 8B, an IC device 300A may have substantially the same configuration as the IC device 300 shown in fig. 7A and 7B. However, the IC device 300A may include air spacers AS3 instead of the first insulating spacers 342S. Air spacer AS3 may have an annular shape and surround contact plug 150.

The air spacer AS3 may include a portion whose bottom is defined by the boron-containing insulating fill pattern 140P and a portion whose bottom is defined by the second insulating film 124. Between the bit line BL and the contact plug 150, the second insulating spacer 344 may be spaced apart from the second insulating film 124 with the air spacer AS3 therebetween. Between the direct contact DC and the contact plug 150, the second insulation spacer 344 may be spaced apart from the boron-containing insulation filling pattern 140P with the air spacer AS3 therebetween.

Fig. 9A illustrates a cross-sectional view of an IC device 400 according to an embodiment, and fig. 9B is an enlarged plan view of a partial region in fig. 9A. In fig. 9A and 9B, the same reference numerals as in fig. 2A to 7B are used to denote the same elements, and are not described again.

Referring to fig. 9A and 9B, the IC device 400 may have substantially the same configuration as the IC device 300 shown in fig. 7A and 7B. However, the IC device 400 may include the inner insulating film 242 configured to surround a portion of the boron-containing insulating fill pattern 140P. The detailed configuration of the internal insulation film 242 may be substantially the same as the configuration described with reference to fig. 4A and 4B. However, the inner insulating film 242 may be in contact with the boron-containing insulating fence 140F between the bit line BL and the insulating fence 348. The inner insulating film 242 may be spaced apart from the insulating fences 348 with the boron-containing insulating fence 140F therebetween. The boron-containing insulating rails 140F can have a U-shaped cross-sectional shape to cover two (i.e., opposing) sidewalls and a bottom surface of the insulating rail 148.

The internal insulating film 242 may be interposed between the bit line BL and the first insulating spacer 342S. Accordingly, the inter insulating film 242, the first insulating spacer 342S, and the second insulating spacer 344, which may be sequentially disposed on the sidewall of the bit line BL, may be interposed between the bit line BL and the contact plug 150. The inner insulating film 242 and the boron-containing insulating fence 140F, which may be sequentially disposed on the sidewall of the bit line BL, may be interposed between the bit line BL and the insulating fence 148.

Fig. 10A shows a cross-sectional view of an IC device 400A according to an embodiment, and fig. 10B is an enlarged plan view of a partial region in fig. 10A. In fig. 10A and 10B, the same reference numerals as in fig. 9A and 9B are used to denote the same elements, and are not described again.

Referring to fig. 10A and 10B, an IC device 400A may have substantially the same configuration as the IC device 400 shown in fig. 9A and 9B. However, the IC device 400A may include the air spacer AS41 disposed between the bit line BL and the second insulating spacer 344 and the inter-insulating film 242G4 that may surround a portion of the boron-containing insulating fill pattern 140P at a lower height than the air spacer AS 41.

The detailed configuration of the internal insulating film 242G4 may be substantially the same as that of the internal insulating film 242G1 described with reference to fig. 5A and 5B. The air spacer AS41 may include a portion whose bottom is defined by the boron-containing insulating fill pattern 140P and the internal insulation film 242G4 and a portion whose bottom is defined by the second insulation film 124. AS shown in fig. 10B, the air spacer AS41 may include a plurality of annular portions configured to surround the plurality of contact plugs 150 and a plurality of linear portions that may communicate (i.e., connect) with the plurality of annular portions and that are interposed between the bit line BL and the boron-containing insulating fence 140F.

The air spacer AS41 may include a gap air portion G41 that may extend toward the substrate 110 between the direct contact DC and the boron-containing insulating fill pattern 140P. In the IC device 400A, the internal insulating film 242G4 and the gap air portion G41 may constitute a gap insulating film/region.

In the IC device 400A, the boron-containing insulating fill pattern 140P having a relatively low dielectric constant, the gap air portion G41 of the air spacer AS41, and the internal insulating film 242G4 may be interposed between the direct contact DC and the bottom 150B of the contact plug 150 adjacent to each other. Accordingly, an undesired parasitic capacitance between the direct contact DC and the contact plug 150 may be reduced.

Fig. 11 is a cross-sectional view of an IC device 400B according to an embodiment. Fig. 11 is an enlarged sectional view of other components of a portion corresponding to a broken line region indicated by "X1" in (a) of fig. 10A. In fig. 11, the same reference numerals as in fig. 10A and 10B are used to denote the same elements, and are not described again.

Referring to fig. 11, an IC device 400B may have substantially the same configuration as the IC device 400 shown in fig. 9A and 9B. However, the IC device 400B may include the air spacer AS42 disposed between the bit line BL and the second insulation spacer 344 and the inter-insulating film 242G5 interposed between the boron-containing insulation filling pattern 140P and the bottom 150B of the contact plug 150. In some embodiments, the internal insulation film 242G5 may include a silicon oxide film.

An air spacer AS42 may extend into the substrate 110 from the space between the bitline BL and the second insulating spacer 344. The air spacer AS42 may include a gap air portion G42, and the gap air portion G42 may extend between the direct contact DC and the boron-containing insulation filling pattern 140P and between the boron-containing insulation filling pattern 140P and the bottom 150B of the contact plug 150, and may surround the boron-containing insulation filling pattern 140P. The gap air portion G42 of the air spacer AS42 may surround the sidewalls and the bottom surface of the boron-containing insulating fill pattern 140P. Air spacer AS42 may include a portion whose bottom is defined by second insulating film 124. In the IC device 400B, the internal insulating film 242G5 and the gap air portion G42 may constitute a gap insulating film/region.

In the IC device 400B, the boron-containing insulating fill pattern 140P having a relatively low dielectric constant, the gap air portion G42 of the air spacer AS42, and the internal insulating film 242G5 may be interposed between the direct contact DC and the bottom 150B of the contact plug 150 adjacent to each other, thereby reducing an undesired parasitic capacitance between the direct contact DC and the contact plug 150.

Fig. 12A to 12N are process sequence diagrams of a method of manufacturing an IC device according to an embodiment. In fig. 12A to 12N, (a) is a cross-sectional view of some components of a portion corresponding to a cross-section taken along line a-a 'of fig. 1 according to a process sequence, and (B) is a cross-sectional view of some components of a portion corresponding to a cross-section taken along line B-B' of fig. 1 according to a process sequence. In fig. 12G to 12K, (c) is an enlarged sectional view of a portion corresponding to a broken line region indicated by "X2" in (a) of the respective drawings. In fig. 12L and 12M, (c) is an enlarged plan view of a partial region in the respective drawings. A method of manufacturing the IC device 100 shown in fig. 2A and 2B according to some example embodiments will now be described with reference to fig. 12A to 12N.

Referring to fig. 12A, a device isolation trench T1 may be formed in a substrate 110, and a device isolation film 112 may be formed within the device isolation trench T1.

A plurality of active regions ACT may be defined in the substrate 110 by the device isolation films 112. The device isolation film 112 may include an oxide film, a nitride film, or a combination thereof.

A plurality of word line trenches T2 may be formed in the substrate 110. The plurality of word line trenches T2 may extend parallel to each other in the X direction and have a linear shape crossing the active region ACT. To form the plurality of word line trenches T2 having stepped bottom surfaces, each of the device isolation film 112 and the substrate 110 may be etched using a separate etching process, so that the etching depth of the device isolation film 112 may be different from the etching depth of the substrate 110. The resulting structure including the plurality of word line trenches T2 may be cleaned, and the gate dielectric film 116, the word line 118, and the buried insulating film 120 may be sequentially formed in each of the plurality of word line trenches T2. Before or after the plurality of word lines 118 are formed, an ion implantation process may be performed to form a plurality of source and drain regions in upper portions of the plurality of active regions ACT.

The gate dielectric film 116 may comprise a material selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide/nitride/oxide (ONO), or an inter-layerAt least one selected from high-k dielectric films having a higher electrical constant than the silicon oxide film. The high-k dielectric film may include hafnium oxide (HfO)₂) Alumina (Al)₂O₃) Hafnium aluminum oxide (HfAlO)₃) Tantalum oxide (Ta)₂O₃) Titanium oxide (TiO)₂) Or a combination thereof. The plurality of word lines 118 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. The plurality of buried insulating films 120 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

A first insulating film 122 and a second insulating film 124 may be sequentially formed on the substrate 110. The first and second insulating films 122 and 124 may be formed to cover top surfaces of the plurality of active regions ACT, top surfaces of the device isolation films 112, and top surfaces of the plurality of buried insulating films 120. In some embodiments, the first insulating film 122 may include a silicon oxide film, and the second insulating film 124 may include a silicon nitride film, but they are not limited thereto.

Referring to fig. 12B, a lower conductive layer 130 may be formed on the second insulating film 124. The lower conductive layer 130 may include doped polysilicon.

Referring to fig. 12C, a mask pattern MP1 may be formed on the lower conductive layer 130, and then the lower conductive layer 130 exposed through an opening MH of the mask pattern MP1 may be etched to expose a portion of the substrate 110 and a portion of the device isolation film 112. The exposed portion of the substrate 110 and the exposed portion of the device isolation film 112 may be etched to form a direct contact hole DCH exposing the active region ACT of the substrate 110. The mask pattern MP1 may include an oxide film, a nitride film, or a combination thereof.

Referring to fig. 12D, the mask pattern MP1 may be removed from the resultant structure of fig. 12C, and a direct contact portion DC may be formed within the direct contact hole DCH.

In order to form the direct contact portion DC, a conductive layer having a thickness sufficient to fill the direct contact hole DCH may be formed in the direct contact hole DCH and on the lower conductive layer 130, and an unnecessary/unnecessary portion of the conductive layer may be removed so that the conductive layer may remain only in the direct contact hole DCH.

Referring to fig. 12E, an intermediate conductive layer 132, an upper conductive layer 134, and a plurality of insulating capping patterns 136 may be sequentially formed on the lower conductive layer 130 and the direct contact DC. Each of the plurality of insulation cap patterns 136 may include a line pattern extending in the Y direction.

Referring to fig. 12F, portions of each of the upper conductive layer 134, the middle conductive layer 132, the lower conductive layer 130, and the direct contact DC may be etched using the insulating cap pattern 136 as an etching mask, thereby forming a plurality of bit lines BL on the substrate 110. The plurality of bit lines BL may include respective remaining portions of the lower conductive layer 130, the middle conductive layer 132, and the upper conductive layer 134. After the plurality of bit lines BL are formed, a portion of the direct contact hole DCH may be exposed in the vicinity of the direct contact portion DC, and a line-shaped space LS may be defined between a plurality of bit line structures each including the bit line BL and the insulating cap pattern 136 and may be elongated in the Y direction.

Referring to fig. 12G, a boron-containing insulating film 140 may be formed to fill the remaining space of the direct contact hole DCH and cover the sidewalls of each of the plurality of bit lines BL, the plurality of insulating cap patterns 136, and the plurality of direct contacts DC. The remaining space of the direct contact hole DCH may be completely filled with the boron-containing insulating film 140 in the vicinity of the direct contact portion DC.

The boron-containing insulating film 140 may have a dielectric constant of about 2 to 6. For example, the boron-containing insulating film 140 may have a dielectric constant of 3 to 5. In some embodiments, the boron-containing insulating film 140 may include a SiBN film. The boron content of the SiBN film included in the boron-containing insulating film 140 may be about 10 atomic percent (at%) to about 50 at%. For example, the boron-containing insulating film 140 may include Si_xB_yN_z(x is more than or equal to 0.1 and less than or equal to 0.5, y is more than or equal to 0.1 and less than or equal to 0.5, and z is more than or equal to 0.1 and less than or equal to 0.8).

The boron-containing insulating film 140 may be formed using a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. For example, the boron-containing insulating film 140 may be formed using a plasma enhanced cvd (pecvd) process, a plasma pulse cvd (picvd) process, or a plasma enhanced ald (peald) process. The boron-containing insulating film 140 including the SiBN film may be formed using a plasma deposition process so that boron (B) atoms may remain strongly bonded with nitrogen (N) atoms in the SiBN film.

In some embodiments, in order to form the boron-containing insulating film 140 including the SiBN film, a reaction between a silicon source and a nitrogen source may be caused in an atmosphere of a boron precursor. Diborane (B)₂H₆) Borazine (B)₃N₃H₆) Or a borazine derivative substituted with an alkyl group may be used as the boron precursor. Silane (SiH) may be used₄) Or SiCl₄Gas is used as a silicon source, and ammonia (NH) may be used₃) Gas is used as nitrogen source. However, these precursors and gas sources are merely examples, and the inventive concept is not limited thereto.

In some embodiments, the boron content in the boron-containing insulating film 140 may be constant in the thickness direction of the boron-containing insulating film 140. In some embodiments, the boron content in the boron-containing insulating film 140 may vary in the thickness direction of the boron-containing insulating film 140.

The boron content or boron concentration of the boron-containing insulating film 140 can be controlled by adjusting the flow rate of the boron precursor during the formation of the boron-containing insulating film 140. In some embodiments, the boron content in the boron-containing insulating film 140 may vary in the thickness direction of the boron-containing insulating film 140. For example, the boron content in the boron-containing insulating film 140 may increase toward the bottom surface of the boron-containing insulating film 140 (i.e., toward the inner wall of the direct contact hole DCH and the side wall of the direct contact portion DC) and decrease toward the top surface of the boron-containing insulating film 140. The boron content in the boron-containing insulating film 140 may be highest in a portion in contact with the inner wall of the direct contact hole DCH and a portion in contact with the direct contact portion DC, and may be lowest in a surface exposed in the line space LS. Further, in a portion of the boron-containing insulating film 140 covering the sidewall of the bit line BL, the boron content in the boron-containing insulating film 140 may increase toward the bit line BL and decrease toward the surface exposed in the line-shaped space LS. Further, in the portion of the boron-containing insulating film 140 covering the sidewall of the bit line BL, the nitrogen content in the boron-containing insulating film 140 may decrease toward the bit line BL, and may decrease toward the surface exposed in the line-shaped space LS.

In some embodiments, in order to form the boron-containing insulating film 140 including the SiBN film, the flow rate of the boron precursor may be controlled to be relatively high in the initial stage of the process of depositing the boron-containing insulating film 140. As the process of depositing the boron-containing insulating film 140 proceeds, the flow rate of the boron precursor may be gradually decreased, and the flow rate of the nitrogen source may be gradually increased. Therefore, since the boron content of the boron-containing insulating film 140 increases toward the bottom surface of the boron-containing insulating film 140, the dielectric constant of the boron-containing insulating film 140 can be decreased toward the bottom surface. In contrast, since the boron content of the boron-containing insulating film 140 decreases toward the top surface of the boron-containing insulating film 140, the dielectric constant of the boron-containing insulating film 140 may increase toward the top surface. However, since the nitrogen content of the boron-containing insulating film 140 increases toward the top surface of the boron-containing insulating film 140, the dry etching resistance may increase toward the top surface of the boron-containing insulating film 140. Therefore, when a dry etching process of removing a part of the structure exposed through the plurality of contact spaces CS is performed to form the plurality of recess spaces R1 as described below with reference to fig. 12L, even if the boron-containing insulating fill pattern 140P formed using the boron-containing insulating film 140 is exposed to a dry etching atmosphere, it is possible to suppress/prevent the boron-containing insulating fill pattern 140P from being undesirably consumed due to the dry etching atmosphere.

Referring to fig. 12H, the boron-containing insulating film 140 may be isotropically etched from the resultant structure of fig. 12G, thereby forming boron-containing insulating fill patterns 140P, the boron-containing insulating fill patterns 140P including the remaining portions (after etching) of the boron-containing insulating film 140.

In some embodiments, the isotropic etching process may be performed using phosphoric acid, sulfuric acid, a combination of phosphoric acid and sulfuric acid, a mixture of phosphoric acid and deionized water (DIW), a mixture of sulfuric acid and DIW, a mixture of phosphoric acid and fluorine acid, or a mixture of sulfuric acid and fluorine acid. The boron-containing insulating fill pattern 140P may include a portion where the boron-containing insulating film 140 is filled within the direct contact hole DCH and a portion where an entrance of the direct contact hole DCH is covered outside an entrance of the direct contact hole DCH.

Referring to fig. 121, a first insulating spacer layer 142 may be formed to conformally cover respective exposed surfaces of the plurality of bit lines BL, the plurality of insulating cap patterns 136, and the boron-containing insulating fill pattern 140P. The first insulating spacer layer 142 may include a material having an etch selectivity with respect to the boron-containing insulating fill pattern 140P. For example, the first insulating spacer layer 142 may include a silicon oxide film. The first insulating spacer layer 142 may be formed using a CVD process or an ALD process.

Referring to fig. 12J, the first insulating spacer layer 142 may be anisotropically etched from the resultant structure of fig. 12I to form a plurality of first insulating spacers 142S. Each of the plurality of first insulating spacers 142S may cover sidewalls of the bit line BL and sidewalls of the insulating cap pattern 136 on the boron-containing insulating fill pattern 140P and the second insulating film 124. After the plurality of first insulation spacers 142S are formed, a portion of the boron-containing insulation filling pattern 140P may be exposed again.

Referring to fig. 12K, second insulating spacers 144 may be formed to conformally cover the resulting structure of fig. 12J. The second insulation spacer 144 may include a material having an etch selectivity with respect to each of the first insulation spacer layer 142 and the boron-containing insulation filling pattern 140P. For example, the second insulation spacer 144 may include a silicon nitride film. The second insulating spacers 144 may be formed using a CVD process or an ALD process.

Referring to fig. 12L, a plurality of insulating fences 148 may be formed between the respective bit lines BL and spaced apart from each other such that a line-shaped space LS defined by the second insulating spacer 144 may be divided into a plurality of contact spaces CS.

Each of the plurality of insulating fences 148 may be formed to overlap the word line 118 in the vertical direction on the word line 118. The plurality of insulating rails 148 can include a silicon nitride film. In some embodiments, a portion of the plurality of insulation cap patterns 136 may be consumed during the formation of the plurality of insulation fences 148, thereby reducing the height of the plurality of insulation cap patterns 136.

Thereafter, a portion of the structure exposed through the plurality of contact spaces CS may be removed, thereby forming a plurality of recess spaces R1 exposing the active region ACT of the substrate 110 between the respective bit lines BL.

The plurality of depression spaces R1 may be formed using an anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process. For example, in a structure in which the respective bit lines BL are exposed through the plurality of contact spaces CS, the second insulating spacer 144, the second insulating film 124, and the first insulating film 122 may be anisotropically etched sequentially. As a result, a portion of the active region ACT of the substrate 110 may be exposed, and the exposed portion of the active region ACT may be etched to form the plurality of recess spaces R1. The plurality of depression spaces R1 may communicate with (i.e., connect to) the contact space CS, respectively. The active region ACT and the boron-containing insulating fill pattern 140P of the substrate 110 may be exposed through the plurality of recess spaces R1.

Referring to fig. 12M, a plurality of contact plugs 150 may be formed between the respective bit lines BL to fill the plurality of recess spaces R1 and a portion of the plurality of contact spaces CS between the respective bit lines BL.

A vertical distance from the top surface of the substrate 110 to the top surface of each of the plurality of contact plugs 150 may be greater than a vertical distance from the top surface of the substrate 110 to the top surface of each of the plurality of bit lines BL.

Referring to fig. 12N, a metal silicide film 172 and a plurality of conductive landing pads LP may be sequentially formed on the plurality of contact plugs 150 exposed through the plurality of contact spaces CS (see fig. 12M).

The contact plug 150 and the metal silicide film 172 may constitute at least a portion of the buried contact BC shown in fig. 1. The plurality of conductive landing pads LP may extend to an upper portion of the insulating capping pattern 136 to fill the plurality of contact spaces CS on the metal silicide film 172 and overlap a portion of the plurality of bit lines BL in a vertical direction. The plurality of conductive landing pads LP may include a conductive barrier film 174 and a conductive layer 176.

In order to form the plurality of conductive landing pads LP, the conductive barrier film 174 and the conductive layer 176 may be formed on the entire surface of the resultant structure including the metal silicide film 172. Thereafter, a mask pattern may be formed on the conductive layer 176 to expose a portion of the conductive layer 176. The conductive layer 176, the conductive barrier film 174, and the insulating film in the vicinity thereof may be etched using the mask pattern as an etching mask, thereby forming the upper recess space R2. The mask pattern may include a silicon nitride film, but is not limited thereto.

The plurality of conductive landing pads LP may be formed in a plurality of island patterns. The portions of the plurality of conductive landing pads LP extending in the horizontal direction outside the contact space CS may constitute the plurality of conductive landing pads LP shown in fig. 1.

The upper recess space R2 may be filled with the insulating film 180 in the vicinity of the plurality of conductive landing pads LP so that the plurality of conductive landing pads LP may be electrically insulated from each other. Thereafter, a plurality of capacitor lower electrodes may be formed on the insulating film 180 and may be electrically connected to the plurality of conductive landing pads LP.

To manufacture the IC device 100A shown in fig. 3A and 3B, a plurality of conductive landing pads LP may be formed using the process described with reference to fig. 12N. Thereafter, the plurality of first insulating spacers 142S may be removed through the upper recess space R2 using a wet etching process before the upper recess space R2 is filled with the insulating film 180. Accordingly, an air spacer AS1 may be formed between the bit line BL and the second insulating spacer 144.

Fig. 13A to 13D are cross-sectional views showing a process sequence of a method of manufacturing an IC device according to an embodiment. In fig. 13A to 13D, (a) is a sectional view of some components of a portion corresponding to a section taken along line a-a 'of fig. 1 according to a process sequence, (B) is a sectional view of some components of a portion corresponding to a section taken along line B-B' of fig. 1 according to a process sequence, and (c) is an enlarged sectional view of a portion corresponding to a dotted line region indicated by "X2" in (a) of the respective drawings. A method of manufacturing the IC device shown in fig. 4A and 4B according to some example embodiments will be described with reference to fig. 13A to 13D. In fig. 13A to 13D, the same reference numerals as in fig. 4A, 4B, and 12A to 12N are used to denote the same elements, and are not described again.

Referring to fig. 13A, the process described with reference to fig. 12A to 12F may be performed to form a plurality of bit lines BL on the substrate 110. Thereafter, an internal insulating film 242 may be formed to conformally cover the plurality of bit lines BL, the plurality of insulating capping patterns 136, the exposed surfaces of the respective direct contacts DC, the inner walls of the direct contact holes DCH, and the top surface of the second insulating film 124.

Subsequently, the boron-containing insulating film 140 may be formed on the inner insulating film 242 using a method similar to that described with reference to fig. 12G. The remaining space of the direct contact hole DCH may be completely filled with the boron-containing insulating film 140 in the vicinity of the direct contact portion DC. The thickness of the internal insulating film 242 may be smaller than that of the boron-containing insulating film 140.

Referring to fig. 13B, the boron-containing insulating film 140 may be isotropically etched from the resultant structure of fig. 13A using a method similar to that described with reference to fig. 12H, thereby forming boron-containing insulating fill patterns 140P, the boron-containing insulating fill patterns 140P including the remaining portions (after etching) of the boron-containing insulating film 140. The boron-containing insulating fill pattern 140P may be separated from the direct contact DC with the inter-insulating film 242 therebetween.

Referring to fig. 13C, a plurality of first insulating spacers 142S may be formed on the boron-containing insulating fill pattern 140P and the inter-insulating film 242 to cover sidewalls of the bit lines BL and sidewalls of the insulating cap patterns 136 using a method similar to that described with reference to fig. 12I and 12J. The plurality of first insulating spacers 142S may be separated from the bit line BL and the insulating capping pattern 136 with the inter-insulating film 242 therebetween.

As described with reference to fig. 12J, the plurality of first insulating spacers 142S may be formed by anisotropically etching the first insulating spacer layer 142. Thereafter, the portions of the inter-insulating film 242 covering the top surfaces of the insulating cap patterns 136 and exposed on the bottoms of the plurality of line-shaped spaces LS may be successively etched to expose the top surfaces of the insulating cap patterns 136, the top surfaces of the second insulating film 124, and the top surfaces of the boron-containing insulating fill patterns 140P.

Referring to fig. 13D, the following may be performed on the resulting structure of fig. 13C: the process described with reference to fig. 12K to 12N. Accordingly, the second insulating spacer 144 may be formed to cover the plurality of first insulating spacers 142S, the plurality of insulating rails 148, the plurality of contact plugs 150, the plurality of metal silicide films 172, and the plurality of conductive landing pads LP may be formed, and the insulating film 180 may be formed to fill the upper recess space R2. Accordingly, the IC device 200 shown in fig. 4A and 4B can be manufactured.

In order to manufacture the IC device 200A shown in fig. 5A and 5B and the IC device 200B shown in fig. 6, after the plurality of conductive landing pads LP are formed using the process described with reference to fig. 13D and before the upper recess space R2 is filled with the insulating film 180, the plurality of first insulating spacers 142S and the inner insulating film 242 may be removed through the upper recess space R2 using a wet etching process, so that the air spacer AS21 may be formed between the bit line BL and the second insulating spacer 144. During the wet etching process for forming the air spacer AS21, a portion of the inter-insulating film 242 interposed between the direct contact DC and the boron-containing insulating fill pattern 140P may be removed, so that the gap air portion G21 shown in fig. 5A may be formed and the inter-insulating film 242G1 may remain in the vicinity of the boron-containing insulating fill pattern 140P. In addition, the amount of removal of the inter-insulating film 242 interposed between the direct contact DC and the boron-containing insulating fill pattern 140P may be adjusted during the wet etching process, so that the air spacer AS22 including the gap air portion G22 and the inter-insulating film 242G2 may remain AS in the IC device 200B shown in fig. 6.

Fig. 14A to 14E are process sequence diagrams of a method of manufacturing an IC device according to an embodiment. In fig. 14A to 14E, (a) is a cross-sectional view of some components of a portion corresponding to a cross-section taken along line a-a 'of fig. 1 according to a process sequence, and (B) is a cross-sectional view of some components of a portion corresponding to a cross-section taken along line B-B' of fig. 1 according to a process sequence. In fig. 14B, 14D, and 14E, (c) is an enlarged plan view of a partial region in the corresponding drawing. A method of manufacturing the IC device 300 shown in fig. 7A and 7B according to some example embodiments will be described with reference to fig. 14A to 14E. In fig. 14A to 14E, the same reference numerals as in fig. 7A, 7B, and 12A to 12N are used to denote the same elements, and are not described again.

Referring to fig. 14A, the process described with reference to fig. 12A to 12G may be performed to form the boron-containing insulating film 140 on the substrate 110. Thereafter, an interlayer insulating film 340 may be formed to fill the line-shaped spaces LS between a plurality of bit line structures, each including the bit line BL and the insulating cap pattern 136.

In some embodiments, the interlayer insulating film 340 may include a silicon oxide film. In the process of forming the interlayer insulating film 340 according to the embodiment, a polysilazane-based insulating film may be formed using a CVD process or a spin-on-glass (SOG) coating process to fill the line-shaped spaces LS (see fig. 12G). Thereafter, the polysilazane-based insulating film may be annealed at a temperature of about 300 ℃ to about 600 ℃ and densified due to a cross-linking reaction of a silicon-oxygen-silicon (Si-O-Si) network, thereby forming a silicon oxide film. The boron-containing insulating film 140 may serve to suppress/prevent oxidation of the plurality of bit lines BL during annealing of the polysilazane-based insulating film.

Referring to fig. 14B, a planarization process may be performed on the top surface of the resultant structure of fig. 14A, so that respective portions of the interlayer insulating film 340 and the boron-containing insulating film 140 may be removed and the top surface of each of the insulating cap patterns 136 may be exposed. Next, a part of the interlayer insulating film 340 may be removed to empty a local region of the line-shaped space LS between the respective bit lines BL. Thereafter, a plurality of insulating fences 348 can be formed to fill the emptied local regions of the linear space LS.

Referring to fig. 14C, the interlayer insulating film 340 remaining between the plurality of bit lines BL may be removed from the resultant structure of fig. 14B, so that the contact space CS may be prepared between the respective insulating fences 348. The boron-containing insulating film 140 may be exposed through a plurality of contact spaces CS defined by the plurality of insulating fences 348 between the respective bit lines BL. Thereafter, the boron-containing insulating film 140 exposed through the plurality of contact spaces CS may be isotropically etched to form boron-containing insulating fill patterns 140P exposing sidewalls of each of the plurality of bit lines BL and the plurality of insulating cap patterns 136 in the plurality of contact spaces CS and covering both (i.e., opposite) sidewalls of the direct contact portion DC.

After the boron-containing insulating fill pattern 140P is formed, a portion of the boron-containing insulating film 140 between the bit line structure including the bit line BL and the insulating cap pattern 136 and the plurality of insulating fences 348 may remain as the boron-containing insulating fence 140F. Each boron-containing insulating fence 140F can have a substantially U-shaped cross-sectional shape to cover a bottom surface and two (i.e., opposing) sidewalls of the insulating fence 348.

Referring to fig. 14D, a silicon oxide film and a silicon nitride film may be sequentially formed to conformally cover the resulting structure of fig. 14C. Thereafter, the silicon oxide film and the silicon nitride film may be anisotropically etched to form first insulating spacers 342S and second insulating spacers 344 in the plurality of contact spaces CS, respectively. The first insulating spacer 342S may include a remaining portion of the silicon oxide film, and the second insulating spacer 344 may include a remaining portion of the silicon nitride film. Each of the first and second insulating spacers 342S and 344 may have an annular shape and conformally cover the inner wall of the contact space CS.

Thereafter, a portion of the structure exposed through the plurality of contact spaces CS may be removed using a method similar to that described with reference to fig. 12L, thereby forming a plurality of recess spaces R1 exposing the active regions ACT of the substrate 110. The plurality of depression spaces R1 may communicate with (i.e., connect to) the contact space CS, respectively. The active region CT of the substrate 110 and the boron-containing insulating fill pattern 140P may be exposed through the plurality of recess spaces R1.

Referring to fig. 14E, a plurality of contact plugs 150, a plurality of metal silicide films 172, a plurality of conductive landing pads LP, and an insulating film 180 filling the upper recess space R2 may be formed by using the method described with reference to fig. 12M to 12N. Accordingly, the IC device 300 shown in fig. 7A and 7B can be manufactured.

To form the IC device 300A shown in fig. 8A and 8B, after the plurality of conductive landing pads LP are formed using the process described with reference to fig. 14E and before the upper recess space R2 is filled with the insulating film 180, the plurality of first insulating spacers 342S may be removed through the upper recess space R2 using a wet etching process, so that air spacers AS3 may be formed between the bit lines BL and the second insulating spacers 344 and between the insulating fences 348 and the second insulating spacers 344.

Fig. 15A to 15E are process sequence diagrams of a method of manufacturing an IC device according to an embodiment. In fig. 15A to 15E, (a) is a cross-sectional view of some components of a portion corresponding to a cross-section taken along line a-a 'of fig. 1 according to a process sequence, and (B) is a cross-sectional view of some components of a portion corresponding to a cross-section taken along line B-B' of fig. 1 according to a process sequence. In fig. 15A, (c) is an enlarged sectional view of a portion corresponding to a dashed line region indicated by "X2" in (a). In fig. 15B, 15D, and 15E, (c) is an enlarged plan view of a partial region in the corresponding drawings. A method of manufacturing the IC device 400 shown in fig. 9A and 9B according to some example embodiments will be described with reference to fig. 15A to 15E.

Referring to fig. 15A, the process described with reference to fig. 12A to 12F may be performed to form a plurality of bit lines BL on the substrate 110. Next, the internal insulating film 242 and the boron-containing insulating film 140 may be formed using a method similar to that described with reference to fig. 13A. Thereafter, an interlayer insulating film 340 may be formed to cover the boron-containing insulating film 140 by using a method similar to that described with reference to fig. 14A.

Referring to fig. 15B, a portion of the interlayer insulating film 340 may be removed using a method similar to that described with reference to fig. 14B, and then a plurality of insulating fences 348 may be formed on the boron-containing insulating film 140 to fill local regions of the linear spaces LS.

Referring to fig. 15C, the interlayer insulating film 340 remaining between the plurality of bit lines BL may be removed from the resultant structure of fig. 15B using a method similar to that described with reference to fig. 14C. Thereafter, the boron-containing insulating film 140 exposed through the plurality of contact spaces CS may be isotropically etched to form boron-containing insulating fill patterns 140P, and the boron-containing insulating fill patterns 140P may expose the inner insulating film 242 in the plurality of contact spaces CS and cover both (i.e., opposite) sidewalls of the direct contact portion DC. A part of the boron-containing insulating film 140 may remain (after etching) as the boron-containing insulating fence 140F covering the bottom surface and both (i.e., opposite) side walls of the insulating fence 348.

Referring to fig. 15D, a first insulating spacer 342S and a second insulating spacer 344 may be formed in each of the plurality of contact spaces CS using a method similar to that described with reference to fig. 14D. Thereafter, a portion of the structure exposed through the plurality of contact spaces CS may be removed to form a plurality of recess spaces R1 exposing the active area ACT of the substrate 110.

Referring to fig. 15E, a plurality of contact plugs 150, a plurality of metal silicide films 172, a plurality of conductive landing pads LP, and an insulating film 180 filling the upper recess space R2 may be formed by using a method similar to that described with reference to fig. 12M and 12N. Accordingly, the IC device 400 shown in fig. 9A and 9B can be manufactured.

In order to manufacture the IC device 400A shown in fig. 10A and 10B and the IC device 400B shown in fig. 11, after the plurality of conductive landing pads LP are formed using the process described with reference to fig. 15E and before the upper recess space R2 is filled with the insulating film 180, the plurality of internal insulating films 242 and the plurality of first insulating spacers 342S may be removed through the upper recess space R2 using a wet etching process. Thus, air spacers AS41 can be formed between the bitline BL and the second insulating spacer 344 and between the insulating fence 348 and the second insulating spacer 344. During the wet etching process for forming the air spacer AS41, a portion of the internal insulation film 242 interposed between the direct contact DC and the boron-containing insulation filling pattern 140P may be removed, so that the gap air portion G41 shown in fig. 10A may be formed and the internal insulation film 242G4 may remain in the vicinity of the boron-containing insulation filling pattern 140P. In addition, the amount of removal of the inter-insulating film 242 interposed between the direct contact DC and the boron-containing insulating fill pattern 140P may be adjusted during the wet etching process, so that the air spacer AS42 including the gap air portion G42 and the inter-insulating film 242G5 may remain AS in the IC device 400B shown in fig. 11.

Although a method of manufacturing an IC device according to an example embodiment of the inventive concept has been shown and described with reference to fig. 12A to 15E, it should be understood that various changes in form and detail may be made within the scope of the inventive concept, and various modified and changed IC devices may be manufactured as described with reference to fig. 12A to 15E.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.