阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 陈赫 华子群 伍术 王永庆 肖亮 于 2019-08-28 设计创作，主要内容包括：提供了一种半导体器件及其制造方法。半导体器件包括半导体结构和输入/输出焊盘。半导体结构包括第一衬底和导电层,其中,第一衬底具有彼此相对的第一表面和第二表面,导电层设置在第一衬底的第一表面上,并且导电层包括一个或多个第一迹线。第一半导体结构具有穿过第一衬底并且暴露出一个或多个第一迹线的凹陷,并且输入/输出焊盘设置在一个或多个第一迹线上并且在凹陷中。(A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor structure and an input/output pad. The semiconductor structure includes a first substrate having a first surface and a second surface opposite to each other, and a conductive layer disposed on the first surface of the first substrate and including one or more first traces. The first semiconductor structure has a recess through the first substrate and exposing the one or more first traces, and the input/output pad is disposed on the one or more first traces and in the recess.)

1. A semiconductor device, comprising:

a first semiconductor structure comprising a first substrate and a conductive layer, wherein the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer comprises one or more first traces; and

an input/output pad disposed on the one or more first traces;

wherein the first semiconductor structure has a recess through the first substrate and exposing the one or more first traces, and the input/output pad is disposed in the recess.

2. The semiconductor device according to claim 1, further comprising a first insulating layer provided over the second surface of the first substrate, wherein the first insulating layer has an opening corresponding to the recess.

3. The semiconductor device of claim 1, wherein the first semiconductor structure further comprises a second insulating layer between the first surface of the first substrate and the first conductive layer, wherein the recess passes through the second insulating layer.

4. The semiconductor device of claim 3, wherein a thickness of the input/output pad is less than a thickness of the second insulating layer.

5. The semiconductor device of claim 1, wherein the first semiconductor structure further comprises peripheral devices on the first substrate.

6. The semiconductor device of claim 5, wherein the conductive layer further comprises at least two second traces electrically connected to the peripheral device.

7. The semiconductor device of claim 1, wherein the input/output pad directly contacts the one or more first traces.

8. The semiconductor device of claim 1, wherein a width of the one or more traces is greater than a width of a bottom of the recess.

9. The semiconductor device of claim 1, further comprising a second semiconductor structure bonded to the first semiconductor structure.

10. The semiconductor device of claim 9, wherein the second semiconductor structure comprises a second substrate and a plurality of NAND strings, and the NAND strings are disposed between the conductive layer and the second substrate.

11. The semiconductor device of claim 10, wherein the first semiconductor structure further comprises a peripheral device on the first substrate, and one of the NAND strings is electrically connected to the peripheral device.

12. A method of manufacturing a semiconductor device, comprising:

providing a temporary semiconductor structure, wherein the temporary semiconductor structure comprises a temporary substrate having a first surface and a conductive layer disposed on the first surface of the temporary substrate, and the conductive layer comprises one or more first traces;

forming a recess in the temporary semiconductor structure to form a first semiconductor structure and a first substrate, wherein the recess passes through the first substrate and exposes the one or more first traces; and

an input/output pad is formed in the recess and on the one or more first traces.

13. The method of manufacturing a semiconductor device according to claim 12, further comprising thinning a surface of the temporary substrate opposite the first surface to form a second surface between providing the temporary semiconductor structure and forming the recess.

14. The method for manufacturing the semiconductor device according to claim 12, further comprising forming a first insulating layer over the temporary substrate between the providing of the temporary semiconductor structure and the forming of the recess, wherein the first insulating layer has an opening that exposes the temporary substrate.

15. The method of manufacturing a semiconductor device according to claim 14, wherein the temporary semiconductor structure further comprises a temporary insulating layer between the first surface of the temporary substrate and the conductive layer, and wherein forming the recess comprises patterning the temporary insulating layer to form a second insulating layer.

16. The manufacturing method of a semiconductor device according to claim 15, wherein a thickness of the input/output pad is smaller than a thickness of the second insulating layer.

17. The manufacturing method of the semiconductor device according to claim 14, wherein forming the input/output pad comprises:

depositing a layer of conductive material on the first insulating layer, sidewalls of the recess, and the one or more first traces; and

removing portions of the layer of conductive material on the first insulating layer and sidewalls of the recess.

18. The method of manufacturing the semiconductor device of claim 17, wherein the input/output pad is formed directly on the one or more first traces.

19. The method of manufacturing a semiconductor device according to claim 12, wherein providing the temporary semiconductor structure comprises providing a second semiconductor structure bonded to the temporary semiconductor structure.

20. The method of manufacturing the semiconductor device of claim 19, wherein the second semiconductor structure comprises a second substrate and a plurality of NAND strings, and the NAND strings are disposed between the conductive layer and the second substrate.

Technical Field

The present invention relates to a semiconductor device and a method of manufacturing the same.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become more difficult and more costly. Therefore, the storage density for planar memory cells approaches the upper limit.

Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array devices. Referring to fig. 1, an input/output (I/O) pad (pad) structure of a conventional 3D memory device is shown. In the I/O pad structure 10 of the conventional 3D memory device, the substrate 12 for forming the memory array device 14 may be etched through to form a via (through hole)12h for electrically connecting the memory array device 14 under the substrate 12 to the I/O pad 16 on the substrate 12. To form the I/O pad structure 10, an insulating layer 18 is further formed on the surface 12a of the substrate 12 opposite the memory array device 14, such that the I/O pads 16 formed on the insulating layer 18 can be insulated from the substrate 12 having some elements (e.g., doped regions) formed therein. Further, vias 12h are formed through the insulating layer 18 and the substrate 12, and a Through Silicon Contact (TSC)20 and a liner layer 22 are formed in each via 12h, with the liner layer 22 being located between the TSC 20 and the substrate 12 for insulating them from each other. The TSCs 20 penetrate the substrate 12 and electrically connect the I/O pads 16 to through array contacts 14c of the memory array device 14 formed on the other surface 12b of the substrate 12 opposite the surface 12 a. A passivation layer (24) is formed on the I/O pad 16 and has an opening 24a exposing the I/O pad 16.

However, some of the drawbacks in the following description remain in the conventional I/O pad structure 10. First, parasitic capacitance generated between the I/O pad 16 and the substrate 12 will strongly affect the operating speed of the 3D memory device or the speed for storing or reading data in the 3D memory device, and therefore, in order to reduce the effect, the thickness of the insulating layer 18 may be increased to reduce the parasitic capacitance, but the parasitic capacitance also exists between the TSC 20 and the substrate 12. Second, when the thickness of the insulating layer 18 is increased to, for example, more than 1.4 μm, the aspect ratio of each via hole 12h passing through the insulating layer 18 and the substrate 12 is increased, thereby significantly amplifying the process difficulty. Third, due to the increased thickness of the insulating layer 18, more advanced techniques are required, such as a machine for forming the via 12h having a larger aspect ratio through the substrate 12, a machine for filling the tungsten paste into the via 12h having a larger aspect ratio, a machine for depositing the liner layer 22 in the via 12h having a larger aspect ratio, and the like. Thus, the cost of the 3D memory device cannot be further reduced. Third, with advanced technology, the number of layers of the storage stack needs to be increased. In such a case, the space between two of the through array contacts 14c becomes smaller so that the opening of each through via 12h will be smaller, and the space between the TSC 20 and the substrate 12 is reduced, thereby increasing parasitic capacitance and slowing the operation speed of the 3D memory device. For this reason, different technology generations cannot continuously share the same architecture. Fourth, since the opening of each via 12h is limited by the space between two of the through array contacts 14c, the opening of each via 12h is small and limited, so that a small deviation of the via 12h caused by process errors may cause an open circuit between the through array contact 14c and the I/O pad 16 or current leakage in the memory array device 14.

Disclosure of Invention

Embodiments of a semiconductor device and a method of manufacturing the same are described herein.

According to an embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor structure and an input/output pad. The first semiconductor structure includes a first substrate having a first surface and a second surface opposite to each other, and a conductive layer disposed on the first surface of the first substrate and including one or more first traces. Input/output pads are disposed on the one or more first traces. The first semiconductor structure has a recess through the first substrate and exposing the one or more first traces, and the input/output pad is disposed in the recess.

In some embodiments, the semiconductor device further includes a first insulating layer disposed on the second surface of the first substrate, and the first insulating layer has an opening corresponding to the recess.

In some embodiments, the first semiconductor structure further comprises a second insulating layer between the first surface of the first substrate and the first conductive layer, wherein the recess passes through the second insulating layer.

In some embodiments, the thickness of the input/output pad is less than the thickness of the second insulating layer.

In some embodiments, the first semiconductor structure further comprises a peripheral device on the first substrate.

In some embodiments, the conductive layer further includes at least two second traces electrically connected to one or more peripheral devices.

In some embodiments, the input/output pads directly contact the one or more first traces.

In some embodiments, the width of the one or more traces is greater than the width of the bottom of the recess.

In some embodiments, the semiconductor device further includes a second semiconductor structure bonded to the first semiconductor structure.

In some embodiments, the second semiconductor structure includes a second substrate and a plurality of NAND strings, and the NAND strings are disposed between the conductive layer and the second substrate.

In some embodiments, the first semiconductor structure further includes a peripheral device on the first substrate, and one of the NAND strings is electrically connected to one or more peripheral devices.

According to an embodiment of the present invention, a method of manufacturing a semiconductor device is disclosed, and the method of manufacturing a semiconductor device includes: providing a temporary semiconductor structure, wherein the temporary semiconductor structure comprises a temporary substrate and a conductive layer, the temporary substrate has a first surface, the conductive layer is disposed on the first surface of the temporary substrate, and the conductive layer comprises one or more first traces; forming a recess in the temporary semiconductor structure to form a first semiconductor structure and a first substrate, wherein the recess passes through the first substrate and exposes one or more first traces; and forming an input/output pad in the recess and on the one or more first traces.

In some embodiments, the method of manufacturing further comprises thinning a surface of the temporary substrate opposite the first surface to form a second surface between providing the temporary semiconductor structure and forming the recess.

In some embodiments, the method further comprises forming a first insulating layer on the temporary substrate between providing the temporary semiconductor structure and forming the recess, wherein the first insulating layer has an opening exposing the temporary substrate.

In some embodiments, the temporary semiconductor structure further comprises a temporary insulating layer between the first surface of the temporary substrate and the conductive layer, and forming the recess comprises patterning the temporary insulating layer to form the second insulating layer.

In some embodiments, forming the input/output pad includes: depositing a layer of conductive material on the first insulating layer, the sidewalls of the recess, and the one or more first traces; and removing portions of the conductive material layer on the first insulating layer and the sidewalls of the recess.

In some embodiments, the input/output pads are formed directly on the one or more first traces.

In some embodiments, providing the first semiconductor structure includes providing a temporary semiconductor structure, which includes providing a second semiconductor structure bonded to the temporary semiconductor structure.

Other aspects of the disclosure will be apparent to those skilled in the art from the description, claims, and drawings of the disclosure.

These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are illustrated in the various drawing figures and drawings.

Drawings

The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

Fig. 1 illustrates an input/output pad structure of a conventional 3D memory device.

Fig. 2 schematically shows a cross-sectional view of an exemplary semiconductor device according to a first embodiment of the present invention.

Fig. 3 schematically shows a cross-sectional view of an exemplary semiconductor device according to a first embodiment of the present invention.

Fig. 4 is a flowchart of an exemplary method of manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 5 to 8 schematically show exemplary manufacturing steps of the semiconductor device.

Fig. 9 schematically shows an exemplary semiconductor device according to a second embodiment of the present invention.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this may be done for illustrative purposes only. One skilled in the relevant art will recognize that: other configurations and arrangements may be used without departing from the spirit and scope of the present invention. It will be apparent to those skilled in the relevant art that the present invention may also be used in a variety of other applications.

Note that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein may be used in a singular sense to describe any feature, structure, or characteristic or may be used in a plural sense to describe a combination of features, structures, or characteristics, depending, at least in part, on the context. Similarly, terms such as "a," "an," and "the" again may be understood to convey a singular use or to convey a plural use, depending at least in part on the context.

It should be readily understood that the meaning of "on … …", "above … …" and "above … …" in the present invention should be interpreted in the broadest manner such that "on … …" not only means "directly on something", but also includes "on something" with the meaning of an intermediate feature or layer therebetween, and "on … …" or "above … …" not only means "on something" or "above something", but also includes the meaning of "on something" or "above something" without an intermediate feature or layer therebetween (i.e., directly on something).

Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

As used throughout this application, the word "may" is used in a permissive sense (e.g., meaning having the potential to), rather than the mandatory sense (e.g., meaning must). The words "include", "including", and "contain" indicate open relationships and are thus meant to include, but not limited to. Similarly, the words "having," "having," and "with" also indicate an open relationship, and thus mean having, but not limited to. As used herein, the terms "first," "second," "third," and the like, refer to labels that distinguish between different elements and may not necessarily have an ordinal meaning according to their numerical designation.

In the present invention, various technical features in different embodiments described in the following description may be combined, substituted, and mixed with each other to constitute another embodiment.

Referring to fig. 2, a cross-sectional view of an exemplary semiconductor device according to a first embodiment of the present invention is schematically shown. As shown in fig. 2, the semiconductor device 1 provided in this embodiment includes a first semiconductor structure 102 and an input/output (I/O) pad 104, wherein the first semiconductor structure 102 has a recess 102R for disposing the I/O pad 104, and the I/O pad 104 is electrically connected to an external circuit or device to transfer an electrical signal between the semiconductor device 1 and the external circuit or device. One I/O pad 104 is shown in fig. 2, but the number of I/O pads 104 of the present invention is not limited thereto and may be plural. In this embodiment, the first semiconductor structure 102 includes a first substrate 110 and one or more conductive layers 112, wherein the first substrate 110 has a first surface 110a and a second surface 110b opposite to each other, and the conductive layers 112 are disposed on the first surface 110a of the first substrate 110. The conductive layer 112 may include one or more first traces 112T1 exposed by the recesses 102R, and the I/O pads 104 are disposed on the first traces 112T1 and electrically connected with the first traces 112T 1. By disposing the I/O pad 104 into the recess 102R, parasitic capacitance generated between the I/O pad 104 and the first substrate 110 can be reduced. The first semiconductor structure 102 may be, for example, a peripheral device structure, so the first semiconductor structure 102 may include a first substrate 110 and a peripheral interconnect layer 108 on a first surface 110a of the first substrate 110, and the conductive layer 112 is included in the peripheral interconnect layer 108. The first semiconductor structure 102 may further include a peripheral device 106 on the first surface 110a of the first substrate 110 and between the peripheral interconnect layer 108 and the first substrate 110. The first substrate 110 may comprise, for example, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The conductive layer 112 may, for example, comprise a conductor material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

It should be noted that X and Y axes are added in fig. 2 to further illustrate the spatial relationship of the components in the semiconductor device 1. The first substrate 110 includes two lateral surfaces (e.g., a first surface 110a and a second surface 110b) extending laterally in an X-direction (lateral or width direction). As used herein, one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device is determined relative to a substrate (e.g., first substrate 110) of the semiconductor device in another direction Y (a vertical direction or a thickness direction). The same concepts are applied throughout this disclosure to describe spatial relationships.

In this embodiment, the first substrate 110 may have a device region DR and a pad region PR. The device region DR is used to form the peripheral device 106 and the pad region PR is used to form the recess 102R and the I/O pad 104 so that the peripheral device 106 is not affected or damaged by the formation of the recess 102R and the I/O pad 104. Accordingly, the first substrate 110 may be etched through to have an opening 110P corresponding to the recess 102R.

The peripheral devices 106 may include one or more transistors. In the embodiment shown in fig. 2, one transistor is shown as an example, but is not limited thereto. The peripheral device 106 may, for example, include a doped region 106a and a gate structure 106 b. The doped region 106a is disposed in the first substrate 110. The gate structure 106b may be disposed between the first substrate 110 and the peripheral interconnect layer 108.

Peripheral interconnect layer 108 includes a conductive layer 112 and one or more insulating layers so that peripheral device 106 may be electrically connected to I/O pads 104 or other devices, such as the memory array devices below. In the embodiment shown in fig. 2, one conductive layer 112 and two insulating layers 114a, 114b are shown as an example, but not limited thereto. Each of the insulating layers 114a and 114b may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, any other suitable dielectric material, or any combination thereof. The conductive layer 112 is disposed on the first surface 110a of the first substrate 110 between the insulating layer 114a and the insulating layer 114b, and the insulating layer 114a is disposed between the conductive layer 112 and the first substrate 110, such that portions of the conductive layer 112 may be electrically isolated from the first substrate 110 by the insulating layer 114 a.

In this embodiment, the recess 102R further passes through the insulating layer 114a between the first substrate 110 and the conductive layer 112 and exposes the first trace 112T1, so that the insulating layer 114a has an opening 114P corresponding to the recess 102R. For example, the opening 110P, the opening 114P, the exposed first trace 112T1, and portions of the insulating layer 114b may form the recess 102R.

In addition, the semiconductor device 1 may further include another insulating layer 118 disposed on the second surface 110b of the first substrate 110, wherein the insulating layer 118 has an opening 118P corresponding to the recess 102R. In other words, the opening 118P exposes the recess 102R. Thus, the I/O pad 104 may be formed on the conductor layer 112 through the opening 118P and the recess 102R, and electrically connected to the exposed first trace 112T1 by being disposed in the recess 102R. For example, the I/O pad 104 may directly contact the first trace 112T 1. In the embodiment shown in fig. 2, the number of exposed first wire traces 112T1 spaced apart from each other is plural, and the I/O pad 104 is electrically connected to the plurality of first wire traces 112T1, but is not limited thereto. In some embodiments, the number of exposed first traces 112T1 may be one, and the width of the first traces 112T1 may be the same as or different from the width of the bottom of the recess 102R. Preferably, the width of the first trace 112T1 may be greater than the width of the bottom of the recess 102R, so that the first trace 112T1 may function as an etch stop layer when forming the recess 102R. In some embodiments, the conductive layer 112 may be, but is not limited to, one of the conductive layers within the peripheral interconnect layer 108 that is closest to the first substrate 110. In some embodiments, the conductive layer 112 may further include at least two second traces 112T2 electrically connected to the peripheral devices 106. In some embodiments, the number of insulating layers penetrated by the recess 102R may be plural. In some embodiments, the thickness T1 of the conductive layer 112 may be less than the thickness T2 of the insulating layer 114a, such that the spacing between the conductive layer 112 and the first substrate 110 may be increased to reduce parasitic capacitance therebetween.

In some embodiments, peripheral interconnect layer 108 may further include at least one contact layer 116 for electrically connecting peripheral device 106 to conductive layer 112. For example, the contact layer 116 includes a contact plug that passes through the insulating layer 114 a. In some embodiments, peripheral interconnect layer 108 may further include a contact layer below conductive layer 112, but is not limited thereto. The conductive layer 116 may, for example, comprise a conductor material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

In some embodiments, the semiconductor device 1 may further include a passivation layer 120 for protecting the insulating layer 118, the first semiconductor structure 102, and the I/O pad 104. The passivation layer 120 has an opening 120P exposing the I/O pad 104 so that the I/O pad 104 can be electrically connected to an external circuit or device through the opening 120P.

The semiconductor device may for example be a memory device or any other suitable device. Referring to fig. 3, a cross-sectional view of a semiconductor device according to an example of a first embodiment of the present invention is schematically shown. As shown in fig. 3, the semiconductor device 1 provided in this example is a NAND flash memory device, but is not limited thereto. The memory cells in the NAND flash memory device are provided in the form of a plurality of NAND strings 222 extending vertically below the first substrate 110. In this example, the semiconductor device 1 may further include a second semiconductor structure 224, and the second semiconductor structure 224 includes a second substrate 226 and a memory array device 228. The second substrate 226 is disposed opposite the first surface 110a of the first substrate 110, and the memory array device 228 is formed on the second substrate 226 and between the first substrate 110 and the second substrate 226. The second substrate 226 may include, for example, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

The memory array device 228 can include a NAND string 222 disposed between the conductive layer 112 and the second substrate 226. NAND string 222 extends vertically through a plurality of conductor layers 230 and a plurality of dielectric layers 232. Each conductor layer 230 may form a pair with a corresponding one of the dielectric layers 232. Each conductor layer 230 may be adjacent to two dielectric layers 232 on two sides, and each dielectric layer 232 may be adjacent to two conductor layers 230 on two sides. Conductor layer 230 may include a conductor material such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, any other suitable conductor material, or any combination thereof. The dielectric layer 232 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, any other suitable dielectric material, or any combination thereof. In addition, the memory array device 228 may further include a source contact 234, a word line contact 236, and a dielectric layer 238, wherein the source contact 234 extends vertically through the conductor layer 230 and the dielectric layer 232, the word line contact 236 extends vertically within the dielectric layer 238, and each word line contact 236 contacts a corresponding conductor layer 230 to individually address a corresponding word line of the memory array device 228. It should be noted that the memory array device 228 shown in fig. 2 is used as an example, and those skilled in the art will appreciate that the memory array device 228 may have other structures, so the structure of the memory array device 228, or variations thereof, will not be described in detail herein. In some embodiments, the isolation regions 240 and the doped regions 242 may be formed in the second substrate 226.

As shown in fig. 2, the semiconductor device 1 may further include an array interconnect layer 244 for electrically connecting the memory array device 228 to the peripheral devices 106 and/or the I/O pads 104. For example, one of the NAND strings 222 is electrically connected to the peripheral device 106 through the array interconnect layer 244 and the peripheral interconnect layer 108. An array interconnect layer 244 is disposed on the memory array device 228 and in contact with the peripheral interconnect layer 108. Array interconnect layer 244 may include one or more contact layers (e.g., contact layers 246a, 246b), one or more conductive layers (e.g., conductive layers 248a, 248b), and one or more dielectric layers (e.g., dielectric layers 250a, 250 b). The contact layers 246a, 246b and conductive layers 248a, 248b may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The dielectric layers 250a, 250b may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, low-k dielectrics, or any combination thereof.

In this example, the peripheral interconnect layer 108 may include a plurality of conductive layers 112 (e.g., conductive layers 112a, 112b), a plurality of contact layers 116 (e.g., contact layers 116a, 116b), and a plurality of dielectric layers (e.g., dielectric layers 114a, 114b, 114 c). In some embodiments, the number of contact layers 116 and the number of dielectric layers are not limited to a plurality and may be adjusted based on the number of conductive layers 112. Bonding interface 252 may be formed between dielectric layer 114c of peripheral interconnect layer 108 and dielectric layer 250a of array interconnect layer 244. The bonding interface 252 may also be formed between the conductor layer 248a of the array interconnect layer 244 and the conductor layer 112b of the peripheral interconnect layer 108. In other words, the first semiconductor structure 102 is bonded to the second semiconductor structure 224 at the bonding interface 252. In some embodiments, the first semiconductor structure 102 may further include an isolation region 154 formed in the first substrate 110 for separating different components.

As mentioned above, the semiconductor device 1 may have the following advantages compared to the conventional memory device shown in fig. 1. First, since the I/O pad 104 is directly disposed in the recess 102R, the I/O pad 104 does not exist in the opening 110P of the first substrate 110. Accordingly, parasitic capacitance generated between the I/O pad 104 and the first substrate 110 can be reduced, thereby improving the operation speed of the semiconductor device 1 or the speed for storing or reading data in the semiconductor device 1. Second, the thickness of the insulating layer 118 does not need to be increased to reduce parasitic capacitance, so that the cost for forming the insulating layer 118 can be reduced and a high aspect ratio is not required. Thus, the formation of I/O pads 104 is not limited by the high aspect ratio of vias through the insulating layer and the substrate, and can ease the process difficulty for forming I/O pads 104 as the density of NAND strings 22 is increased. Third, since the recesses 102R are formed on the first semiconductor structure 108 including the peripheral devices 106, the width of the recesses 102R (e.g., in the range of 70 μm to 80 μm) is not limited to be similar or identical to the width of the NAND strings 222 or the TSCs, and the exposure light used in the photolithography process is not limited to have a very small wavelength. For example, the photolithography process used to form the recesses 102R may use an I-line exposure (e.g., 365 nm). For this reason, an open circuit between the through array contact and the I/O pad or a current leakage in the semiconductor device due to a process error will not occur. For this reason, more advanced techniques such as a machine for forming a through-hole having a larger aspect ratio through the substrate, a machine for filling tungsten paste into a through-hole having a larger aspect ratio, a machine for depositing a liner layer in a through-hole having a larger aspect ratio, and the like are not required. Fourth, while increasing the number of conductor layers 230 and dielectric layers 232 to upgrade the storage capacity, different technology generations can still easily share the same semiconductor device 1.

Fig. 4 is a flowchart of an exemplary method of manufacturing a semiconductor device according to the first embodiment of the present invention. Fig. 5 through 8 and fig. 2 schematically illustrate exemplary fabrication steps of a semiconductor device, wherein fig. 6 through 8 omit portions of the first and second semiconductor structures for clarity, although the invention is not limited thereto. It should be noted that the steps shown in fig. 4 are not exhaustive and that other steps may be performed before, after or in between any of the illustrated steps. The manufacturing method of the semiconductor device 1 provided in this embodiment includes the following steps S12-S20. As shown in fig. 4 and 5, step S12 is performed to provide temporary semiconductor structure 302. The temporary semiconductor structure 302 includes a temporary substrate 310, a temporary insulating layer 314a, and one or more conductive layers 112. The temporary semiconductor structure 302 differs from the first semiconductor structure 102 in that: the temporary substrate 310 of the semiconductor structure 302 is not thinned and etched through in step S12, so the temporary semiconductor structure 302 does not have the recess 102R and the temporary substrate 310 does not have the opening 110P. In some embodiments, the thickness of the temporary substrate 310 may be greater than the thickness of the first substrate 110 in step S12. In this embodiment, temporary substrate 310 has first surface 110a and third surface 310b opposite each other, and temporary peripheral interconnect layer 308 and peripheral devices 106 are formed on first surface 110a of temporary substrate 310. In step S12, the temporary peripheral interconnect layer 308 differs from the peripheral interconnect layer 108 mentioned above in that: the temporary insulating layer 314a is not etched through so as to have no opening 114P. In this embodiment, the peripheral devices 106 are similar or identical to those mentioned above, and redundant description thereof will not be given.

In step S12, a second semiconductor structure 224 is also provided, and the second semiconductor structure 224 is bonded to the temporary semiconductor structure 302. Since the second semiconductor structure 224 is the same as mentioned above, detailed description of the second semiconductor structure 224 will not be repeated.

As shown in fig. 4, 5, and 6, step S14 is optionally performed to thin the third surface 310b of the temporary substrate 310 to form the second surface 110 b. For example, thinning the first substrate 310 may include performing a Chemical Mechanical Planarization (CMP) process or any other suitable process.

After thinning the temporary substrate 310, step S16 is performed to form an insulating layer 118 on the second surface 110b of the thinned temporary substrate 310, wherein the insulating layer 118 has an opening 118P exposing the second surface 110b of the temporary substrate 310. For example, forming the insulating layer 118 may include depositing an insulating material and patterning a layer of the insulating material. The deposition of the layer of insulating material may for example employ a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process or any other suitable deposition process. The patterning of the layer of insulating material may for example employ a lithographic process using a photomask, such as an I-line mask. In some embodiments, step S16 may be performed directly after providing the temporary semiconductor structure 302.

After the insulating layer 118 is formed, step S18 may be performed to form a recess 102R in the pad region PR of the temporary semiconductor structure 302. Specifically, forming the recess 102R may include: the exposed temporary substrate 310 is patterned to form an opening 110P in the temporary substrate 310, thereby forming the aforementioned first substrate 110 having the opening 110P. The patterning of the temporary substrate 310 may, for example, employ an etching process that uses the insulating layer 118 as a mask. Forming the recess 102R may further include patterning a portion of the temporary insulating layer 314a exposed by the opening 110P to form an opening 114P after forming the opening 110P and expose the first trace 112T1, thereby forming the aforementioned insulating layer 114a having the opening 114P. Accordingly, the above-mentioned first semiconductor structure 102 can be formed, and the above-mentioned peripheral interconnect layer 108 can be formed. Patterning of the temporary insulating layer 314a may, for example, employ an etching process that selectively etches the temporary insulating layer 314a relative to the insulating layer 118, the first substrate 110, and the conductive layer 112. In some embodiments, the peripheral interconnect layer 308 may also include an etch stop layer between the conductive layer 112 and the temporary insulating layer 314a, such that etching of the temporary insulating layer 314a can stop at the etch stop layer and can protect the insulating layer 114b between the first traces 112T 1. In some embodiments, the etching process may have a high etch selectivity to the temporary insulating layer 314a relative to the insulating layer 114 b.

As shown in fig. 4 and 8, step S20 may be performed to form the I/O pad 104 in the recess 102R and on the first trace 112T 1. Specifically, as shown in fig. 7, forming the I/O pad 104 includes: a layer of conductive material 104m is deposited over the insulating layer 118, the sidewalls of the recess 102R, and the first trace 112T 1. In other words, the layer of conductive material 104m extends from the top surface of the insulating layer 118 onto the sidewalls of the opening 118P, the sidewalls of the opening 110P, the sidewalls of the opening 114P, and the I/O pad 104. The deposition of the layer of conductive material 104m may use a CVD process, a PVD process, an ALD process, or any other suitable deposition process. Subsequently, as shown in fig. 8, forming the I/O pad 104 further includes patterning the conductive material layer 104m to remove portions of the conductive material layer 104m on the insulating layer 118 and on the sidewalls of the recess 102R.

As shown in fig. 2, after the I/O pad 104 is formed, a passivation layer 120 may also be formed on the insulating layer 118, the sidewall of the opening 110P, the sidewall of the opening 114P, and the I/O pad 104, and then, the passivation layer 120 is patterned to have an opening 120P exposing the I/O pad 104. Accordingly, the semiconductor device 1 of this embodiment is formed.

The following description sets forth in detail various embodiments of the disclosure. For simplicity of description, identical reference numerals are used to designate identical parts of each of the following embodiments. In order that the differences between the embodiments may be more readily understood, the following description will set forth in detail the differences between the different embodiments, and will not repeatedly describe equivalent features.

Referring to fig. 9, an exemplary semiconductor device according to a second embodiment of the present invention is schematically shown. As shown in fig. 9, the semiconductor device 2 provided in this embodiment is different from the previous embodiment in that: the width W1 of the first trace 112T1 may be greater than the width W2 of the bottom of the recess 102R, and thus the first trace 112T1 may function as an etch stop layer when forming the recess 102R.

By using the disclosed semiconductor device and method of manufacturing the same, parasitic capacitance generated between an I/O pad and a first substrate can be reduced, thereby improving the operating speed of a memory device or the speed for storing or reading data in the memory device. Further, the thickness of the insulating layer over the first substrate does not need to be increased to reduce parasitic capacitance, so that the cost for forming the insulating layer can be reduced and a high aspect ratio is not required. Thus, the formation of the I/O pad is not limited by a high aspect ratio, and the process difficulty for forming the I/O pad can be made easy while increasing the density of the NAND strings. Since the recess is formed on the first semiconductor structure including the peripheral device, the width of the recess of the first semiconductor structure is not limited to be similar to or the same as the width of the NAND string or the TSC, and the exposure light used in the photolithography process can have a large wavelength. Furthermore, no open circuit between the through-array contacts and the I/O pads or current leakage in the semiconductor device due to process errors will occur and no more advanced technology is required. Furthermore, different technology generations can still easily use the same architecture when increasing the number of conductor layers and dielectric layers to upgrade the storage capacity.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art to various applications (e.g., the specific embodiments), readily modify and/or adapt for various applications such as the treatment of diseases or conditions requiring treatment without undue experimentation and without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the present invention and the guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the present disclosure and guidance.

Embodiments of the present invention have been described above with the aid of functional building blocks illustrating the implementation of specific functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.