阅读说明：本技术 反熔丝结构 (Anti-fuse structure ) 是由 黄庆玲 施江林 陈姿吟 于 2018-11-01 设计创作，主要内容包括：一种反熔丝结构,包括一主动区及该主动区上的一栅极电极。该主动区包括一第一本体部分及在一第一方向延伸的一第一延伸部分。该栅极电极包括一第二本体部分及在垂直于该第一方向的一第二方向上延伸的一第二延伸部分。该第一本体部分包括面向该第二本体部分的一部分的一第一表面,该第二本体部分包括面向该第一延伸部分的一部分的一第二表面。该第一延伸部分及该第二延伸部分在垂直于该第一方向及该第二方向的一第三方向上部分重叠,且一介电层夹在该第一延伸部分及该第二延伸部分之间,形成一交叉区域。(An anti-fuse structure includes an active region and a gate electrode on the active region. The active region includes a first body portion and a first extension portion extending in a first direction. The gate electrode includes a second body portion and a second extension portion extending in a second direction perpendicular to the first direction. The first body portion includes a first surface facing a portion of the second body portion, and the second body portion includes a second surface facing a portion of the first extension portion. The first extending portion and the second extending portion are partially overlapped in a third direction perpendicular to the first direction and the second direction, and a dielectric layer is sandwiched between the first extending portion and the second extending portion to form a crossing region.)

1. An antifuse structure, comprising:

an active region having a first body portion and a first extension portion extending along a first direction; and

a gate electrode over the active region, wherein the gate electrode includes a second body portion and a second extension portion extending along a second direction perpendicular to the first direction;

wherein the first body portion includes a first surface facing a portion of the second body portion, the second body portion includes a second surface facing a portion of the first extension portion;

wherein the first and second extensions partially overlap in a third direction perpendicular to the first and second directions, and a dielectric layer is sandwiched between the first and second extensions to form an intersection region.

2. The antifuse structure of claim 1, wherein the aspect ratio of the intersection region is in the range of about 0.9 to 1.5.

3. The antifuse structure of claim 1, wherein the first surface is separated from the gate electrode in the first direction.

4. The antifuse structure of claim 1, further comprising:

a first conductive via disposed on the first body portion and electrically connected to the active region;

a second conductive via disposed on the second body portion and electrically connected to the gate electrode.

5. An antifuse structure, comprising:

an active region having a first body portion and a first extension portion extending along a first direction; and

a gate electrode over the active region, wherein the gate electrode comprises a second body portion and two second extension portions; the second extension portion extends from the second body portion in the first direction, and the second body portion and the two second extension portions are separated from each other by a space;

wherein the first extension portion and the second extension portion are partially overlapped in a vertical projection direction perpendicular to the first direction, and a dielectric layer is sandwiched between the first extension portion and the second extension portion to form an intersection region.

6. The antifuse structure of claim 5, wherein the aspect ratio of the intersection region is in the range of about 0.9 to 1.5.

7. The antifuse structure of claim 5, wherein the second body portion includes an edge surface opposite a surface from which the two second extension portions extend, and wherein the edge surface is proximate to the first body portion in the first direction.

8. The antifuse structure of claim 5, further comprising:

a first conductive via disposed on the first body portion and electrically connected to the active region.

9. The antifuse structure of claim 5, wherein the first extension portion extends beyond the second body portion and protrudes from the space, and a portion of the first extension portion appears between the two second extension portions when viewed in the perpendicular projection.

10. The antifuse structure of claim 9, wherein the two second extending portions extend further from the second body portion than the first extending portion.

11. The antifuse structure of claim 5, wherein the gate electrode comprises a third body portion, and the two second extension portions extend between the second body portion and the third body portion.

12. The antifuse structure of claim 11, further comprising:

a second conductive via disposed on the third body portion and electrically connected to the gate electrode.

13. The antifuse structure of claim 11, wherein the first extension portion comprises a convex surface facing the third body portion.

14. The antifuse structure of claim 11, wherein the two second extensions have an extension width, and the void has a void width greater than the extension width.

15. The antifuse structure of claim 14, wherein the first extension has a width that is greater than the extension width and less than the space width.

Technical Field

The present disclosure claims priority and benefit of 2018/07/13 application U.S. official application No. 16/034,905, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to an anti-fuse structure, and more particularly, to a Gate Oxide (GOX) anti-fuse structure.

Background

Antifuses and fuses are widely used for fault tolerance (fault tolerance) in the fabrication of integrated circuits. For example, antifuses and fuses may be placed in the circuit path of the element. A circuit path that is initially conductive can be broken by blowing a fuse. Conversely, an otherwise non-conductive circuit path may become a short circuit by blowing the antifuse. In addition, antifuses are also used for one-time programming.

An antifuse structure is comprised of two conductors separated from each other by an insulator. The two conductors are connected to different components, respectively. When the applied voltage is lower than a programmable voltage, the path between the two conductors is a non-conductive circuit path, i.e., an open circuit. When a programmable voltage is applied, the insulator undergoes a dielectric breakdown process. Leakage current increases and a thermal runaway condition occurs, melting the insulator and adjacent conductive material. The conductive material flows from the two conductors and forms a conductive filament that creates a short circuit between the two conductors.

The programming voltage is a critical factor in the design rules of an antifuse, and the present disclosure provides an antifuse structure that can be programmed using an appropriate programming voltage.

The above prior art description merely provides background and does not constitute an admission that the above prior art description discloses the subject matter of the present disclosure and does not constitute prior art to the present disclosure, and that any description of the above prior art should not be taken as any part of the present disclosure.

Disclosure of Invention

The present disclosure provides an antifuse structure. The anti-fuse structure includes an active region and a gate electrode over the active region. The active region includes a first body portion and a first extension portion extending in a first direction. The gate electrode includes a second body portion and a second extension portion extending in a second direction perpendicular to the first direction. The first body portion includes a first surface facing a portion of the second body portion, and the second body portion includes a second surface facing a portion of the first extension portion. The first extending portion and the second extending portion are partially overlapped in a third direction perpendicular to the first direction and the second direction, and a dielectric layer is sandwiched between the first extending portion and the second extending portion to form a crossing region.

In some embodiments, the aspect ratio (aspect ratio) of the intersection region is approximately in the range of 0.9 to 1.5.

In some embodiments, the first surface is separated from the gate electrode in the first direction.

In some embodiments, the antifuse structure further comprises a first conductive via disposed on the first body portion. The first conductive via is electrically connected to the active region. The antifuse structure further includes a second conductive via disposed on the second body portion. The second conductive via is electrically connected to the gate electrode.

The present disclosure provides an antifuse structure. The anti-fuse structure includes an active region and a gate electrode over the active region. The active region includes a first body portion and a first extension portion extending in a first direction. The gate electrode includes a second body portion and two second extension portions. The second extension portion extends from the second body portion in the first direction, and the second body portion and the two second extension portions are separated from each other by a space. The first extending portion and the second extending portion are partially overlapped in a vertical projection direction perpendicular to the first direction, and a dielectric layer is sandwiched between the first extending portion and the second extending portion to form a crossing region.

In some embodiments, the intersection region has an aspect ratio in the range of about 0.9 to about 1.5.

In some embodiments, the first surface is separated from the gate electrode in the first direction.

In some embodiments, the antifuse structure further comprises a first conductive via disposed on the first body portion. The first conductive via is electrically connected to the active region.

In some embodiments, the first extension portion extends beyond the second body portion and protrudes from the space, and a portion of the first extension portion appears between the two second extension portions when viewed from the perpendicular projection.

In some embodiments, the two second extension portions extend further from the second body portion than from the first extension portion.

In some embodiments, the gate electrode includes a third body portion, and the two second extension portions extend between the second body portion and the third body portion.

In some embodiments, the antifuse structure further comprises a second conductive via disposed on the third body portion. The second conductive via is electrically connected to the gate electrode.

In some embodiments, the first extension portion includes a convex surface facing the third body portion.

In some embodiments, the two second extensions have an extension width, and the space has a space width greater than the extension width.

In some embodiments, the first extension portion has a width that is greater than the extension portion width and less than the space width.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages will be described hereinafter that form the claims of the present disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure will become more fully understood from the consideration of the following description and the appended claims, taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like elements.

FIG. 1A is a top view illustrating an antifuse structure of some embodiments of the present disclosure;

FIG. 1B is a cross-sectional view taken along line A-A' of FIG. 1A illustrating an antifuse structure of some embodiments of the present disclosure;

FIG. 1C is a cross-sectional view taken along line B-B' of FIG. 1A illustrating an antifuse structure of some embodiments of the present disclosure;

FIG. 1D is a cross-sectional view taken along line C-C' of FIG. 1A illustrating an antifuse structure of some embodiments of the present disclosure;

FIG. 2A is a top view illustrating an antifuse structure according to a comparative embodiment of the present disclosure; and

fig. 2B is a cross-sectional view taken along line D-D' of fig. 2A illustrating an antifuse structure according to some embodiments of the present disclosure.

Description of reference numerals:

10 antifuse structure

20 active region

21 first body part

22 first extension

23 first conductive via

24 conductive vias

25 insulating layer

30 gate electrode

31 second body part

32 second extension portion

33 second conductive via

34 conductive vias

35 semiconductor substrate

40 cross region

50 dielectric layer

60 antifuse structure

81 second body part

82 second extension

82' second extension

83 third body part

84 space

90 cross region

D1 first direction

D2 second direction

Third direction D3

S1 first surface

S2 second surface

S3 edge surface

S4 projected surface

w1 extended part width

width of w2 space

w3 width

Detailed Description

The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the present disclosure, however, the present disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

"one embodiment," "an example embodiment," "another embodiment," etc., mean that the embodiments described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated use of the phrases "in an embodiment" or "in an embodiment" does not necessarily refer to the same embodiment, but may.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It will be apparent that the implementation of the disclosure does not limit the specific details known to those skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be widely implemented in other embodiments besides the embodiments. The scope of the present disclosure is not limited to the content of the embodiments but is defined by the claims.

Fig. 1A is a top view illustrating an antifuse structure 10 according to some embodiments of the present disclosure. FIG. 1B is a sectional view taken along line A-A ' in FIG. 1A, FIG. 1C is a sectional view taken along line B-B ' in FIG. 1A, and FIG. 1D is a sectional view taken along line C-C ' in FIG. 1A.

The antifuse structure 10 includes an active region 20 and a gate electrode 30 over the active region.

The active region 20 includes a doped region. For example, the active region 20 is formed in a semiconductor substrate 35 (see fig. 1B) and is close to a surface of the semiconductor substrate 35. The active region 20 may contain a higher dopant concentration than other portions of the semiconductor substrate 35. The concentration, type and extent of dopants or other critical factors (critical factors) may be adjusted to control the characteristics of a channel formed between the active region 20 and the gate electrode 30 after melting or blowing the antifuse structure 10.

The material of the gate electrode 30 may comprise a doped semiconductor material, such as doped polysilicon. The active region 20 and the gate electrode 30 may have the same doping type. The gate electrode 30 may be formed on a gate electrode oxide (e.g., the dielectric layer 50 in fig. 1B) on the semiconductor substrate 35.

Still referring to fig. 1, as shown in fig. 1A, the active region 20 includes a first body portion 21 and a first extension portion 22 extending along a first direction D1. The gate electrode 30 includes the first two-body portion 31 and a second extending portion extending in a second direction perpendicular to the first direction D1.

In some embodiments of the present disclosure, the first body portion 21 is substantially rectangular when viewed from a third direction D3 (orthogonal projection). The first extension portion 22 extends from the first body portion 21 along one long side of the first body portion 21. In some embodiments of the present disclosure, a side of the first body portion 21 and a side of the first extension portion 22 are coplanar. In some embodiments of the present disclosure, the first extension portion 22 is substantially rectangular when viewed from the third direction D3.

In some embodiments of the present disclosure, the second body portion 31 is substantially rectangular when viewed from a third direction D3 (perpendicular projection). The second extension portion 32 extends from the second body portion 31 along one long side of the second body portion 31. In some embodiments of the present disclosure, a side of the second body portion 31 and a side of the second extension portion 32 are coplanar. In some embodiments of the present disclosure, the second extension portion 32 is substantially rectangular when viewed from the third direction D3.

In some embodiments of the present disclosure, the first body portion 21 includes a first surface S1 facing the portion of the second body portion 31, and the second body portion 31 includes a second surface S2 facing the portion of the first extension portion 22.

In some embodiments of the present disclosure, a normal vector (normal vector) of the first surface S1 points toward the second body portion 31 along the first direction D1. In some embodiments of the present disclosure, a normal vector of the second surface S2 is directed toward the first extension 22 along the second direction D2.

In some embodiments of the present disclosure, the first extension portion 22 extends from the first body portion 21 along a normal vector to the first surface S1. In some embodiments of the present disclosure, the second extension portion 32 extends from the second body portion 31 along a normal vector to the second surface S2.

In some embodiments of the present disclosure, the first surface S1 is separated from the gate electrode 30 when viewed from the first direction D1, as shown in fig. 1A. In some embodiments of the present disclosure, an edge surface S3 of the gate electrode 30 is proximate to the active region 20 when viewed from the first direction D1, as shown in fig. 2A.

In some embodiments of the present disclosure, the first extension portion 22 and the second extension portion 32 partially overlap in a third direction D3 (to be further described in fig. 1B) perpendicular to the first direction D1 and the second direction D2, and a dielectric layer is sandwiched between the first extension portion 22 and the second extension portion 32. The first extension 22 and the second extension 32 partially overlap and form an intersection region 40.

In some embodiments of the present disclosure, the aspect ratio of intersection region 40 is approximately in the range of 0.9 to 1.5.

It should be appreciated that the size of the crossover region 40 is critical to the programmable voltage of the fused antifuse structure 10. In other words, a larger cross-over region 40 corresponds to a higher programmable voltage. There is a suitable programmable voltage range. The antifuse structure 10 needs to maintain a normal voltage without blowing and cannot allow a programmable voltage too low to blow the antifuse structure 10. On the other hand, the antifuse structure 10 must be configured to melt when the applied voltage meets a desired value, and too high a programmable voltage will cause the antifuse structure 10 to fail.

If the aspect ratio of intersection region 40 is less than about 0.9, intersection region 40 is insufficient to maintain a normal voltage before the antifuse fuses. If the aspect ratio of the intersection region 40 is greater than about 1.5, the intersection region 40 may be too large to melt properly at a suitable voltage.

Referring to fig. 1B, the first extension portion 22 and the second extension portion 22 partially overlap in a third direction, and a dielectric layer 50 is sandwiched between the first extension portion 22 and the second extension portion 32.

In some embodiments, the dielectric layer 50 includes a gate oxide (gate oxide). In the case where the gate oxide isolates the first extension 22 from the second extension 32, the path between the first extension 22 and the second extension 32 remains open unless the programmable voltage is applied.

In some embodiments of the present disclosure, the dielectric layer 50 directly contacts the second extension portion 32. In some embodiments of the present disclosure, the top view area of the dielectric layer 50 is substantially equal to the top view area of the second extension portion 32.

In some embodiments of the present disclosure, the dielectric layer 50 is recessed into the semiconductor substrate 35. In some embodiments of the present disclosure, the dielectric layer 50 directly contacts the first extension portion 22.

In some embodiments of the present disclosure, an insulating layer 25 covers the active region 20 and the gate electrode 30. In some embodiments of the present disclosure, the gate electrode 30 is recessed in the insulating layer 25 and proximate to a surface of the insulating layer 25.

In some embodiments of the present disclosure, the insulating layer 25 has a common surface with the semiconductor substrate 35, and the active region 20 and the gate electrode 30 are both proximate to the common surface.

Referring to fig. 1C, in some embodiments of the present disclosure, a first conductive via 23 is formed on the first body portion 21 and electrically connected to the active region 20.

In some embodiments of the present disclosure, the first conductive via 23 extends through the thickness of the insulating layer 25 and is connected to a conductor, such as a signal line for applying the programmable voltage.

In some embodiments of the present disclosure, another conductive via 24 is formed on the first body portion 21 and electrically connected to the active region 20.

Although two conductive vias are illustrated in fig. 1C for simplicity of illustration, it will be apparent to those of ordinary skill in the art that any number of conductive vias may be formed by the present disclosure.

As shown in fig. 1C, two conductive vias extend through the thickness of the insulating layer 25, but the conductive vias of the present disclosure may extend through the thickness of the semiconductor substrate 35, as will be apparent to those of ordinary skill in the art.

Referring to fig. 1D, in some embodiments of the present disclosure, a second conductive via 33 is formed on the second body portion 31 and electrically connected to the gate electrode 30.

In some embodiments of the present disclosure, the second conductive via 33 extends through the thickness of the semiconductor substrate 35 and is connected to a conductor, such as a signal line for applying the programmable voltage. As mentioned above, the second conductive via 33 may extend through the thickness of the insulating layer 25.

In some embodiments of the present disclosure, another conductive via 34 is formed. As described above, any number of conductive vias may be formed.

Until the programmable voltage is applied through conductive via 23, 24, 33 or 34, antifuse structure 10 remains open, and dielectric layer 50 undergoes a dielectric breakdown process when the programmable voltage is applied. Leakage current increases and a thermal runaway condition occurs, melting the dielectric layer 50 and the adjacent conductive materials (e.g., active region 20 and gate electrode 30). The conductive material flows from the two conductors and forms a conductive filament that creates a short circuit between the two conductors.

Fig. 2A is a top view illustrating an antifuse structure 60 according to some embodiments of the present disclosure. Fig. 2B is a sectional view taken along line D-D' in fig. 2A.

Antifuse structure 60 is similar to antifuse structure 10, and like numerals represent like parts for simplicity of description. For the sake of brevity, these similar components are omitted from the description, and only the differences are described.

The anti-fuse structure 60 includes an active region 20 and a gate electrode 30 over the active region 20. The active region 20 includes a first body portion 21 and a first extension portion 22 extending along a first direction D1.

As shown in fig. 2A, the line of symmetry of the first extension portion 22 is aligned with the line of symmetry of the first body portion 21.

Still referring to fig. 2A, the gate electrode 30 includes a second body portion 81 and two second extension portions 82 and 82', the second extension portions 82 and 82' extending from the second body portion 81 in the first direction D1 and being separated from each other by a space 84.

In some embodiments of the present disclosure, the second body portion 81 includes an edge surface S3, the edge surface S3 being opposite a surface from which the two second extension portions 82 and 82' extend. In some embodiments of the present disclosure, the edge surface S3 approaches the first body portion 21 in the first direction D1.

Two second extension portions 82 and 82' extend from the second body portion 81 along a normal vector to the edge surface S3. Two second extension portions 82 and 82' extend from the second body portion 81 in a direction away from the edge surface S3.

In some embodiments of the present disclosure, the two second extensions 82 and 82' have an extension width w1, and the space 84 has a space width w2 that is greater than the extension width w 1.

In some embodiments of the present disclosure, a surface of one of the two second extension portions 82 and 82' is aligned with a surface of the first body portion 21.

When the antifuse structure 60 is fused and the circuit path between the active region 20 and the gate electrode 30 is conductive, the current is split into two paths, i.e., two second extensions 82 and 82'.

In some embodiments of the present invention, first extension 22 has a width w3, with width w3 being greater than extension width w1 and less than space width w 2.

Still referring to fig. 2A, the first extension portion 22 and the second body portion 81 partially overlap in a third direction D3 (perpendicular projection direction), and a dielectric layer 50 (see fig. 2B) is sandwiched between the first extension portion 22 and the second body portion 81 to form an intersection region 90.

In some embodiments of the present disclosure, the aspect ratio of intersection region 90 is approximately in the range of 0.9 to 1.5.

In some embodiments of the present disclosure, the first extension portion 22 extends beyond the second body portion 81 and protrudes from the space 84, a portion of the first extension portion 22 being present between the two second extension portions 82 and 82' when viewed from the third direction D3.

In some embodiments of the present disclosure, two second extension portions 82 and 82' extend further from the second body portion 81 than the first extension portion 22.

In some embodiments of the present disclosure, the gate electrode 30 further comprises a third body portion 83, wherein two second extension portions 82 and 82' extend between the second body portion 81 and the third body portion 83. In some embodiments of the present disclosure, two second extension portions 82 and 82' are connected to the second body portion 81 and the third body portion 83. In some disclosed embodiments, the two second extension portions 82 and 82', the second body portion 81 and the third body portion 83 together surround the space 84.

In some embodiments of the present disclosure, the first extension portion 22 includes a convex surface S4 facing the third body portion 83. In some embodiments of the present disclosure, the projection surface S4 is located in the space 84 and when viewed from the third direction D3, the projection surface S4 is surrounded by both the second extension portions 82 and 82', the second body portion 81, and the third body portion 83.

Referring to fig. 2B, in some embodiments of the present disclosure, the antifuse structure 60 includes a first conductive via 23 formed on the first body portion 21, electrically connected to the active region 20.

In some embodiments of the present disclosure, another conductive via 24 is formed on the first body portion 21 and electrically connected to the active region 20.

In some embodiments of the present disclosure, the antifuse structure 60 includes a second conductive via 33 formed on the third body portion 83, which is electrically connected to the gate electrode 30.

The present disclosure provides an antifuse structure. The anti-fuse structure includes an active region and a gate electrode over the active region. The active region includes a first body portion and a first extension portion extending in a first direction. The gate electrode includes a second body portion and a second extension portion extending in a second direction perpendicular to the first direction. The first body portion includes a first surface facing a portion of the second body portion, and the second body portion includes a second surface facing a portion of the first extension portion. The first extending portion and the second extending portion are partially overlapped in a third direction perpendicular to the first direction and the second direction, and a dielectric layer is sandwiched between the first extending portion and the second extending portion to form a crossing region.

The present disclosure provides an antifuse structure. The anti-fuse structure includes an active region and a gate electrode over the active region. The active region includes a first body portion and a first extension portion extending in a first direction. The gate electrode includes a second body portion and two second extension portions. The second extension portion extends from the second body portion in the first direction, and the second body portion and the two second extension portions are separated from each other by a space. The first extending portion and the second extending portion are partially overlapped in a vertical projection direction perpendicular to the first direction, and a dielectric layer is sandwiched between the first extending portion and the second extending portion to form a crossing region.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.