阅读说明：本技术 一种键合墙体扇出器件的三维封装结构和方法 (Three-dimensional packaging structure and method for bonding wall fan-out device ) 是由 于大全 于 2019-08-08 设计创作，主要内容包括：一种键合墙体扇出器件的三维封装结构和方法,器件第一表面具有功能区和若干焊盘；其特征在于：器件除第一表面外具有包封材料；在器件第一表面制备有墙体结构并延展至包封材料第一表面,该墙体结构局部覆盖至少一焊盘且在焊盘处设有第一开口；设置有一盖板与墙体结构粘结,并在器件的功能区形成空腔结构,盖板上具有至少一个与第一开口相通的第二开口；盖板表面设置有金属互连结构通过第一开口、第二开口与焊盘电性连接。本发明能提高整体结构可靠性,降低风险、降低成本。(A three-dimensional packaging structure and a method for a bonding wall fan-out device are provided, wherein a first surface of the device is provided with a functional area and a plurality of bonding pads; the method is characterized in that: the device has an encapsulant material in addition to the first surface; preparing a wall structure on the first surface of the device and extending to the first surface of the packaging material, wherein the wall structure partially covers at least one bonding pad and is provided with a first opening at the bonding pad; a cover plate is arranged to be bonded with the wall structure, a cavity structure is formed in the functional area of the device, and the cover plate is provided with at least one second opening communicated with the first opening; the surface of the cover plate is provided with a metal interconnection structure which is electrically connected with the bonding pad through the first opening and the second opening. The invention can improve the reliability of the whole structure, reduce the risk and reduce the cost.)

1. A three-dimensional packaging structure of a bonding wall fan-out device is provided, wherein a first surface of the device is provided with a functional area and a plurality of bonding pads; the method is characterized in that: the device has an encapsulant material in addition to the first surface; preparing a wall structure on the first surface of the device and extending to the first surface of the packaging material, wherein the wall structure partially covers at least one bonding pad and is provided with a first opening at the bonding pad; a cover plate is arranged to be bonded with the wall structure, a cavity structure is formed in the functional area of the device, and the cover plate is provided with at least one second opening communicated with the first opening; the surface of the cover plate is provided with a metal interconnection structure which is electrically connected with the bonding pad through the first opening and the second opening.

2. The three-dimensional package structure of a bonded wall fan-out device of claim 1, wherein: the cover plate is a polymer film, glass, silicon or ceramic.

3. The three-dimensional package structure of a bonded wall fan-out device of claim 1, wherein: the wall structure is a polymer, glass, ceramic or insulator.

4. The three-dimensional package structure of a bonded wall fan-out device of claim 1, wherein: the device is made of lithium niobate, lithium tantalate, glass or silicon.

5. The three-dimensional package structure of a bonded wall fan-out device of claim 1, wherein: the encapsulating material is polymer, plastic package material, epoxy resin or glass paste.

6. The three-dimensional package structure of a bonded wall fan-out device of claim 1, wherein: the metal interconnection structure comprises a conductive line, a passivation layer and a signal port; the conductive circuit is insulated from the cover plate, and is arranged on the surface of the cover plate and extends to the second opening and the first opening to be electrically connected with the bonding pad; the passivation layer covers the exposed surfaces of the conducting circuit and the cover plate and is provided with a third opening; the signal port is positioned at the third opening and electrically connected with the conductive circuit.

7. The three-dimensional packaging structure of a bonded wall fan-out device of claim 6, wherein: the signal port is a BGA solder ball, a nickel-palladium-gold, a nickel-gold or a titanium-copper bonding pad.

8. A three-dimensional packaging method of a bonded wall fan-out device is characterized by comprising the following steps: comprises that

1) Scribing the device wafer;

2) placing the device on a temporary carrier plate by picking and placing;

3) encapsulating the device;

4) separating the encapsulated device from the carrier plate to obtain a reconstructed wafer or square plate with the encapsulating material;

5) manufacturing a wall structure on the edge of the first surface of the device and the first surface of the packaging material, partially extending to cover at least one bonding pad, and opening the bonding pad;

6) adding a cover plate on the surface of the wall structure to form a cavity in the functional area, and opening at the welding pad;

7) and manufacturing a metal interconnection structure to be electrically connected with the bonding pad.

9. The method of three-dimensional encapsulation of a bonded wall fan-out device of claim 8, wherein: and 3), packaging by adopting plastic packaging, film pressing or glue brushing.

Technical Field

The invention relates to the field of semiconductor packaging, in particular to a three-dimensional packaging structure and a three-dimensional packaging method of a bonded wall fan-out device.

Background

For many MEMS, such as accelerometers, RF switches, gyroscopes, and various sensors, such as filters, CMOS image sensors, it is necessary to form a protective cavity to protect the device and provide a vacuum or hermetic working environment for the device. With the development of technology, the size of a chip is smaller, and for many devices, such as a SAW filter and a CMOS image sensor, a sealing wall cannot be arranged on the surface of the device, so that the size of the wall for forming a cavity is narrower, and the reduction of the bonding area greatly affects the reliability of the device due to the bonding force. New low cost, high reliability solutions must be sought.

Fanout packaging is currently one of the mainstream advanced packaging technologies. With the further improvement of the integration level of the chip and the further increase of the I/O number, the product requirements of the conventional wafer level package (WLCSP) are difficult to meet, and the contradiction between the excessive I/O number and the small chip area in the WLCSP needs to be solved. In 2004, the wafer level fanout ewlb (embedded wafer level bga) technology was proposed by english flying (patent No. US6727576B 2). The technology is mainly characterized in that a new fan-out plane is constructed around the chip by using a molding compound and the surface of the chip, and metal wiring is led from the chip to the fan-out plane. The fan-out packaging technique is in principle no longer limited by the chip size, the number of I/os, and the solder ball pitch can all be no longer limited by the chip size. Because the substrate is not adopted, the thickness of the package is reduced, and the packaging structure has the advantages of excellent cost and electrical property.

With the gradual maturity of the FOWLP process technology, the cost is continuously reduced, and meanwhile, with the continuous improvement of the chip process, the FOWLP will have explosive growth. In order to improve the thickness and the electrical performance of the PoP package of the conventional pitch AP processor, a three-dimensional FOWLP stacking technology for manufacturing through hole interconnection on molding compound is further developed on the basis of the FOWLP technology. Typically, the InFO technology developed by station power station is used to provide package services for apple processors a10, a11 and a12, which has brought the trend of developing a three-dimensional FOWLP stacking technology in the whole industry.

Disclosure of Invention

The invention mainly aims to overcome the defects in the prior art and provides a three-dimensional packaging structure and a method for bonding a wall fan-out device, which improve the reliability and reduce the risk and the cost.

The invention adopts the following technical scheme:

a three-dimensional packaging structure of a bonding wall fan-out device is provided, wherein a first surface of the device is provided with a functional area and a plurality of bonding pads; the method is characterized in that: the device has an encapsulant material in addition to the first surface; preparing a wall structure on the first surface of the device and extending to the first surface of the packaging material, wherein the wall structure partially covers at least one bonding pad and is provided with a first opening at the bonding pad; a cover plate is arranged to be bonded with the wall structure, a cavity structure is formed in the functional area of the device, and the cover plate is provided with at least one second opening communicated with the first opening; the surface of the cover plate is provided with a metal interconnection structure which is electrically connected with the bonding pad through the first opening and the second opening.

Preferably, the cover plate is a polymer film, glass, silicon or ceramic.

Preferably, the wall structure is a polymer, glass, ceramic or insulator.

Preferably, the material of the device is lithium niobate, lithium tantalate, glass or silicon.

Preferably, the encapsulating material is a polymer, a molding compound, an epoxy resin or a glass paste.

Preferably, the metal interconnection structure comprises a conductive line, a passivation layer and a signal port; the conductive circuit is insulated from the cover plate, and is arranged on the surface of the cover plate and extends to the second opening and the first opening to be electrically connected with the bonding pad; the passivation layer covers the exposed surfaces of the conducting circuit and the cover plate and is provided with a third opening; the signal port is positioned at the third opening and electrically connected with the conductive circuit.

Preferably, the signal port is a BGA solder ball, a nickel-palladium-gold, a nickel-gold or a titanium-copper pad.

A three-dimensional packaging method of a bonded wall fan-out device is characterized by comprising the following steps: comprises that

1) Scribing the device wafer;

2) placing the device on a temporary carrier plate by picking and placing;

3) encapsulating the device;

4) separating the encapsulated device from the carrier plate to obtain a reconstructed wafer or square plate with the encapsulating material;

5) manufacturing a wall structure on the edge of the first surface of the device and the first surface of the packaging material, partially extending to cover at least one bonding pad, and opening the bonding pad;

6) adding a cover plate on the surface of the wall structure to form a cavity in the functional area, and opening at the welding pad;

7) and manufacturing a metal interconnection structure to be electrically connected with the bonding pad.

Preferably, in the step 3), plastic packaging, film pressing or glue brushing is adopted for encapsulation.

As can be seen from the above description of the present invention, compared with the prior art, the present invention has the following advantages:

1. the invention adopts the packaging material to package the device except the first surface, the wall structures are arranged on the first surfaces of the device and the packaging material to support the cover plate and form the large cavity, and the wall structure is manufactured by the fan-out area, so that the wall structure has enough positions to be widened, the reliability of the whole structure is improved, the risk is reduced, and the cost is reduced.

2. The structure and the method of the invention ensure that the wafer is not fragile any more by reconstructing the wafer, are beneficial to improving the process yield of products, are easy to process and reduce the risk of fragment.

3. The structure and the method of the invention enlarge the area of the device, reduce the area of the area without the device, increase the number of the devices for the same raw material and reduce the cost.

4. The structure and the method of the invention can adopt wafer level packaging, are suitable for large-scale batch production, reduce the production cost and ensure the consistency of the device performance.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a device wafer structure view;

FIG. 3 is a schematic drawing of dicing;

FIG. 4 is a top view of FIG. 3;

FIG. 5 is a schematic view of placing a chip into a temporary carrier;

FIG. 6 is a schematic illustration of encapsulation;

FIG. 7 is a top view of FIG. 6;

FIG. 8 is a schematic view of the key removal;

FIG. 9 is a schematic view of a wall structure;

FIG. 10 is a top view of FIG. 9;

FIG. 11 is a schematic view of fabricating a cover plate;

FIG. 12 is a device conductive trace schematic;

FIG. 13 is a top view of FIG. 11;

FIG. 14 is a block diagram of the present invention (not diced);

wherein: 10. device, 11, pad, 12, functional area, 13, cavity, 20, encapsulating material, 30, wall structure, 31, first opening, 40, cover plate, 41, second opening, 50, conductive line, 60, passivation layer, 61, third opening, 70, signal port, 80, temporary carrier.

Detailed Description

The invention is further described below by means of specific embodiments.

Referring to fig. 1, a three-dimensional packaging structure of a bonded wall fan-out device includes a device 10, an encapsulation material 20, a wall structure 30, a cover plate 40, a metal interconnection structure and the like. The first surface of the device 10 is provided with pads 11 and functional areas 12. The functional region 12 is provided with IDTs, and the pads 11 may be aluminum pads, aluminum nickel gold pads, aluminum nickel palladium gold pads, and the like. The chip type of the device is a SAW filter, a BAW filter or other filter devices with similar functions, and the device 10 is the device 10 obtained by cutting wafer materials such as lithium niobate, lithium tantalate, glass, silicon and the like.

The encapsulating material 20 encapsulates the device 10 except for the first surface, and referring to fig. 1, the encapsulating material 20 encapsulates four side edges and one bottom edge of the device 10, with the top edge of the device being the first surface and not being encapsulated. The encapsulating material 20 can be realized by plastic packaging, film pressing or glue brushing, and the encapsulating thickness can be set according to the requirement. The encapsulating material may be a polymer, a molding compound, an epoxy resin, or a glass paste, etc.

The wall structure 30 is disposed at the edge of the first surface of the device 10 and the first surface of the encapsulating material 20, the first surface of the encapsulating material 20 is on the same plane as the first surface of the device 10, that is, the wall structure 30 covers the interface between the first surfaces of the device 10 and the encapsulating material 20, and the wall structure 30 may completely cover or partially cover the first surface of the encapsulating material 20.

The wall structure 30 also partially extends to cover at least one pad 11, and a first opening 31 is provided at the pad 11, and the first opening 31 is located on the upper surface of the pad 11. The area of the first opening 31 is slightly smaller than the area of the pad 11. The number of the pads covered by the wall structure 30 may be one, two, three or even all of the pads, which is not limited herein. The wall structure 30 may be a polymer, glass, ceramic, or insulator, etc.

The cover plate 40 covers the surface of the wall structure 30 to form the cavity 13 at the functional region 12, and is provided with a second opening 41 at the land 11. The height of the cavity 13 is determined by the thickness of the wall structure 30. The second opening 41 is communicated with the first opening 31, and the area of the second opening 41 can be slightly larger than or equal to the area of the first opening 31, preferably larger than. The cover plate 40 may be a polymer film, glass, silicon, or ceramic.

The metal interconnection structure is disposed on the surface of the cover plate 40 and extends to the second opening 41 and the first opening 31 to electrically connect with the pad 11. The metal interconnection structure includes conductive lines 50, a passivation layer 60, signal ports 70, and the like. The conductive circuit 50 is insulated from the cover plate 40, is disposed on the surface of the cover plate 40 and extends to the second opening 41 and the first opening 31 to be electrically connected to the pad 11, and the conductive circuit 50 is made of a metal material. The passivation layer 60 covers the exposed surfaces of the conductive traces 50 and the cover plate 40, and is provided with a third opening 61 in the outer connection region. The signal port 70 is located at the third opening 61 to electrically connect with the conductive trace 50.

The passivation layer 60 is used to protect the conductive traces 50, and may be made of a polymer material, so as to improve the insulating property of the product and prevent oxidation of the conductive traces 50. The signal port 70 is a BGA solder ball, ni-pd-au, ni-au or ti-cu pad. The implementation of the metal interconnection structure of the present invention is not limited thereto, and other metal external connection structures can be used.

The invention also provides a three-dimensional packaging method of the bonded wall fan-out device, which is used for manufacturing the three-dimensional packaging structure of the bonded wall fan-out device and comprises the following steps:

1) referring to fig. 4, a filter wafer is selected and the device wafer is diced to yield individual devices 10. The device wafer is a wafer of lithium niobate, lithium carbonate or the like, and the structure diagram after dicing is shown in fig. 3 and 4.

2) The device 10 is placed on the temporary carrier board 80 by pick and place using the alignment marks, see fig. 5.

3) And (3) encapsulating the first surface of the device 10 by plastic packaging, film pressing or glue brushing, wherein the encapsulating material is polymer, plastic packaging material, epoxy resin or glass paste and the like, as shown in fig. 6 and 9.

4) The encapsulated device is separated from the temporary carrier plate 80, i.e. the temporary carrier plate 80 is removed resulting in a reconstituted wafer or square plate with encapsulating material 20, see fig. 8.

5) Wall structures 30 are formed on the edges of the first surface of the device 10 and the first surface of the encapsulating material 20 and partially extend to cover at least one bonding pad 11, and a first opening 31 is formed at the bonding pad 11, wherein the wall structures 30 can be polymers, glass, ceramics or insulators, as shown in fig. 9 and 10.

6) A cover plate 40 is covered on the surface of the wall structure 30, so that a cavity 13 is formed in the functional region 12 of the device 10, and a second opening 41 is formed at the bonding pad 11. The cover plate 40 may be a dry film, glass, silicon, or ceramic material, and may be opened by photolithography or laser, as shown in fig. 11 and 13.

7) And manufacturing a metal interconnection structure to be electrically connected with the bonding pad 11. Specifically, a conductive trace 50 is formed on the surface of the cover plate 40, and extends to the second opening 41 and the first opening 31 to be electrically connected to the pad 11, as shown in fig. 12; a passivation layer 60 is then formed to cover the exposed surfaces of the conductive traces 50 and the cover plate 40, and a third opening 61 is formed by performing a photolithographic opening in the interconnect area. A signal port 70 is formed at the third opening 61 of the external connection region to electrically connect with the conductive trace 50. The signal port 70 may be a conventional signal port such as a BGA solder ball, a ni-pd-au, a ni-au or a ti-cu pad.

8) Referring to fig. 14, the fabricated wafer or square board is diced to obtain a final package.

For the problem that the reliability of a device is further influenced due to the fact that the area of a chip is reduced and the size of a bonding wall body is narrowed, the invention provides a method for solving the problem of the reliability of a wafer-level package with a closed cavity caused by the fact that the size of the chip is reduced by fanning out the bonding wall body in order to meet the standard overall dimension of the package. The invention is different from the fan-out type packaging standard in fan-out of the metal wiring electrical signal, the device is scribed and then embedded into another material, and the wall structure is manufactured by the fan-out area, so that the wall structure has enough positions to be widened, a large cavity is realized, the reliability is high, and the cost is reduced.

The above description is only an embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by using the design concept should fall within the scope of infringing the present invention.