阅读说明：本技术 包含加固角部支撑件的半导体装置 (Semiconductor device including reinforced corner support ) 是由 刘扬名 叶宁 邱进添 于 2018-06-28 设计创作，主要内容包括：公开了一种半导体装置,其在装置的角部处具有加固支撑。半导体装置可以在装置的下表面上包含焊料球,以将装置焊接到印刷电路板上。在一个示例中,可以由支撑坯替换半导体装置的角部处的焊料球,支撑坯具有更大质量和半导体装置与PCB之间的更大的接触面积。在其他示例中,可以在装置的角部处提供螺钉(取代角部焊料球或附加于角部焊料球)。这些螺钉可放置为穿过半导体装置的角部并进到印刷电路板中。(A semiconductor device is disclosed having reinforcing supports at the corners of the device. The semiconductor device may include solder balls on a lower surface of the device to solder the device to the printed circuit board. In one example, solder balls at corners of the semiconductor device may be replaced by a support blank having a greater mass and a greater contact area between the semiconductor device and the PCB. In other examples, screws may be provided at the corners of the device (instead of or in addition to corner solder balls). These screws may be placed through the corners of the semiconductor device and into the printed circuit board.)

1. A semiconductor device, comprising:

a substrate, the substrate comprising:

a solder ball configured to couple the semiconductor device to a host device, an

Corner structural supports at corners of the substrate, the corner structural supports having a higher strength than the solder balls; and

one or more semiconductor die coupled to the substrate.

2. The semiconductor device of claim 1, wherein the corner structural support comprises a structural blank.

3. The semiconductor device of claim 1, wherein the corner structural support comprises a copper blank.

4. The semiconductor device of claim 1, wherein the structural support comprises a single structural blank in each of four corners of the substrate.

5. The semiconductor device of claim 1, wherein the structural support comprises a plurality of structural blanks in each of four corners of the substrate.

6. The semiconductor device of claim 1, wherein the structural support comprises a structural blank that is not part of a conductive pattern used to transmit signals to and from the one or more semiconductor die.

7. The semiconductor device of claim 1, wherein the corner structural support comprises a screw fitted through a screw hole at a corner of the semiconductor device, the screw configured to attach to the host device.

8. The semiconductor device according to claim 7, further comprising a no-entry region on the substrate, the no-entry region being around the screw hole passing through the substrate, no conductive pattern being formed in the no-entry region.

9. A semiconductor device, comprising:

a substrate, the substrate comprising:

a solder ball configured to couple the semiconductor device to a host device, an

One or more structural blanks at each of the corners of the substrate, the one or more structural blanks having a higher strength than the solder balls; and

one or more semiconductor die coupled to the substrate.

10. The semiconductor device of claim 9, wherein the one or more structural blanks are formed on a side of the substrate opposite the one or more semiconductor die.

11. The semiconductor device of claim 9, wherein the one or more structural blanks are formed of copper.

12. The semiconductor device of claim 9, wherein the one or more structural blanks have a circular cross-section.

13. The semiconductor device of claim 9, wherein the one or more structural blanks have one of a rectangular cross-section and an L-shaped cross-section.

14. The semiconductor device of claim 9, wherein the one or more structural blanks are not part of a conductive pattern used to transmit signals to and from the one or more semiconductor die.

15. The semiconductor device of claim 9, wherein the one or more structural blanks are part of a conductive pattern for transmitting signals to and from the one or more semiconductor die.

16. A host device for receiving a semiconductor device, the host device comprising:

a pattern of contact pads configured to receive a plurality of solder balls of a set of contact pads on the semiconductor device; and

a structure blank at a corner of the pattern of contact pads on the host device, the structure blank configured to mate with corner contact pads of the set of contact pads on the semiconductor device.

17. The host device of claim 16, wherein the host device is a printed circuit board.

18. The host device of claim 16, wherein the structural blank is formed of copper.

19. The host device of claim 16, wherein a structure blank on the host device is configured to have a higher strength than a solder ball of a plurality of solder balls on the semiconductor device.

20. A semiconductor device, comprising:

a substrate;

one or more semiconductor die coupled to the substrate; and

a molding compound around the one or more semiconductor die;

wherein a screw hole is formed through the substrate and molding compound at a corner of the semiconductor device, the screw hole configured to receive a screw to screw the semiconductor device down onto a host device.

21. The semiconductor device according to claim 20, further comprising a no-entry region on the substrate, the no-entry region being around the screw hole passing through the substrate, no conductive pattern being formed in the no-entry region.

22. A semiconductor device, comprising:

a substrate, the substrate comprising:

a solder ball configured to couple the semiconductor device to a host device, an

A structural support member to structurally support the semiconductor device on a host device, the structural support member being provided at a corner of the substrate and having a higher strength than the solder ball; and

one or more semiconductor die coupled to the substrate.

Technical Field

The present invention relates generally to semiconductor devices and, more particularly, to semiconductor devices including reinforced corner supports.

Background

The strong growth in demand for portable consumer electronic devices is driving the demand for mass storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-increasing demand for digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs and cellular telephones.

While many different packaging configurations are known, flash memory semiconductor devices may generally be manufactured as system-in-package (SIP) or multi-chip modules (MCM) in which multiple semiconductor die are mounted and interconnected to the upper surface of a small-footprint substrate. The substrate may generally comprise a rigid, dielectric base having a conductive layer etched on one or both sides. Solder balls are typically mounted on contact pads formed on the lower surface of the substrate to allow the substrate to be soldered to a host device such as a printed circuit board. Once installed, signals may be transmitted between the semiconductor die and the host device via the substrate.

In conventional board-level semiconductor products, mechanical stress is often generated at the solder ball joints between substrate pads and PCB (printed circuit board) pads. For example, these stresses may be generated due to different thermal expansion coefficients of the semiconductor package and the PCB, for example, during thermal cycling testing of board-level semiconductor products. These stresses may also be generated due to shock vibration to the solder ball, for example, during handling or drop testing of the semiconductor device. Such stresses tend to be high at the corner solder ball bonds and may cause Board Level Reliability (BLR) failures at these corner bonds.

Disclosure of Invention

In summary, in one example, the present technology relates to a semiconductor device comprising: a substrate, the substrate comprising: a solder ball configured to couple the semiconductor device to a host device, and a corner structural support at a corner of the substrate, the corner structural support having a higher strength than the solder ball; and one or more semiconductor die coupled to the substrate.

In another example, the present technology relates to a semiconductor device comprising: a substrate, the substrate comprising: a solder ball configured to couple the semiconductor device to a host device, and one or more structural blanks at each of the corners of the substrate, the one or more structural blanks having a higher strength than the solder ball; and one or more semiconductor die coupled to the substrate.

In another example, the present technology relates to a host device for receiving a semiconductor device, the host device comprising: a pattern of contact pads configured to receive a plurality of solder balls on a set of contact pads on a semiconductor device; and a structural blank at a corner of the pattern of contact pads on the host device, the structural blank configured to mate with corner contact pads of the set of contact pads on the semiconductor device.

In other examples, the present technology relates to a semiconductor device comprising: a substrate; one or more semiconductor die coupled to a substrate; and a molding compound around the one or more semiconductor die; wherein screw holes are formed at corners of the semiconductor device, through the substrate and the molding compound, the screw holes configured to receive screws for screwing the semiconductor device down onto a host device.

In another example, the present technology relates to a semiconductor device comprising: a substrate, the substrate comprising: a solder ball configured to couple the semiconductor device to a host device, and a structural support member for structurally supporting the semiconductor device on the host device, the structural support member being provided at a corner of the substrate and having a higher strength than the solder ball; and one or more semiconductor die coupled to the substrate.

Drawings

Fig. 1 is a flow chart of an overall manufacturing process of a substrate and a semiconductor device using the substrate in accordance with an embodiment of the present technology.

Fig. 2 is a side view of a substrate of a semiconductor device at a first step in the fabrication process, in accordance with embodiments of the present technique.

Fig. 3 is a top view of the substrate of fig. 2.

Fig. 4 is a side view of a substrate of a semiconductor device at a second step in the fabrication process, in accordance with embodiments of the present technique.

Fig. 5 is a top view of the substrate of fig. 4.

Fig. 6 is a bottom view of the substrate of fig. 4.

Fig. 7 is a side view of a number of semiconductor die mounted on a substrate in accordance with embodiments of the present technology.

Fig. 8 is a perspective view of a number of semiconductor die mounted on and wire bonded to a substrate in accordance with embodiments of the present technology.

Fig. 9 is a side view of a semiconductor device in accordance with embodiments of the present technique.

Fig. 10 is a side view of a completed semiconductor device mounted on a host device.

Fig. 11 is a sectional bottom view through line 11-11 of fig. 10.

Fig. 12-14 are cross-sectional bottom views through line 11-11 of fig. 10, in accordance with alternative embodiments of the present technique.

Fig. 15 and 16 are cross-sectional views of a semiconductor device mounted on a host device in accordance with an alternative embodiment of the present technique.

Fig. 17 and 18 are perspective views in the case where the corner support structure includes a screw to fix the semiconductor device to the host device.

Detailed Description

The present technology will now be described with reference to the accompanying drawings, which in embodiments relate to a semiconductor device having reinforcing supports at the corners of the device. The semiconductor device may include solder balls on a lower surface of the device to solder the device to a PCB (printed circuit board). In one example, solder balls at corners of the semiconductor device may be replaced with a support blank having a greater mass and a greater contact area between the semiconductor device and the PCB. In other examples, screws may be provided at the corners of the device (instead of or in addition to corner solder balls). These screws may be placed through the corners of the semiconductor device and into the PCB.

It should be understood that the present technology may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technology to those skilled in the art. Indeed, the present technology is intended to cover alternatives, modifications, and equivalents of these embodiments, which may be included within the scope and spirit of the present technology as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it will be apparent to one of ordinary skill in the art that the present technology may be practiced without these specific details.

The terms "top" and "bottom", "upper" and "lower" and "vertical" and "horizontal" as may be used herein are by way of example only and for purposes of illustration, and are not intended to limit the description of the technology as the items involved may be interchanged in position and orientation. Additionally, as used herein, the terms "substantially," "approximately," and/or "about" mean that the specified dimensions or parameters may vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is ± 0.25% of the given dimension.

Embodiments of the present technique will now be explained with reference to the flow chart of fig. 1 and the top, side and perspective views of fig. 2-18. Although the figures illustrate a single semiconductor device 150 or a portion thereof, it should be understood that the device 150 may be mass-produced on a substrate panel along with a plurality of other semiconductor devices to achieve economies of scale. The number of rows and columns of devices 150 on the substrate panel may vary.

A substrate panel for manufacturing semiconductor devices 150 begins with a plurality of substrates 100 (again, one such substrate is shown in fig. 2-6). Substrate 100 may be a variety of different chip carrier media including a Printed Circuit Board (PCB), lead frame, or Tape Automated Bonding (TAB) tape. Where the substrate 100 is a PCB, the substrate may be formed from a core 102 as shown in fig. 2. The core 102 may be formed of various dielectric materials, for example, a polyimide laminate, an epoxy resin containing FR4 and FR5, Bismaleimide Triazine (BT), and the like. The core may have a thickness of between 40 micrometers (μm) and 200 μm, although the thickness of the core may vary outside of this range in alternative embodiments. The core 102 may be ceramic or organic in alternative embodiments.

In step 200, conductive layers 104 and 105 may be formed on the exposed planar surfaces of the dielectric core 102, as shown in the edge and top views of fig. 2 and 3, respectively. The conductive layers 104, 105 may be formed of copper or copper alloy, plated copper or plated copper alloy, alloy 42(42Fe/58Ni), copper plated steel, or other metals and materials suitable for use on the substrate panels. The conductive layers 104, 105 may have a thickness of about 8 μm to 40 μm, although the thickness of the layers may vary outside of this range in alternative embodiments.

In step 202, a conductive pattern of vias, leads, and/or pads is formed in the substrate 100 and through the substrate 100. The substrate 100 may be drilled to define a through-hole via (via) 106, which is then plated and/or filled with a conductive metal. Conductive patterns of electrical traces 108 and contact pads 110 may then be formed on the top and/or bottom major planar surfaces of the substrate 100. Fig. 3 shows an example of a conductive pattern comprising traces 108 and contact pads 110 formed on a first major planar surface 112 of the substrate 100. Fig. 6 shows an example of a conductive pattern comprising traces 108 and contact pads 110 formed on a second major planar surface 114 of the substrate 100.

The pattern of vias 106, traces 108, and contact pads 110 shown on surfaces 112 and 114 in the figures is by way of example, and substrate 100 may contain more or fewer vias, traces, and/or contact pads in other embodiments, and they may be in different locations in other embodiments. The conductive patterns on the top and/or bottom surface of the substrate 100 may be formed by various known processes including, for example, various photolithographic processes.

In accordance with aspects of the present technique, a support blank may be provided at one or more contact pads 110a at each of the corners of the substrate 100, as explained below. The contact pads 110a receiving the support blank may be identical to the other contact pads 110. However, in other embodiments, contact pad 110a may be thicker, larger, and/or formed of a more rigid material than other contact pads 110. In an embodiment, contact pads 110a are provided for structural support and not for signal transmission. In such an embodiment, the contact pad 110a need not have a trace 108 connected thereto. However, in other embodiments, contact pad 110a may be used for signal communication.

Referring again to fig. 1, the substrate 100 may next be inspected in step 204. This step may include Automated Optical Inspection (AOI). Once inspected, solder mask 118 may be applied to the upper and/or lower surfaces of the substrate in step 206, as shown in the edge, top and bottom views of FIGS. 4, 5 and 6, respectively. After the solder mask is applied, the contact pads 110, as well as any other areas to be soldered on the conductive pattern, may be plated in step 208 with, for example, Ni/Au, alloy 42, etc., in a known electroplating or thin film deposition process. The substrate 100 may next undergo operational testing in step 210 to ensure that the substrate 100 is functioning properly. In step 212, the substrate may be visually inspected, including, for example, Automated Visual Inspection (AVI) and Final Visual Inspection (FVI), for contamination, scratches, and discoloration (discolouration). In other embodiments, one or more of these steps may be omitted or performed in other orders.

Assuming that the substrate 100 passes inspection, the passive components 122 (fig. 4 and 5) may next be secured to the substrate 100 in step 214. The one or more passive components may include, for example, one or more capacitors, resistors, and/or inductors, although other components are contemplated. The passive components 122 are shown as examples only, and in other embodiments the number, type, and location may vary.

The substrate 100 described above may have a thickness in the range between 0.05mm and 0.3mm, and more particularly 0.08mm or 0.21 mm. It should be understood that the substrate 100 may have other thicknesses in other embodiments. In the above embodiments, the substrate 100 is a two-layer substrate (two conductive layers sandwiched on a dielectric layer). In other embodiments, the substrate 100 may comprise more layers, such as a four layer substrate (four conductive layers dispersed around three dielectric layers).

In step 220, one or more semiconductor die 124 may be mounted on substrate 100, as shown in the edge view of fig. 7. Semiconductor die 124 may be, for example, a memory die such as a 2D NAND flash memory or a 3D BiCS (bit cost scalable), V-NAND, or other 3D flash memory, although other types of die 124 may be used. These other types of semiconductor die include, but are not limited to, controller die such as ASIC, or RAM such as SDRAM, DDR SDRAM, LPDDR, and GDDR.

Where multiple semiconductor die 124 are included, the semiconductor die 124 can be stacked one on top of the other in a variety of configurations. In one example, the die are stacked in an offset stepped configuration to form a stack of die as shown, for example, in fig. 7. The die may instead be stacked directly one on top of the other by using, for example, spacers between each die to leave room for electrical interconnects (explained below). The number of die 124 shown in the stack is merely an example, and embodiments may include a different number of semiconductor die, including, for example, 1, 2, 4, 8, 16, 32, or 64 die. There may be other numbers of die in other embodiments. The die may be secured to the substrate and/or to each other using a die attach film. As one example, the die attach film may be cured to a B-stage to initially secure the die 124 in the stack, and then to a final C-stage to permanently secure the die 124 to the substrate 100.

In step 224, semiconductor die 124 may be electrically interconnected to each other and to substrate 100. Fig. 8 illustrates a perspective view of wire bonds 128, which wire bonds 128 are formed down the stack between corresponding die bond pads on respective die 124 and then bonded to contact pads 110 on surface 112 of substrate 100. The wire bonds may be formed by ball bonding techniques, but other wire bonding techniques are possible. Semiconductor die 124 may be electrically interconnected to each other and to substrate 100 in other embodiments by other methods, including Through Silicon Vias (TSVs).

After electrically connecting the die 124 to the substrate 100, the semiconductor device 150 may be encapsulated in a molding compound 130 in step 228, as shown in fig. 9. The molding compound 130 may comprise, for example, a solid epoxy resin, a phenolic resin, fused silica, crystalline silica, carbon black, and/or a metal hydroxide. Other molding compounds from other manufacturers are contemplated. The molding compound may be applied by various known processes, including by compression molding, FFT (free flow film) molding, transfer molding, or injection molding techniques.

In step 230, solder balls 132 may be secured to the contact pads 110 on the lower surface 114 of the substrate 100, as shown in fig. 11 and 12. Solder balls 132 may be used to solder the semiconductor device to a host device, such as a printed circuit board. The pattern of contact pads 110 and solder balls 132 shown on the bottom surface 114 of the substrate 100 in fig. 12 is by way of example only and may vary in other embodiments. In embodiments, the number of solder balls 132 may range between 50 and 1000, and more particularly 70 to 500.

As mentioned in the background section, mechanical stress is generated between the semiconductor device and a host device (e.g., PCB) to which the semiconductor device is attached, particularly at the corners of the semiconductor device. According to aspects of the present technique, the corners of the semiconductor device 150 may be secured to the host device using a high strength securing structure.

In one embodiment, solder balls 132 may be omitted from corner bond pads 110a, as shown, for example, in fig. 9. Instead of solder balls 132, corner bond pads 110 may receive support blanks 156 to reinforce the corners in step 236. Fig. 10 shows an edge view of semiconductor device 150 mounted to host device 160, which host device 160 may be, for example, a PCB. As seen in fig. 10 and in the cross-sectional view through line 11-11 in fig. 11, the support blanks 156 are larger and/or stronger than the solder balls 132 and provide greater support at the corners of the semiconductor device 150. In an embodiment, the support blank 156 may be formed of copper, but may be formed of other materials having higher tensile and/or shear strengths than the solder balls 132.

As shown in the cross-sectional view of fig. 10, in an embodiment, the blank may have a circular cross-section to provide a cylindrical blank 156. However, the support blank may have other shapes in other embodiments. Fig. 12 shows an example in which the support blank 156 has a square (or rectangular) cross section. Fig. 13 shows an example in which the support blank 156 has an "L" shaped cross-section.

As mentioned, the support blanks may be formed from a material, such as copper, that has a higher tensile and/or shear strength than the solder used for the solder balls 132. In embodiments, the support blank may additionally and/or alternatively be larger than the solder balls 132. The contact pads 110a receiving the support blank may be square between 70 μm and 150 μm. Where support blank 156 is cylindrical, support blank 156 may have a diameter that occupies all or substantially all of the length or width of contact pad 110a, such as a diameter of 40 μm to 150 μm. Contact pad 110a may be smaller or larger in other embodiments, and support blank 156 occupies, for example, 50% to 100% of the length or width of contact pad 110 a.

In an embodiment, the blank 156 is provided for structural support and not for signal transmission. In such embodiments, the contact pads 110a to which the blanks 156 are secured need not have traces 108 connected thereto. However, in other embodiments, the blank 156 and the contact pad 110a may be used for signal communication.

As mentioned, the support blank 156 provides a higher tensile strength than the solder balls 132, taking into account the material and/or size of the support blank 156. In one example, each support billet may have a tensile strength between 200 and 300MPa compared to the tensile strength of the solder ball, which is about 20-100 MPa. The tensile strength of the support blank may be higher or lower in other embodiments. A similar linear relationship exists between shear strength and tensile strength such that the support billet 156 has a higher shear strength than the solder balls 132.

The support blank 156 may be placed at the contact pads 110a at the four corners in view of the increased mechanical stress at the corners of the semiconductor device 150. However, in other embodiments, the support blank 156 may replace the solder balls 132 at more than the four corners of the end of the semiconductor device 150. Fig. 14 shows other embodiments in which a support blank is provided at more than one contact pad at each of the corners 101 of the substrate 100. In the embodiment of fig. 14, the three contact pads 110a in each corner 101 each comprise a support blank 156. In other embodiments, there may be two or more than three contact pads 110a in each corner with the support blank 156.

In an embodiment, the support blank may be initially mounted on contact pads on the host device 160 and then coupled to the bond pads 110a (not covered by the solder mask 118) when the semiconductor device 150 is mounted on the host device 160. Such an embodiment is shown in an edge view in fig. 15. The support blanks 156 may be mounted on contact pads of the host device 160 in the same process as other electronic components 162 (such as passive devices) are mounted on the host device 160. However, in alternative embodiments, support blank 156 may be initially mounted on contact pad 110a, and semiconductor device 150 including support blank 156 may be thereafter mounted on host device 160. Such an embodiment is shown in the edge view of fig. 16.

As mentioned above, the semiconductor device 150 may be formed on a panel of substrates. In embodiments where the support blank is initially secured to the host device 160, the semiconductor devices 150 may be singulated from each other after encapsulation and securing of the solder balls 132. The semiconductor device may then be secured to host device 160 and support billet 156. In embodiments where the support blank is initially secured to the semiconductor device 150, the semiconductor device 150 may be singulated from each other after encapsulation and securement of the solder balls 132 and the support blank 156. Thereafter, the semiconductor device may be fixed to the host device.

The semiconductor device 150 may be singulated by any of a variety of cutting methods including sawing, water jet cutting, laser cutting, water guided laser cutting, dry media cutting, and diamond coated wire cutting. While a straight wire cut will define a generally rectangular or square shape of the semiconductor device 150, it should be understood that the semiconductor device 150 may have shapes other than rectangular and square in other embodiments of the present technology.

In the above-described embodiments, support blanks are provided at the corners of the semiconductor device 150 to provide additional structural support and to facilitate secure attachment to the host device 160. Structural supports other than support blanks may be used in other embodiments. Fig. 17 and 18 illustrate one such alternative embodiment, in which screws are used as structural supports at the corners of the semiconductor device 150.

Fig. 17 is an exploded perspective view of the host device 160 and the semiconductor device 250 to be fixed to the host device 160. In the example shown, host device 160 may be a PCB containing electrical connector 166, with electrical connector 166 fitting within an edge connector (not shown) on a motherboard or other PCB. Host device 160 may be other PCBs or electronic devices in other embodiments. One or more of the electrical connectors 166 may be coupled by traces 168 to plated vias 170, the vias 170 helping to route electrical signals through the host device 160.

Semiconductor device 250 may be similar to semiconductor device 150 except that contact pads 110a and support blanks 156 are omitted. Additionally, screw holes 252 are formed at the corners of the semiconductor device 250, through the molding compound 130 and the substrate 100. Although four such screw holes 252 are shown, they may be more or less than four screw holes in other embodiments.

A further difference between the semiconductor device 250 and the semiconductor device 150 is that an exclusion region 254 (shown in dashed lines) may be formed in the substrate 100 and a portion of the semiconductor device 250 in the region around the screw hole 252. That is, when the conductive pattern is formed on the substrate 100 in step 202 (fig. 1), the via 106, the trace 108, or the contact pad 110 may not be formed in the exclusion zone 254 of the semiconductor device 250. Alternatively, the keep-out region 254 may include one or more vias, traces, and/or contact pads, but those vias, traces, and/or contact pads are not used in signal communication between the host device 160 and the semiconductor device 250.

In an embodiment, the screw holes 252 are formed through the molding compound 130 (fig. 9), but do not contact the semiconductor die 124 within the semiconductor device 150. In particular, the substrate 100 and the molding compound 130 can be larger than the footprint of the stack of semiconductor die 124 such that the screw holes 152 can be formed at the corners of the semiconductor device 250 while being spaced apart from the semiconductor die 124 within the semiconductor device 250.

The plated hole 170 on the host device 160 may include a threaded hole 170a, which may be threaded to receive a screw 180. In an embodiment, threaded bore 170a is not used for signal communication.

As shown in the assembled perspective view of fig. 18, screws 180 may be fitted through screw holes 252 in semiconductor device 250 and screwed into threaded through-holes 170a on host device 160 to secure semiconductor device 250 to host device 160. It should be noted that the screws 180 may be used in addition to the solder balls 132 coupled to the contact pads 172 on the host device 160.

Although shown as extending above the surface of semiconductor device 250, the head of screw 180 may be countersunk so as to be flush with the surface of semiconductor device 250. The screws 180 may be micro-screws or the like formed of copper, aluminum, steel, or other materials. The screw 180 has a higher modulus than the solder ball 132. The screws 180 may be provided instead of the corner solder balls 132 or in addition to the corner solder balls 132.

The use of support blanks and/or screws adds structural support to the semiconductor devices 150 and 250 and acts to dissipate stresses that may otherwise develop at the corners of the semiconductor devices 150 and 250. Thus, Board Level Reliability (BLR) performance is improved because the additional structural support prevents solder balls from cracking or falling off. The support blank and/or the screws also provide the advantage that an underfill (under-fill) layer, which is conventionally used to connect the semiconductor device to a host device, can be omitted. Omitting the underfill layer alleviates the need to inject epoxy under the semiconductor device 150, 250, eliminates the need to cure such layers, and eliminates the need to clean the semiconductor device 150, 250 and/or the host device after applying the underfill layer. In addition, providing structural blanks and/or screws provides better access for heat dissipation from semiconductor devices 150 and 250.

The foregoing detailed description of the technology has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present technology to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the present technology be defined by the claims appended hereto.