阅读说明：本技术 半导体封装件和方法 (Semiconductor package and method ) 是由 潘国龙 郑淑蓉 罗登元 郭鸿毅 张志鸿 郭庭豪 蔡豪益 于 2019-05-29 设计创作，主要内容包括：在实施例中,一种器件包括：第一再分布结构,包括第一介电层；管芯,粘附至第一再分布结构的第一侧；密封剂,横向密封管芯,密封剂通过第一共价键与第一介电层接合；穿过密封剂的通孔；第一导电连接器,电连接至第一再分布结构的第二侧,第一导电连接器的子集与密封剂和管芯的界面重叠。本发明实施例涉及半导体封装件和方法。(In an embodiment, a device comprises: a first redistribution structure comprising a first dielectric layer; a die attached to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant bonded to the first dielectric layer by a first covalent bond; a through hole passing through the sealant; a first electrically conductive connector electrically connected to the second side of the first redistribution structure, a subset of the first electrically conductive connectors overlapping an interface of the encapsulant and the die. Embodiments of the invention relate to semiconductor packages and methods.)

1. A semiconductor device, comprising:

a first redistribution structure comprising a first dielectric layer;

a die attached to a first side of the first redistribution structure;

an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer by a first covalent bond;

a through hole extending through the sealant; and

a first electrically conductive connector electrically connected to the second side of the first redistribution structure, a subset of the first electrically conductive connectors overlapping an interface of the encapsulant and the die.

2. The semiconductor device of claim 1, wherein the encapsulant comprises a molding compound and a nucleophile.

3. The semiconductor device of claim 2, wherein the nucleophile is ethylene glycol, 2-ethoxyethanol, or ethanolamine hydrochloride.

4. The semiconductor device of claim 2, further comprising:

an adhesive adhering the die to the first dielectric layer, the adhesive being bonded to the first dielectric layer by a second covalent bond.

5. The semiconductor device of claim 4, wherein the adhesive comprises an epoxy and a nucleophilic agent.

6. The semiconductor device of claim 1, wherein each respective conductive connector of the subset of first conductive connectors has a width, wherein at least one quarter of the width of each respective conductive connector is disposed over the die, wherein at least one quarter of the width of each respective conductive connector is disposed over the encapsulant.

7. The semiconductor device of claim 1, further comprising:

a second redistribution structure electrically connected to the via and the die, the encapsulant disposed between the first redistribution structure and the second redistribution structure; and

a second conductive connector electrically connected to the second redistribution structure, a subset of the second conductive connectors overlapping an interface of the encapsulant and the die.

8. The semiconductor device of claim 7, further comprising:

a device package connected to the first redistribution structure by the first conductive connector; and

a package substrate connected to the second redistribution structure by the second conductive connector.

9. A method of forming a semiconductor device, comprising:

forming a first dielectric layer over the first metallization pattern;

forming a via extending through the first dielectric layer, the via electrically connected to the first metallization pattern;

adhering a die to a first surface of the first dielectric layer;

bonding an encapsulant to the first surface of the first dielectric layer with a first covalent bond, the encapsulant laterally sealing the die and the via;

forming a second dielectric layer over the encapsulant; and

forming a second metallization pattern extending through the second dielectric layer, the second metallization pattern being electrically connected to the die and the via.

10. A method of forming a semiconductor device, comprising:

plating a via through the first dielectric layer with a seed layer;

etching the exposed portions of the seed layer, leaving residual metal of the seed layer after etching the seed layer;

treating a first surface of the first dielectric layer to hydroxylate the first surface and remove residual metal of the seed layer from the first surface;

adhering a die to the hydroxylated first surface; and

bonding an encapsulant to the hydroxylated first surface with a first covalent bond, the encapsulant laterally sealing the die and the via; and

a second dielectric layer is formed over the encapsulant and the die.

Technical Field

Embodiments of the invention relate to semiconductor packages and methods.

Background

The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a need for smaller and more creative packaging techniques for semiconductor dies. One example of such a packaging system is the package on package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and small footprint on Printed Circuit Boards (PCBs).

Disclosure of Invention

According to some embodiments of the present invention, there is provided a semiconductor device including: a first redistribution structure comprising a first dielectric layer; a die attached to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer by a first covalent bond; a through hole extending through the sealant; and a first electrically conductive connector electrically connected to the second side of the first redistribution structure, a subset of the first electrically conductive connectors overlapping an interface of the encapsulant and the die.

According to further embodiments of the present invention, there is also provided a method of forming a semiconductor device, including: forming a first dielectric layer over the first metallization pattern; forming a via extending through the first dielectric layer, the via electrically connected to the first metallization pattern; adhering a die to a first surface of the first dielectric layer; bonding an encapsulant to the first surface of the first dielectric layer with a first covalent bond, the encapsulant laterally sealing the die and the via; forming a second dielectric layer over the encapsulant; and forming a second metallization pattern extending through the second dielectric layer, the second metallization pattern being electrically connected to the die and the via.

According to further embodiments of the present invention, there is also provided a method of forming a semiconductor device, including: plating a via through the first dielectric layer with a seed layer; etching the exposed portions of the seed layer, leaving residual metal of the seed layer after etching the seed layer; treating a first surface of the first dielectric layer to hydroxylate the first surface and remove residual metal of the seed layer from the first surface; adhering a die to the hydroxylated first surface; and bonding an encapsulant to the hydroxylated first surface with a first covalent bond, the encapsulant laterally sealing the die and the via; and forming a second dielectric layer over the encapsulant and the die.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-12 illustrate cross-sectional views of intermediate steps during a process for forming a device package, according to some embodiments.

Fig. 13A-14 illustrate cross-sectional views of intermediate steps during a process for forming a package structure, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, prior to forming the packages on the backside redistribution structure, the topmost dielectric layer of the backside redistribution structure is cleaned using several surface treatment processes. The surface treatment process may reduce the amount of residual metal embedded in the topmost dielectric layer. The residual metal may be a metallic residue from, for example, a seed layer formed on the topmost dielectric layer. The surface treatment process may also hydroxylate the topmost dielectric layer. The subsequently formed molding compound includes a nucleophile that forms a covalent bond with the hydroxylated surface. By removing the residual metal and forming covalent bonds with the molding compound, the strength of the interface between the molding compound and the topmost dielectric layer may be increased, which may help avoid delamination of the subsequently formed component. Thus, components may be formed in areas of the package that are subject to higher mechanical strain.

Fig. 1-12 illustrate cross-sectional views of intermediate steps during a process for forming a first package 200 (see fig. 12), according to some embodiments. A first package region 100A and a second package region 100B are shown, and a first package 200 is formed in each package region. The first package 200 is also referred to as an integrated fan out (InFO) package.

In fig. 1, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer such that multiple packages may be formed on the carrier substrate 102 at the same time. The release layer 104 may be formed of a polymer-based material that may be removed with the carrier substrate 102 from overlying structures to be formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesion upon heating, such as a light-heat-conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an Ultraviolet (UV) glue that loses its adhesion when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, may be a laminated film laminated to the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be horizontal and may have a high degree of coplanarity.

In fig. 2, a backside redistribution structure 106 is formed on the release layer 104. In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108, a metallization pattern 110 (sometimes referred to as a redistribution layer or redistribution line), and a dielectric layer 112.

A dielectric layer 108 is formed on the release layer 104. The bottom surface of the dielectric layer 108 may be in contact with the top surface of the release layer 104. In some embodiments, the dielectric layer 108 is formed from a polymer, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. In other embodiments, the dielectric layer 108 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like. The dielectric layer 108 may be formed by any acceptable deposition process, such as spin-on coating, Chemical Vapor Deposition (CVD), lamination, or the like, or combinations thereof.

A metallization pattern 110 is formed on the dielectric layer 108. As an example of forming metallization pattern 110, a seed layer (not shown) is formed over dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, Physical Vapor Deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. Then, portions of the photoresist and the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form a metallization pattern 110.

A dielectric layer 112 is formed over the metallization pattern 110 and the dielectric layer 108. In some embodiments, the dielectric layer 112 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, and the like, and may be patterned using a photolithographic mask. In other embodiments, the dielectric layer 112 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 112 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 112 is then patterned to form an opening 114 that exposes a portion of the metallization pattern 110. The patterning may be by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material or by etching using, for example, anisotropic etching. In some embodiments, the dielectric layer 112 is a material having a high Coefficient of Thermal Expansion (CTE), such as polyimide. In some embodiments, the CTE of the dielectric layer 112 is in a range from about 45 ppm/deg.C to about 55 ppm/deg.C.

It should be appreciated that the backside redistribution structure 106 may include any number of dielectric layers and metallization patterns. Additional dielectric layers and metallization patterns may be formed by repeating the process used to form metallization pattern 110 and dielectric layer 112. The metallization pattern may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming the conductive material and the seed layer of the metallization pattern in the openings of the underlying dielectric layer. Thus, the conductive vias may interconnect and electrically connect the individual conductive lines.

In fig. 3A, vias 116 are formed in the openings 114 and extend away from the topmost dielectric layer (e.g., dielectric layer 112 in the illustrated embodiment) of the backside redistribution structure 106. Fig. 3B is a detailed view of region 10 and is described in conjunction with fig. 3A. As an example of forming the vias 116, a seed layer 116A is formed over the backside redistribution structure 106, e.g., on the dielectric layer 112 and on the portion of the metallization pattern 110 exposed by the opening 114. In some embodiments, seed layer 116A is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In a particular embodiment, the seed layer 116A includes a titanium layer and a copper layer over the titanium layer. Seed layer 116A may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer 116A. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive via. Patterning forms openings through the photoresist to expose seed layer 116A. Conductive material 116B is formed in the openings of the photoresist and on the exposed portions of seed layer 116A. The conductive material 116B may be formed by plating, such as electroplating or electroless plating. The conductive material 116B may include a metal such as copper, titanium, tungsten, aluminum, and the like. The photoresist and the portion of the seed layer 116A on which the conductive material 116B is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer 116A are removed, such as by using an acceptable etch process, such as by wet or dry etching. The remaining portions of seed layer 116A and conductive material 116B form vias 116.

Fig. 3C is a detailed view of region 12 of backside redistribution structure 106 after removing exposed portions of seed layer 116A (see fig. 3B). In embodiments where seed layer 116A includes a titanium layer and a copper layer over the titanium layer, seed layer 116A is formed by a PVD process, such as sputtering. The PVD process may include a pre-etch step that increases the roughness of the top surface of the dielectric layer 112 and forms pits 118 in the top surface of the dielectric layer 112. When a titanium layer is sputtered on the dielectric layer 112, some residual metal 120 (e.g., titanium) may be implanted into the dielectric layer 112. In particular, the residual metal 120 may be trapped in the pits 118 formed in the rough top surface of the dielectric layer 112.

In fig. 4A, the topmost dielectric layer (e.g., dielectric layer 112 in the illustrated embodiment) of the backside redistribution structure 106 is cleaned utilizing a first surface treatment process 122. In some embodiments, the first surface treatment process 122 includes an etching process on the top surface of the dielectric layer 112 to expose the buried residual metal 120, and also includes a hydroxylation process on the top surface of the dielectric layer 112. For example, in some embodiments, the first surface treatment process 122 is a plasma treatment process. The plasma treatment process may be performed with precursors that leave hydroxyl groups on the treated surface, such as Ar, O₂、N₂、CF₄Or a combination thereof. In such embodiments, the plasma treatment process may be performed at a temperature of about 25 ℃ to about 100 ℃ (such as about 70 ℃), and may be performed for a time of about 30 seconds to about 180 seconds (such as less than about 180 seconds). In some embodiments, the precursor may contain small amounts of H₂For example, at a concentration of about 0.1% to about 10%. Comprising H₂May help create a plasma that removes material of the dielectric layer 112. In one embodiment, the precursor of the plasma treatment process comprises O₂And H₂. Thus, the plasma treatment process may be considered as a combination of dry etching and surface hydroxylation. After the first surface treatment process 122, one of the precursors is plasma treatedSuch residues may remain on the top surface of the dielectric layer 112.

Fig. 4B is a detailed view of the region 12 of the backside redistribution structure 106 after the first surface treatment process 122. After the first surface treatment process 122, the dielectric layer 112 is thinned by a distance D₁Such that the residual metal 120 trapped in the pit 118 of the dielectric layer 112 is more exposed than before the first surface treatment process 122. In addition, after the first surface treatment process 122, a pendant hydroxyl group is formed on the top surface of the dielectric layer 112.

In fig. 5A, the topmost dielectric layer (e.g., dielectric layer 112 in the illustrated embodiment) of the backside redistribution structure 106 is cleaned with a second surface treatment process 124. In some embodiments, the second surface treatment process removes the exposed residual metal 120. In some embodiments, the second surface treatment process 124 includes an etching process, such as a wet etch. In one embodiment, the etchant of the wet etching process comprises hydrofluoric acid. The wet etch process may be selective to the material of the residual metal 120 such that the thickness of the dielectric layer 112 is not substantially reduced. In some embodiments, the second surface treatment process 124 is a plasma etch process that removes the residual metal 120. Some residue of the plasma treatment precursor may remain on the top surface of the dielectric layer 112 after the second surface treatment process 124.

Fig. 5B is a detailed view of the region 12 of the backside redistribution structure 106 after the second surface treatment process 124. After the second surface treatment process 124, the amount of residual metal 120 trapped in the recesses 118 of the dielectric layer 112 is eliminated or at least reduced.

In fig. 6, an integrated circuit die 126 is adhered to the dielectric layer 112 by an adhesive 128. The integrated circuit die 126 may be a logic die (e.g., a central processing unit, a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof. Also, in some embodiments, the integrated circuit dies 126 may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the integrated circuit dies 126 may be the same size (e.g., the same heights and/or surface areas).

Prior to adhering to dielectric layer 112, integrated circuit die 126 may be processed according to an applicable manufacturing process to form an integrated circuit in integrated circuit die 126. For example, each integrated circuit die 126 includes a semiconductor substrate 130, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, and the like may be formed in and/or on semiconductor substrate 130 and may be interconnected by interconnect structures 132 to form an integrated circuit, interconnect structures 132 being formed from metallization patterns in one or more dielectric layers on semiconductor substrate 130.

Integrated circuit die 126 also includes a pad 134, such as an aluminum pad, with external connections formed on pad 134. Pads 134 are located on the corresponding active side of so-called integrated circuit die 126. A passivation film 136 is located on the integrated circuit die 126 and on portions of the pads 134. The opening extends through the passivation film 136 to the pad 134. Die connectors 138, such as conductive posts (e.g., comprising a metal such as copper), extend through openings in the passivation film 136 and are mechanically and electrically connected to respective pads 134. The die connectors 138 may be formed by plating, for example. Die connectors 138 electrically connect the respective integrated circuits of integrated circuit die 126.

A dielectric material 140 is located on the active side of the integrated circuit die 126, such as on the passivation film 136 and the die connectors 138. The dielectric material 140 laterally encapsulates the die connectors 138, and the dielectric material 140 laterally connects with the respective integrated circuit die 126. The dielectric material 140 may be a polymer such as PBO, polyimide, BCB, etc.; nitrides such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG, and the like; or a combination thereof, and may be formed by, for example, spin coating, lamination, CVD, or the like.

The adhesive 128 is located on the back side of the integrated circuit die 126 and adheres the integrated circuit die 126 to the back side redistribution structure 106, such as to the dielectric layer 112. The adhesive 128 may be any suitable adhesive, epoxy, Die Attach Film (DAF), or the like. In one embodiment, the binder 128 includes a nucleophilic additive. The nucleophilic additive may be any nucleophile, such as ethylene glycol, 2-ethoxyethanol, ethanolamine hydrochloride, and the like. In one embodiment, the adhesive 128 is an epoxy with a nucleophile. The adhesive 128 may be applied to the backside of the integrated circuit die 126 or may be applied on the surface of the carrier substrate 102. For example, the adhesive 128 may be applied to the backside of the integrated circuit die 126 prior to singulation to separate the integrated circuit die 126.

Although one integrated circuit die 126 is shown attached in each of the first package area 100A and the second package area 100B, it should be understood that more integrated circuit dies 126 may be attached in each package area. For example, multiple integrated circuit dies 126 may be attached in each area. In addition, the size of the integrated circuit die 126 may vary. In some embodiments, the integrated circuit die 126 may be a die having a large footprint, such as a system-on-a-chip (SoC) device. In embodiments where the integrated circuit die 126 has a large footprint, the available space for the vias 116 in the package area may be limited. The use of the backside redistribution structure 106 allows for an improved interconnection arrangement when the package area has limited space available for the vias 116.

In fig. 7A, a sealant 142 is formed on each component. After formation, encapsulant 142 laterally encapsulates vias 116 and integrated circuit die 126. Encapsulant 142 may be a molding compound, epoxy, or the like. Encapsulant 142 may have a CTE similar to the CTE of dielectric layer 112, which may reduce CTE mismatch, reducing warpage. In some embodiments, the CTE of the encapsulant 142 is in a range of about 10 ppm/c to about 65 ppm/c. In one embodiment, encapsulant 142 includes a nucleophilic additive. The nucleophilic additive may be any nucleophile, such as ethylene glycol, 2-ethoxyethanol, ethanolamine hydrochloride, and the like. The nucleophilic additive may be the same nucleophilic additive in the binder 128. Encapsulant 142 may be applied by compression molding, transfer molding, etc., and may be formed over carrier substrate 102 such that vias 116 and/or integrated circuit die 126 are buried or covered. The encapsulant 142 is then cured.

Fig. 7B is a detailed view of region 14 of encapsulant 142 after encapsulant 142 is cured. The adhesive 128 may also cure. After curing, some of the nucleophilic additives of the encapsulant 142 and the adhesive 128 react with the dangling hydroxyl groups on the top surface of the dielectric layer 112 to form covalent bonds between the dielectric layer 112 and the encapsulant 142. Specifically, the oxygen atom of the nucleophilic additive cleaves the hydroxyl group, thereby forming a bond between the nucleophilic additive and the material of the dielectric layer 112. An example of such a reaction is shown in fig. 7C. Some nucleophilic additives may not form covalent bonds and may remain in encapsulant 142. As a result, the adhesion of the interface between the dielectric layer 112 and the sealant 142 may be improved. In one embodiment, the adhesion may be increased by up to 22% compared to an interface lacking covalent bonds, and the interface between the dielectric layer 112 and the sealant 142 may withstand a force of up to 14.8 gf. Adhesion at the interface between the adhesive 128 and the dielectric layer 112 may be similarly improved. Improving the adhesion at the interface between the dielectric layer 112 and the encapsulant 142/adhesive 128 may reduce the chance of interfacial delamination in subsequent processing steps. In some embodiments, the covalent bonds do not consume all of the dangling hydroxyl groups on the top surface of the dielectric layer 112, and some trace amounts of hydroxyl groups remain on or in the dielectric layer 112.

In fig. 8, a planarization process is performed on encapsulant 142 to expose vias 116 and die connectors 138. The planarization process may also polish the dielectric material 140. After the planarization process, the top surfaces of vias 116, die connectors 138, dielectric material 140, and encapsulant 142 are coplanar. The planarization process may be, for example, Chemical Mechanical Polishing (CMP), an abrasive process, or the like. In some embodiments, planarization may be omitted, for example, if the vias 116 and die connectors 138 have been exposed.

In fig. 9, a front side redistribution structure 144 is formed over the vias 116, encapsulant 142, and integrated circuit die 126. The front-side redistribution structure 144 includes dielectric layers 146,148,150, and 152; and metallization patterns 154, 156, and 158. The metallization pattern may also be referred to as a redistribution layer or a redistribution line.

The front side redistribution structure 144 is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 144. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

As an example of forming the front-side redistribution structure 144, a dielectric layer 146 is deposited over the encapsulant 142, through the vias 116 and the die connectors 138. In some embodiments, the dielectric layer 146 is formed of a photosensitive material such as PBO, polyimide, BCB, and the like and may be patterned using a photolithographic mask. The dielectric layer 146 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 146 is then patterned. The patterning forms openings (not shown) that expose portions of the vias 116 and the die connectors 138. The patterning may be by an acceptable process, such as exposing the dielectric layer 146 to light when the dielectric layer 146 is a photosensitive material or by etching using, for example, anisotropic etching. If the dielectric layer 146 is a photosensitive material, the dielectric layer 146 can be developed after exposure.

A metallization pattern 154 is then formed. Metallization pattern 154 includes conductive lines on and extending along a major surface of dielectric layer 146. Metallization pattern 154 also includes conductive vias that extend through dielectric layer 146 to physically and electrically connect to vias 116 and integrated circuit die 126. To form metallization pattern 154, a seed layer (not shown) is formed over dielectric layer 146 and in the openings extending through dielectric layer 146. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist (not shown) is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 154. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the underlying portions of the seed layer form a metallization pattern 154. Portions of the photoresist and seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

Dielectric layer 148 is deposited over dielectric layer 146 and metallization pattern 154. The dielectric layer 148 may be formed in a similar manner as the dielectric layer 146 and may be formed of the same material as the dielectric layer 146.

A metallization pattern 156 is then formed. Metallization pattern 156 includes conductive lines on and extending along a major surface of dielectric layer 148. Metallization pattern 156 also includes conductive vias extending through dielectric layer 148 to physically and electrically connect to metallization pattern 154. Metallization pattern 156 may be formed in a similar manner as metallization pattern 154 and may be formed of the same material as metallization pattern 154.

Dielectric layer 150 is deposited over dielectric layer 148 and metallization pattern 156. The dielectric layer 150 may be formed in a similar manner as the dielectric layer 146, and may be formed of the same material as the dielectric layer 146.

A metallization pattern 158 is then formed. Metallization pattern 158 includes conductive lines on and extending along a major surface of dielectric layer 150. Metallization pattern 158 also includes conductive vias extending through dielectric layer 150 to physically and electrically connect to metallization pattern 156. Metallization pattern 158 may be formed in a similar manner as metallization pattern 154 and may be formed of the same material as metallization pattern 154.

Dielectric layer 152 is deposited over dielectric layer 150 and metallization pattern 158. The dielectric layer 152 may be formed in a similar manner to the dielectric layer 146, and may be formed of the same material as the dielectric layer 146.

In fig. 10, UBM160 is formed on dielectric layer 152 and extends through dielectric layer 152. As an example of forming UBM160, dielectric layer 152 may be patterned to form openings (not shown) that expose portions of metallization pattern 158. The patterning may be by an acceptable process, such as by exposing the dielectric layer 152 to light when the dielectric layer 152 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 152 is a photosensitive material, the dielectric layer 152 can be developed after exposure. The opening for UBM160 may be wider than the openings for the conductive via portions of metallization patterns 154, 156, and 158. A seed layer (not shown) is formed over the dielectric layer 152 and in the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to UBM 160. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. Then, portions of the photoresist and the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portion of the seed layer and the conductive material form UBM 160. In embodiments where UBM160 is formed differently, more photoresist and patterning steps may be used.

In fig. 11A, a conductive connector 162 is formed on the UBM 160. The conductive connectors 162 may be Ball Grid Array (BGA) connectors, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) techniques, or the like. The conductive connector 162 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connectors 162 are formed by first forming a solder layer by conventional methods such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 162 includes a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the metal pillar. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and may be formed by a plating process.

Fig. 11B is a detailed view of the region 16 of fig. 11A showing the integrated circuit die 126 and the front side redistribution structure 144 after the conductive connectors 162 are formed. In a top view, a subset of the conductive connectors 162 are placed along an edge or corner of the integrated circuit die 126. The edges of the integrated circuit die 126 are defined by the interface of the integrated circuit die 126 and the encapsulant 142. The edges and corners of the integrated circuit die 126 are typically subjected to higher mechanical strain. For example, the conductive connectors 162 along the edges and corners of the integrated circuit die 126 may experience 10% higher strain than the conductive connectors 162 in the center of the integrated circuit die 126. UBM160 is similarly subjected to increased strain. By improving adhesion at the interface between the dielectric layer 112 and the encapsulant 142/adhesive 128 in previous steps (e.g., using surface treatment processes 122 and 124), the encapsulant 142 and integrated circuit die 126 are less likely to exert pressure on the front-side redistribution structure 144. Thus, under increased strain, the chance of the UBM160 delaminating from the front side redistribution structure 144 may be reduced. More expensive layering solutions, such as relocating the location of the integrated circuit die 126 or the conductive connectors 162, may thus be avoided. This may allow the integrated circuit dies 126 to be more evenly distributed in the resulting first package 200, allowing the encapsulant 142 to be more evenly distributed around the integrated circuit dies 126.

Conductive connectors 162 along the edges and corners of the integrated circuit die 126 may be formed to overlap the edges and corners of the integrated circuit die 126. In one embodiment, the conductive connectors 162 are disposed in edge regions near edges or corners of the integrated circuit die 126. The boundary of the edge region is disposed at a distance D from an edge or corner of the integrated circuit die 126₂To (3). In one embodiment, distance D₂May be about 25 μm. The entire edge area may be occupied by the conductive connector 162. The first side of the conductive connector 162 is disposed a distance D outside of the edge region₃And the second side of the conductive connector 162 is disposed a distance D outside the edge region₄To (3). In one embodiment, distance D₃And D₄Each may be at least one-quarter of the overall width of the respective conductive connector 162. In other words, when the conductive connectors 162 have a width, at least one-quarter of the width of each respective conductive connector 162 is disposed over the integrated circuit die 126 and at least one-quarter of the width of each respective conductive connector 126 is disposed over the encapsulant 142. Forming the conductive connectors 162 along the edges and corners of the integrated circuit die 126 may allow the number of conductive connectors 162 to be increased, thereby increasing the number of input/outputs (I/os) of the resulting first package 200.

In fig. 12, carrier substrate debonding is performed to separate (debond) the carrier substrate 102 from the backside redistribution structure 106 (e.g., the dielectric layer 108). The components remaining after de-bonding (e.g., in the first package area 100A and the second package area 100B) form the first package 200. According to some embodiments, debonding includes projecting light, such as laser or UV light, on the release layer 104 such that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 may be removed. The structure is then inverted and placed on the belt 164. In addition, an opening 166 is formed through the dielectric layer 108 to expose a portion of the metallization pattern 110. The openings 166 may be formed, for example, using laser drilling, etching, and the like.

Fig. 13A-14 illustrate cross-sectional views of intermediate steps during a process for forming a package structure 500 (see fig. 14) according to some embodiments. The package structure 500 may be referred to as a package on package (PoP) structure.

In fig. 13A, the second package 300 is attached to each of the first packages 200. The second package 300 includes a substrate 302 and one or more stacked dies 308(308A and 308B) connected to the substrate 302. Although a single stacked die 308(308A and 308B) is shown, in other embodiments, multiple stacked dies 308 (each having one or more stacked dies) may be disposed side-by-side and connected to the same surface of the substrate 302. The substrate 302 may be made of a semiconductor material such as silicon, germanium, diamond, and the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Additionally, the substrate 302 may be a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, Silicon Germanium On Insulator (SGOI), or a combination thereof. In an alternative embodiment, the substrate 302 is based on an insulating core, such as a fiberglass reinforced resin core. One exemplary core material is a fiberglass resin, such as FR 4. Alternatives to core materials include bismaleimide-triazine (BT) resins, or alternatively, other Printed Circuit Board (PCB) materials or films. A build film such as Ajinomoto Build Film (ABF) or other laminate may be used for substrate 302.

The substrate 302 may include active and passive devices (not shown). Various devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to create the structural and functional requirements of the design of the second package 300. The device may be formed using any suitable method.

The substrate 302 may also include metallization layers (not shown) and conductive vias 306. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the layers of conductive material and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc. In some embodiments, the substrate 302 is substantially free of active and passive devices.

The substrate 302 may have bond pads 303 on a first side of the substrate 302 to connect to the stacked die 308 and bond pads 304 on a second side of the substrate 302, opposite the first side of the substrate 302, to connect to the conductive connectors 314. In some embodiments, bond pads 303 and 304 are formed by forming recesses (not shown) in a dielectric layer (not shown) on the first and second sides of substrate 302. The grooves may be formed to allow the bond pads 303 and 304 to be embedded in the dielectric layer. In other embodiments, the recess is omitted, as the bond pads 303 and 304 may be formed on the dielectric layer. In some embodiments, bond pads 303 and 304 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, or the like, or combinations thereof. The conductive material of bond pads 303 and 304 may be deposited over a thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, Atomic Layer Deposition (ALD), PVD, the like, or combinations thereof. In one embodiment, the conductive material of bond pads 303 and 304 is copper, tungsten, aluminum, silver, gold, or the like, or combinations thereof.

In one embodiment, bond pads 303 and 304 are UBMs that include three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers, such as a chrome/chrome copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement may be used to form bond pads 303 and 304. Any suitable material or layer of material that may be used for bond pads 303 and 304 is fully intended to be included within the scope of the present application. In some embodiments, a conductive via 306 extends through substrate 302 and connects at least one bond pad 303 to at least one bond pad 304.

In the illustrated embodiment, the stacked die 308 are connected to the substrate 302 by wire bonds 310, but other connections, such as conductive bumps, may be used. In one embodiment, the stacked die 308 is a stacked memory die. For example, the stacked die 308 may be a memory die, such as a Low Power (LP) Double Data Rate (DDR) memory module, such as an LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory module.

The stacked die 308 and the wire bonds 310 may be encapsulated by a molding material 312. The molding material 312 may be molded over the stacked die 308 and the wire bonds 310, for example, using compression molding. In some embodiments, the molding material 312 is a molding compound, a polymer, an epoxy, a silica filler material, or the like, or combinations thereof. A curing process may be performed to cure the molding material 312; the curing process may be thermal curing, UV curing, or the like, or combinations thereof.

In some embodiments, the stacked die 308 and the wire bonds 310 are buried in the molding material 312, and after curing the molding material 312, a planarization step, such as grinding, is performed to remove excess portions of the molding material 312 and provide a substantially planar surface for the second package 300.

After forming the second package 300, the second package 300 is mechanically and electrically bonded to the first package 200 through the conductive connectors 314, the bonding pads 304 and the metallization patterns 110. In some embodiments, stacked die 308 may be connected to integrated circuit die 126 by wire bonds 310, bond pads 303 and 304, conductive vias 306, conductive connectors 314, and vias 116.

In some embodiments, a solder resist (not shown) is formed on the opposite side of the substrate 302 from the stacked die 308. Conductive connectors 314 may be disposed in openings in the solder resist to electrically and mechanically connect to conductive features (e.g., bond pads 304) in the substrate 302. Solder resist may be used to protect areas of the substrate 302 from external damage.

In some embodiments, the conductive connector 314 has an epoxy solder (not shown) formed thereon prior to reflow thereof, wherein at least some of the epoxy portion of the epoxy solder remains after the second package 300 is attached to the first package 200.

In some embodiments, an underfill 316 is formed between the first package 200 and the second package 300 and surrounds the conductive connectors 314. The underfill 316 may reduce stress and protect the joints caused by reflow of the conductive connectors 314. The underfill 316 may be formed by a capillary flow process after attaching the first package 200, or may be formed by a suitable deposition method before attaching the first package 200. In embodiments where an epoxy solder is formed, it may be used as the underfill 316.

Fig. 13B is a detailed view of the region 18 of the conductive connector 314 after the second package 300 is attached to the first package 200. In a top-down view, a subset of the conductive connectors 314 are placed along an edge or corner of the integrated circuit die 126. Similar to conductive connector 162, conductive connectors 314 placed along edges and corners of integrated circuit die 126 may experience increased strain. For example, the conductive connectors 314 along the edges and corners of the integrated circuit die 126 may experience more strain than the conductive connectors 314 at the center of the integrated circuit die 126 by more than 200%. By improving the adhesion of the interface between dielectric layer 112 and encapsulant 142/adhesive 128 in the previous steps (e.g., using surface treatment processes 122 and 124), the chance of delamination of dielectric layer 112 from integrated circuit die 126 under increased strain may be reduced. More expensive layering solutions, such as relocating the location of the integrated circuit die 126 or the conductive connectors 314, may thus be avoided. This may allow the integrated circuit dies 126 to be more evenly distributed in the resulting first package 200, allowing the encapsulant 142 to be more evenly distributed around the integrated circuit dies 126.

Conductive connectors 314 along the edges and corners of the integrated circuit die 126 may be formed to overlap the edges and corners of the integrated circuit die 126. In one embodiment, the guideElectrical connectors 314 are disposed in edge regions near edges or corners of the integrated circuit die 126. The boundary of the edge region is disposed at a distance D from an edge or corner of the integrated circuit die 126₅To (3). Distance D₅May be equal to the distance D₂. In one embodiment, distance D₅May be about 25 μm. The entire edge area may be occupied by the conductive connector 314. The first side of the conductive connector 314 is disposed a distance D outside of the edge region₆And a second side of the conductive connector 314 is disposed a distance D outside of the edge region₇To (3). In one embodiment, distance D₆And D₇May each be at least one-quarter of the overall width of the respective conductive connector 314. In other words, when the conductive connectors 314 have a width, at least one-quarter of the width of each respective conductive connector 314 is disposed over the integrated circuit die 126 and at least one-quarter of the width of each respective conductive connector 314 is disposed over the encapsulant 142.

Fig. 13C is a top view showing some of the components of the device of fig. 13A. For clarity, some components or layers are omitted from fig. 13C. The corners of integrated circuit die 126 are shown and encapsulated by encapsulant 142. Portions of the metallization pattern 110 are shown connected by conductive connectors 314. The conductive connectors 314 are connected to the pads 110A and 110B in the metallization pattern 110. Some of pads 110B are disposed in edge regions near edges or corners of integrated circuit die 126 (e.g., disposed less than distance D5 from the edges of integrated circuit die 126). In some embodiments, first shaped pads 110A are disposed over integrated circuit die 126 and second shaped pads 110B are disposed over encapsulant 142. In other embodiments, the pads all have the same shape.

In fig. 14, a singulation process is performed by sawing along the scribe area (e.g., between the first package area 100A and the second package area 100B). The sawing singulates the first package area 100A from the second package area 100B. The resulting divided first and second packages 200 and 300 are from one of the first or second package regions 100A or 100B. In some embodiments, the dicing process is performed after the second package 300 is attached to the first package 200. In other embodiments (not shown), a singulation process is performed prior to attaching the second package 300 to the first package 200, such as after the carrier substrate 102 is debonded and the opening 166 is formed.

The first package 200 is then mounted to the package substrate 400 using the conductive connectors 162. The package substrate 400 may be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. In addition, the package substrate 400 may be an SOI substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI or combinations thereof. In an alternative embodiment, the package substrate 400 is based on an insulating core, such as a fiberglass reinforced resin core. One exemplary core material is a fiberglass resin, such as FR 4. Alternatives to the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. A build-up film such as ABF or other laminate may be used for the package substrate 400.

The package substrate 400 may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices, such as transistors, capacitors, resistors, combinations of these, and the like, may be used to create the structural and functional requirements of the design of the package structure 500. Any suitable method may be used to form the device.

Package substrate 400 may also include metallization layers and vias (not shown) and bond pads 402 over the metallization layers and vias. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with vias interconnecting the conductive material layers and may be formed by any suitable process, such as deposition, damascene, dual damascene, and the like. In some embodiments, the package substrate 400 is substantially free of active and passive devices.

In some embodiments, the conductive connectors 162 are reflowed to attach the first package 200 to the bond pads 402. The conductive connectors 162 electrically and/or physically connect the package substrate 400 (including the metallization layers in the package substrate 400) to the first package 200. In some embodiments, a passive device (e.g., a Surface Mount Device (SMD), not shown) may be attached to the first package 200 (e.g., bonded to the bond pads 402) prior to mounting on the package substrate 400. In such embodiments, the passive devices may be bonded to the same surface of the first package 200 as the conductive connectors 162.

The conductive connectors 162 have an epoxy solder (not shown) formed thereon prior to reflow thereof, wherein at least some of the epoxy portion of the epoxy solder remains after the first package 200 is attached to the package substrate 400. These remaining epoxy portions may be used as an underfill to reduce stress and protect the joints created by the reflowed conductive connectors 162. In some embodiments, an underfill (not shown) may be formed between the first package 200 and the package substrate 400 and around the conductive connectors 162. The underfill may be formed by a capillary flow process after attaching the first package 200, or may be formed by a suitable deposition method before attaching the first package 200.