阅读说明：本技术 主控元件及电路基板 (Master control element and circuit board ) 是由 赖照民 王鸿玮 王丙嘉 于 2018-06-20 设计创作，主要内容包括：本发明公开一种主控元件以及电路基板。主控元件可配合电路基板操作,且包括一设置在所述主控元件底部的锡球阵列。锡球阵列包括：多个电源锡球以及多个接地锡球。多个电源锡球与多个接地锡球共同位于一锡球设置区内,并且多个接地锡球的至少一部分与多个电源锡球的至少一部分相互交错设置。电路基板具有对应于主控元件的锡球阵列的焊盘阵列,以使主控元件可被组装于电路基板上。(The invention discloses a main control element and a circuit substrate. The main control element can be operated in cooperation with the circuit substrate and comprises a solder ball array arranged at the bottom of the main control element. The solder ball array includes: a plurality of power solder balls and a plurality of ground solder balls. The plurality of power solder balls and the plurality of grounding solder balls are positioned in a solder ball arrangement area together, and at least one part of the plurality of grounding solder balls and at least one part of the plurality of power solder balls are arranged in a staggered manner. The circuit substrate is provided with a pad array corresponding to the solder ball array of the main control element, so that the main control element can be assembled on the circuit substrate.)

1. A main control element, comprising a solder ball array disposed at a bottom of the main control element, the solder ball array comprising: the power supply solder balls and the grounding solder balls are positioned in a solder ball arrangement area, and at least one part of the grounding solder balls and at least one part of the power supply solder balls are arranged in a staggered manner.

2. The main control device as claimed in claim 1, wherein the array of solder balls comprises at least a 2 x 2 array of solder balls, and the 2 x 2 array of solder balls comprises two of the ground solder balls arranged along one diagonal and two of the power solder balls arranged along the other diagonal.

3. The main control device as claimed in claim 1, wherein the number of the grounding solder balls is the same as the number of the power solder balls, and a plurality of the grounding solder balls and a plurality of the power solder balls are arranged in a plurality of rows and a plurality of columns, the plurality of the grounding solder balls and the plurality of the power solder balls in each row or each column are alternately arranged, and one power solder ball is arranged between every two adjacent grounding solder balls.

4. A circuit substrate, comprising:

the laminated board body is provided with a first surface and a second surface opposite to the first surface, wherein the laminated board body comprises at least one grounding layer and a power supply layer electrically insulated from the grounding layer;

the pad array is arranged on the first surface and comprises a plurality of power pads electrically connected to the power layer and a plurality of ground pads electrically connected to the ground layer, the plurality of power pads and the plurality of ground pads are jointly positioned in a first preset area of the first surface, and at least a part of the ground pads and at least a part of the power pads are arranged in a staggered mode.

5. The circuit substrate of claim 4, wherein the pad array comprises at least a 2 x 2 pad array, the 2 x 2 pad array comprising two of the ground pads arranged along one of the diagonals and two of the power pads arranged along the other diagonal.

6. The circuit substrate of claim 4, further comprising:

and the conductive column array comprises a plurality of grounding conductive columns and a plurality of power conductive columns which penetrate through the laminated board body, wherein a plurality of power pads are electrically connected to the power layer through the plurality of power conductive columns, a plurality of grounding pads are electrically connected to the grounding layer through the plurality of grounding conductive columns, and the plurality of grounding conductive columns and the plurality of power conductive columns are arranged in a mutually staggered manner.

7. The circuit substrate according to claim 6, wherein two of the ground conductive pillars and two of the power conductive pillars are arranged in a 2 × 2 conductive pillar array, two of the ground conductive pillars in the 2 × 2 conductive pillar array are arranged along one diagonal line of the 2 × 2 conductive pillar array, and two of the power conductive pillars are arranged along another diagonal line of the 2 × 2 conductive pillar array.

8. The circuit substrate of claim 6, further comprising:

and a plurality of connection pad groups disposed on the second surface, wherein each connection pad group includes a positive connection pad and a negative connection pad, the positive connection pad is adjacent to the corresponding power conductive pillar, and the negative connection pad is adjacent to the corresponding ground conductive pillar.

9. The circuit substrate according to claim 8, wherein two of the ground conductive pillars and two of the power conductive pillars are configured as a 2 × 2 conductive pillar array, two of the ground conductive pillars in the 2 × 2 conductive pillar array are arranged along one diagonal line of the 2 × 2 conductive pillar array, two of the power conductive pillars are arranged along another diagonal line of the 2 × 2 conductive pillar array, two of the connection pad groups are respectively disposed on two opposite sides of the 2 × 2 conductive pillar array, wherein the positive connection pad and the negative connection pad of one of the connection pad groups are configured oppositely, and the positive connection pad and the negative connection pad of the other of the capacitance connection pad groups are configured oppositely.

10. The circuit substrate of claim 6, further comprising:

a plurality of front-side grounding circuits disposed on the first surface, each front-side grounding circuit being electrically connected to a corresponding plurality of grounding pads and a corresponding plurality of grounding conductive pillars;

a plurality of positive power supply lines, it set up in the first surface, each positive power supply line electric connection is in a plurality of that correspond the power pad and a plurality of that correspond the power is led electrical pillar, wherein, many positive power supply line and many the ground connection circuit of openly extends along the equidirectional extension.

Technical Field

The present invention relates to a main control device and a circuit board, and more particularly, to a main control device with a solder ball array and a circuit board.

Background

Ball grid array packages are widely used today to package integrated circuit chips (IC chips) to form integrated circuit components. Ball grid array packaging is to make a solder ball array on the bottom of the packaging substrate of the integrated circuit element, and a plurality of solder balls in the solder ball array can be used as external contacts to electrically connect the integrated circuit chip to the circuit board. In addition, the integrated circuit chip can transmit signals between the circuit board and a plurality of solder balls in the solder ball array.

Currently, in designing a circuit board and a ball grid array, a plurality of ground solder balls are electrically connected to a ground plane in the circuit board through a plurality of ground vias (ground vias), and a plurality of power solder balls are electrically connected to a power plane in the circuit board through a plurality of power vias (power vias).

In order to reduce the direct current drop (IR drop) caused by parasitic resistance in the circuit board, the number of the ground solder balls and the number of the power solder balls are increased as much as possible to increase the current transmission path. Accordingly, the number of ground vias (grounded vias) and power vias (power vias) is increased, thereby increasing the density of ground vias and the density of power vias. In addition, the conventional grounding solder balls and the conventional power solder balls are usually disposed in different areas, so as to simplify the inner circuit fabrication of the circuit board.

However, parasitic inductance is generated between the ground vias (ground vias) and the power vias (power vias) in the high-density distribution. Due to the transient variation of the current and the parasitic inductance generated when the integrated circuit device operates, Synchronous Switching Noise (SSN) is generated in the circuit, which results in a reduction of the power supply voltage supplied to the integrated circuit device.

As the performance requirements of integrated circuit devices increase, the integrated circuit devices need to be switched from a low power state to a high power state in a few nanoseconds. Therefore, the current supplied to the integrated circuit element needs to be increased sharply in a very short time. The increased transient variation of the current also makes the negative effect of the parasitic inductance more significant. That is, the increase in current transients and the presence of parasitic resistances cause the voltage drop of the supply voltage to increase. This can affect the integrity of the power supply (power integration), resulting in instability in the use of the electronic device.

Disclosure of Invention

The invention aims to solve the technical problem of reducing the parasitic inductance generated in the circuit of the circuit substrate so as to solve the voltage drop caused by overlarge transient change of current.

In order to solve the above technical problem, one of the technical solutions of the present invention is to provide a main control element, where the main control element includes a solder ball array disposed at a bottom of the main control element. The solder ball array includes: a plurality of power solder balls and a plurality of ground solder balls. The plurality of power solder balls and the plurality of grounding solder balls are positioned in a solder ball arrangement area together, and at least one part of the plurality of grounding solder balls and at least one part of the plurality of power solder balls are arranged in a staggered manner.

In one embodiment, the array of solder balls comprises a 2 × 2 array of solder balls, wherein the 2 × 2 array of solder balls comprises two ground solder balls arranged along one diagonal and two power solder balls arranged along the other diagonal.

In an embodiment, the number of the grounding solder balls is the same as the number of the power solder balls, and the plurality of grounding solder balls and the plurality of power solder balls are arranged in a plurality of rows and a plurality of columns, the plurality of grounding solder balls and the plurality of power solder balls in each row or each column are alternately arranged, and one power solder ball is arranged between every two adjacent grounding solder balls.

Another technical solution adopted by the present invention is to provide a circuit board. The circuit substrate comprises a laminated board body and a pad array. The laminated plate body is provided with a first surface and a second surface opposite to the first surface. The laminated board body comprises at least one grounding layer and a power layer electrically insulated from the grounding layer. The pad array is disposed on the first surface and includes a plurality of power pads electrically connected to the power layer and a plurality of ground pads electrically connected to the ground layer. The plurality of power solder balls and the plurality of grounding solder balls are positioned in a first preset area of the first surface together, and at least one part of the grounding bonding pads and at least one part of the power bonding pads are arranged in a staggered mode.

In one embodiment, the pad array includes at least a 2 × 2 pad array, and the 2 × 2 pad array includes two ground pads arranged along one diagonal line and two power pads arranged along the other diagonal line.

In an embodiment, the electronic device further includes a conductive pillar array including a plurality of ground conductive pillars and a plurality of power conductive pillars penetrating through the laminated board body, wherein the plurality of power pads are electrically connected to the power layer through the plurality of power conductive pillars, the plurality of ground pads are electrically connected to the ground layer through the plurality of ground conductive pillars, and the plurality of ground conductive pillars and the plurality of power conductive pillars are arranged in a staggered manner.

In an embodiment, two of the ground conductive pillars and two of the power conductive pillars are configured as a 2 × 2 conductive pillar array, two of the ground conductive pillars in the 2 × 2 conductive pillar array are arranged along one diagonal of the 2 × 2 conductive pillar array, and two of the power conductive pillars are arranged along another diagonal of the 2 × 2 conductive pillar array.

In an embodiment, the circuit substrate further includes a plurality of connection pad groups disposed on the second surface, wherein each connection pad group includes a positive connection pad and a negative connection pad, the positive connection pad is adjacent to the corresponding power conductive pillar, and the negative connection pad is adjacent to the corresponding ground conductive pillar.

In an embodiment, two of the ground conductive pillars and two of the power conductive pillars are configured as a 2 × 2 conductive pillar array, two of the ground conductive pillars in the 2 × 2 conductive pillar array are arranged along one diagonal line of the 2 × 2 conductive pillar array, two of the power conductive pillars are arranged along another diagonal line of the 2 × 2 conductive pillar array, two of the connection pad groups are respectively disposed on two opposite sides of the 2 × 2 conductive pillar array, the positive connection pad and the negative connection pad of one of the connection pad groups, and the positive connection pad and the negative connection pad of the other of the capacitance connection pad groups are configured oppositely.

In one embodiment, the circuit substrate further comprises: a plurality of front-side grounding circuits disposed on the first surface, each front-side grounding circuit being electrically connected to a corresponding plurality of grounding pads and a corresponding plurality of grounding conductive pillars;

a plurality of positive power supply lines, it set up in the first surface, each positive power supply line electric connection is in a plurality of that correspond the power pad and a plurality of that correspond the power is led electrical pillar, wherein, many positive power supply line and many the ground connection circuit of openly extends along the equidirectional extension.

The main control element and the circuit substrate provided by the technical scheme of the invention have the beneficial effects that the parasitic inductance generated by the circuit substrate can be reduced by arranging at least one part of the power supply bonding pads and at least one part of the grounding bonding pads in a staggered manner, so that the problem of overlarge voltage change caused by overlarge transient change of current when the main control element is operated at high frequency is avoided.

For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.

Drawings

Fig. 1 is a partial bottom view of a main control element according to an embodiment of the invention.

Fig. 2 is a partial bottom view of a main control element according to another embodiment of the invention.

Fig. 3 is a partial bottom view of a main control element according to another embodiment of the present invention.

Fig. 4 is a partial top view of a circuit substrate according to an embodiment of the invention.

Fig. 5 is a partial bottom view of the circuit substrate of fig. 4.

Fig. 6 is a partial cross-sectional view of the circuit substrate of fig. 4 along line VI-VI.

Fig. 7 is a partial cross-sectional view of the circuit substrate of fig. 4 along line VII-VII.

Fig. 8 is a partial cross-sectional view of the circuit substrate of fig. 4 along line VIII-VIII.

Fig. 9 is a schematic top view illustrating a power plane according to an embodiment of the invention.

Fig. 10 is a schematic top view of a ground plane according to an embodiment of the invention.

Fig. 11 shows a schematic partial cross-sectional view of the circuit substrate of fig. 5 along the line XI-XI.

The reference numbers are as follows:

master control element 1

Solder ball array 10

Power solder ball P1

Grounding solder ball G1

Solder ball setting region 10R

2 x 2 tin ball array 100, 101, 102

Tin-free ball region E1

Circuit board 2

Laminated board body 20

First surface 20a

Second surface 20b

Ground layer 21

Second insulating hole 210

Power plane 22

First insulating hole 220

Pad array 200

Power pad P2

Ground pad G2

First predetermined region 200R

Conductive column array 200'

Grounded conductive pillar C21

Power conductive post C22

2 x 2 conductive pillar array 201

Second predetermined region 200' R

Line layer 23

Front side ground line 231

Front power supply line 232

Connection pad group 24

Positive electrode connection pad 24a

Negative connection pad 24b

Bottom surface circuit layer 25

Bottom ground line 251

Bottom surface power supply line 252

First direction D1

Second direction D2

Detailed Description

Please refer to fig. 1. Fig. 1 is a partial bottom view of a main control element according to an embodiment of the invention. The main control element 1 is used to be assembled on another circuit substrate to form an electronic device. In addition, the main control element 1 can operate in cooperation with the circuit substrate.

The main control element 1 may be a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), which may be a package structure of a system on chip (SoC). In addition, the main control element 1 of the present embodiment may be adapted to operate at high frequencies.

The main device 1 includes a solder ball array 10 disposed on the bottom of the main device 1, and the solder ball array 10 includes a plurality of power solder balls P1 and a plurality of ground solder balls G1. It should be noted that, in the embodiment of the present invention, the arrangement positions of the plurality of power solder balls P1 and the plurality of ground solder balls G1 in the solder ball array 10 are improved, so as to reduce the parasitic inductance during the operation of the electronic device.

It should be noted that fig. 1 is only a simplified schematic diagram of the solder ball array 10 for clarity of the concept of the present invention, and is not an actual solder ball array 10. In addition, the solder ball array 10 of the main control device 1 also includes other signal solder balls, but for convenience of description, other signal solder balls are not shown in fig. 1.

As shown in fig. 1, a plurality of grounding solder balls G1 and a plurality of power solder balls P1 of the solder ball array 10 of the present embodiment are commonly disposed in a solder ball disposing region 10R, and at least a portion of the plurality of grounding solder balls G1 and at least a portion of the plurality of power solder balls P1 are disposed in a staggered manner.

Accordingly, in the embodiment of the invention, the solder ball array 10 at least includes a 2 × 2 solder ball array 10, and the 2 × 2 solder ball array 10 includes two ground solder balls G1 arranged along one diagonal and two power solder balls P1 arranged along the other diagonal.

In the embodiment, the number of the grounding solder balls G1 is the same as the number of the power solder balls P1, and the plurality of grounding solder balls G1 and the plurality of power solder balls P1 are arranged in a plurality of rows along the first direction D1 and in a plurality of columns along the second direction D2. In addition, a plurality of grounding solder balls G1 and a plurality of power solder balls P1 in each row or each column are alternately arranged. Furthermore, in the same row (or the same column), a power solder ball P1 is disposed between every two adjacent ground solder balls G1. Therefore, any two power solder balls P1 in the same row or column are not adjacent.

Accordingly, in the present embodiment, there is at least one grounding solder ball G1 around each power solder ball P1. In contrast, there is at least one power solder ball P1 around each ground solder ball G1. That is, in the present embodiment, all the power solder balls P1 and all the ground solder balls G1 are disposed alternately.

In another embodiment, the number of the plurality of power solder balls P1 and the number of the ground solder balls G1 in the solder ball placement region 10R are not necessarily the same. That is, the number of the grounding solder balls G1 may be greater than or less than the number of the power solder balls P1.

Specifically, when the number of the grounding solder balls G1 is greater than the number of the power solder balls P1, only a portion of the grounding solder balls G1 may be interlaced with the power solder balls P1. When the number of the grounding solder balls G1 is smaller than the number of the power solder balls P1, only a portion of the plurality of power solder balls P1 may be interlaced with the plurality of grounding solder balls G1.

Referring to fig. 2, a schematic bottom view of a main control element according to another embodiment of the invention is shown. The same elements in this embodiment and the previous embodiment have the same reference numerals, and the description of the same parts is omitted.

Unlike the embodiment of fig. 1, in the present embodiment, the number of the grounding solder balls G1 is greater than the number of the power solder balls P1. Therefore, only a part of the plurality of ground solder balls G1 are interleaved with the plurality of power solder balls P1.

As shown in fig. 2, the solder ball array 10 of the present embodiment further includes another 2 × 2 solder ball array 101, and the 2 × 2 solder ball array 101 includes two adjacent grounding solder balls G1. Furthermore, in the present embodiment, the 2 × 2 solder ball array 101 includes four adjacent ground solder balls G1. That is, the four grounding solder balls G1 in the 2 × 2 solder ball array 101 are not staggered with the power solder balls P1.

Nevertheless, the other grounding solder balls G1 not belonging to the 2 × 2 solder ball array 101 are still interlaced with the plurality of power solder balls P1, so that the scope of "at least a portion of the plurality of power solder balls and at least a portion of the plurality of grounding solder balls are interlaced" is still met.

In addition, the four grounding solder balls G1 in the 2 × 2 solder ball array 101 can be replaced by two adjacent grounding solder balls G1 and two adjacent power solder balls P1, or by four power solder balls P1 without departing from the spirit of the present invention.

Referring to fig. 3, a schematic bottom view of a main control element according to another embodiment of the invention is shown. In the present embodiment, the number of the grounding solder balls G1 is the same as the number of the power solder balls P1, but the solder ball array 10 further includes at least one solder ball free region E1. The solder ball-free region E1 indicates that no solder balls are disposed at this position.

That is, in the present embodiment, the plurality of ground solder balls G1, the plurality of power solder balls P1, and the at least one solder ball free area E1 are arranged in a plurality of rows and a plurality of columns, and the solder ball free area E1 is located in one row (or one column). In other words, in the present embodiment, the solder ball array 10 may further include another 2 × 2 solder ball array 102, and the 2 × 2 solder ball array 102 at least includes a solder ball free region E1. In the present embodiment, the 2 × 2 solder ball array 102 includes two solder free areas E1, a power solder ball P1, and a ground solder ball G1.

However, the number and the position of the tin-free ball regions E1 are not limited, and may be changed according to actual needs. In addition, the power solder ball P1 and the ground solder ball G1 in the 2 × 2 solder ball array 102 can be replaced by two power solder balls P1 or two ground solder balls G1.

Based on the embodiments shown in fig. 1 to fig. 3, it is only necessary that a portion of the power solder balls P1 and a portion of the ground solder balls G1 in the solder ball array 10 are interlaced with each other, so as to meet the spirit of the embodiments of the present invention.

Please refer to fig. 4, fig. 5 and fig. 6. As shown in fig. 6, the circuit substrate 2 of the embodiment of the invention includes a laminated board body 20, and the laminated board body 20 has a first surface 20a and a second surface 20b opposite to the first surface 20 a. In addition, the laminated board 20 includes a ground layer 21 and a power layer 22.

It should be noted that, in the cross-sectional views of all the circuit substrates 2 of the present invention, other layers of the laminated board body 20 are not shown, and only the ground layer 21 and the power layer 22 are shown. In practice, the laminated board 20 is formed by laminating a plurality of insulating layers and a plurality of conductive layers, wherein one conductive layer can be used as the ground layer 21, and the other conductive layer can be used as the power layer 22. The ground layer 21 and the power layer 22 may be electrically insulated from each other by an insulating layer.

As shown in fig. 4, the circuit substrate 2 further includes a pad array 200 disposed corresponding to the solder ball array 10 of the main control element 1. In the present embodiment, the main control element 1 may be assembled on the first surface 20a of the laminated plate body 20. Thus, the pad array 200 is located on the first surface 20a of the laminated board body 20.

In the present embodiment, the pad array 200 includes a plurality of power pads P2 and a plurality of ground pads G2. The power pads P2 correspond to the power solder balls P1 in the solder ball array 10 of fig. 1, respectively, and the ground pads G2 correspond to the ground solder balls G1 in fig. 1, respectively.

However, in another embodiment, the power pads P2 and the ground pads G2 in the pad array 200 may also correspond to the solder ball array shown in fig. 2. In yet another embodiment, the pad array 200 may also include a vacancy configured region, and the position of the vacancy configured region corresponds to the tin-free ball region E1 depicted in fig. 3.

With reference to fig. 4, in the present embodiment, the plurality of ground pads G2 and the plurality of power pads P2 are commonly located in the first predetermined region 200R of the first surface 20a, and at least a portion of the ground pads G2 and at least a portion of the power pads P2 are disposed alternately.

Similar to the solder ball array 10 of the main device 1 in fig. 1, the pad array 200 at least includes a 2 × 2 pad array (not numbered), and the 2 × 2 pad array includes two ground pads G2 and two power pads P2. In addition, two ground pads G2 are arranged along one diagonal of the 2 × 2 pad array, and two power pads P2 are arranged along the other diagonal of the 2 × 2 pad array. Therefore, in the 2 × 2 pad array, the power pad P2 and the ground pad G2 may be adjacently disposed.

Further, in the present embodiment, the plurality of power pads P2 and the plurality of ground pads G2 are arranged in a plurality of rows and a plurality of columns in common. The plurality of power pads P2 in each row or each column are alternately disposed with the plurality of ground pads G2. In the same row (or the same column), one power supply pad P2 is provided between every two adjacent ground pads G2.

In addition, referring to fig. 4 and fig. 5, the circuit substrate 2 of the embodiment of the invention further includes a conductive pillar array 200'. The conductive pillar array 200' includes a plurality of ground conductive pillars C21 and a plurality of power conductive pillars C22, wherein the ground conductive pillars C21 and the power conductive pillars C22 penetrate through the laminated board 20. The power pads P2 are electrically connected to the corresponding power conductive pillars C22, and the ground pads G2 are electrically connected to the corresponding ground conductive pillars C21.

As shown in fig. 4, in the present embodiment, since the power pads P2 and the ground pads G2 are disposed in a staggered manner, in order to match the positions of the power pads P2 and the ground pads G2, the power conductive pillars C22 and the ground conductive pillars C21 are also disposed in a staggered manner.

Specifically, referring to fig. 4, one of the power conductive pillars C22 or one of the ground conductive pillars C21 is located in a central region of the 2 × 2 pad array. In other words, one of the power conductive pillars C22 or one of the ground conductive pillars C21 is disposed between the 2 × 2 pad array formed by the two power pads P2 and the two ground pads G2.

Referring to fig. 5, the plurality of ground conductive pillars C21 and the plurality of power conductive pillars C22 are commonly disposed in the second predetermined region 200' R of the second surface 20 b. The second predetermined region 200' R and the first predetermined region 200R at least partially overlap in the thickness direction of the laminated plate body 20.

In the conductive pillar array 200', at least two ground conductive pillars C21 and two power conductive pillars C22 may be arranged to form a 2 × 2 conductive pillar array 201. In the 2 × 2 conductive pillar array 201, two ground conductive pillars C21 are arranged along one diagonal of the 2 × 2 conductive pillar array 201, and two power conductive pillars C22 are arranged along the other diagonal of the 2 × 2 conductive pillar array 201.

Please refer to fig. 4, 7 to 8. As shown in fig. 4 and 7, the circuit substrate 2 further includes a circuit layer 23, and the circuit layer 23 includes a plurality of front-side ground lines 231 and a plurality of front-side power lines 232.

A plurality of front ground lines 231 are disposed on the first surface 20 a. Each front ground line 231 is electrically connected to the corresponding ground pads G2 and the corresponding ground conductive pillars C21. In other words, the plurality of ground pads G2 are electrically connected to the ground layer 21 through the corresponding front ground lines 231 and the corresponding ground conductive pillars C21.

As shown in fig. 4 and 8, a plurality of front power traces 232 are disposed on the first surface 20 a. Each front power line 232 is electrically connected to the corresponding power pads P2 and the corresponding power conductive pillars C22. In other words, the power pads P2 are electrically connected to the power layer 22 through the corresponding front power traces 232 and the corresponding power conductive pillars C22.

Referring to fig. 4 again, based on the arrangement of the power pad P2, the ground pad G2, the power conductive pillar C22, and the ground conductive pillar C21, in the present embodiment, the plurality of front ground lines 231 and the plurality of front power lines 232 extend along the same direction. Specifically, the plurality of front ground lines 231 and the plurality of front power lines 232 are disposed on the first surface 20a in an inclined manner with respect to the row direction (i.e., the first direction D1) of the pad array 200.

It should be noted that, since the plurality of ground pads G2 and the plurality of power pads P2 are disposed in an interlaced manner, and the plurality of ground conductive pillars C21 and the plurality of power conductive pillars C22 are disposed in an interlaced manner, the area of a current loop (current loop) formed by a corresponding group of power pads P2, power conductive pillars C22, ground pads G2, and ground conductive pillars C21 can be reduced, so that parasitic inductance is greatly reduced.

Due to the reduction of the parasitic inductance, the voltage variation caused by the parasitic inductance and the excessive transient variation of the current can be further reduced, thereby improving the power integration.

In addition, please refer to fig. 7 and fig. 9, wherein fig. 9 shows a top view of a power layer according to an embodiment of the invention. As shown in fig. 7, a plurality of ground conductive pillars C21 penetrate through the laminated board 20. Therefore, in order to electrically insulate the power layer 22 from the plurality of ground conductive pillars C21, the power layer 22 further includes a plurality of first insulating holes 220, and the plurality of first insulating holes 220 are disposed corresponding to the plurality of ground conductive pillars C21, respectively. That is, each of the ground conductive pillars C21 can be electrically insulated from the power layer 22 through the corresponding first insulating hole 220.

As shown in fig. 9, the first pattern formed by the first insulating holes 220 on the surface of the power layer 22 is the same as the grounding pattern formed by the grounding conductive pillars C21 on the first surface 20 a.

Similarly, please refer to fig. 8 and fig. 10, wherein fig. 10 is a schematic top view of a ground layer according to an embodiment of the invention. As shown in fig. 8, in order to electrically insulate the ground layer 21 and the plurality of power conductive pillars C22 penetrating through the laminated board body 20, the ground layer 21 further includes a plurality of second insulation holes 210. The second insulating holes 210 are respectively disposed at positions corresponding to the power conductive pillars C22, so that each power conductive pillar C22 can be electrically insulated from the ground layer 21 by the corresponding second insulating hole 210.

As shown in fig. 10, the second pattern formed by the plurality of second insulating holes 210 on the surface of the power layer 22 is the same as the power pattern formed by the plurality of power conductive pillars C22 on the second surface 20 b.

It should be noted that although the insulation holes (the first insulation hole 220 and the second insulation hole 210) formed in both the power plane 22 and the ground plane 21 may increase the parasitic resistance in the circuit substrate 2, the increase is small, and thus the operation of the electronic device as a whole is not affected.

Next, please refer to fig. 5 and fig. 11 together. As shown in fig. 5, the circuit substrate 2 of the present embodiment further includes a plurality of connection pad sets 24, and the connection pad sets 24 are disposed on the second surface 20b of the laminated board body 20. In the present embodiment, each connection pad set 24 includes a positive connection pad 24a and a negative connection pad 24b for electrically connecting to a passive device. The passive element is, for example, a multilayer ceramic capacitor element.

In the present embodiment, each positive connection pad 24a is disposed adjacent to the corresponding power conductive pillar C22, and the negative connection pad 24b is disposed adjacent to the corresponding ground conductive pillar C21. In a preferred embodiment, two connection pad sets 24 are respectively disposed on two opposite sides of one of the 2 × 2 conductive pillar arrays 201, wherein the positive connection pad 24a and the negative connection pad 24b of one connection pad set 24 are disposed opposite to the positive connection pad 24a and the negative connection pad 24b of the other connection pad set 24.

Thus, all the power conductive pillars C22 and all the ground conductive pillars C21 can be arranged in a staggered manner, so that the area covered by the current loop can be reduced, and the parasitic inductance can be further reduced.

As shown in fig. 5 and 11, the circuit board 2 further includes a bottom surface wiring layer 25 disposed on the second surface 20b, and including a plurality of bottom surface ground wirings 251 and a plurality of bottom surface power supply wirings 252. Each positive connection pad 24a may be electrically connected to the corresponding power conductive pillar C22 through the corresponding bottom power circuit 252. Each negative connection pad 24b can be electrically connected to the corresponding ground conductive pillar C21 through the corresponding bottom ground line 251.

Since the positive connection pads 24a and the negative connection pads 24b of the connection pad group 24 occupy the positions where the ground conductive pillars C21 and the power conductive pillars C22 can be originally arranged, the number of the connection pad group 24 can be increased or decreased according to the number of the passive elements to be arranged.

In addition, since the ground conductive pillars C21 and the power conductive pillars C22 in the embodiment of the present invention are arranged in a staggered manner, a plurality of connection pad groups 24 can be dispersedly arranged between the power conductive pillars C22 and the ground conductive pillars C21. When the passive device is assembled on the circuit substrate 2, the passive device can be distributed in the conductive pillar array 200', and can be electrically connected to more ground conductive pillars C21 and power conductive pillars C22, so as to effectively reduce the impedance of the main control device 1 during high frequency operation.

In summary, the main control element and the circuit substrate provided in the technical solution of the present invention have the beneficial effects that parasitic inductance generated by the circuit substrate can be reduced by "staggering at least a portion of the plurality of power solder balls and at least a portion of the plurality of ground solder balls" and "staggering at least a portion of the plurality of power conductive pillars and at least a portion of the plurality of ground conductive pillars", so as to avoid the problem of excessive voltage variation caused by excessive transient variation of current when the main control element is operated at high frequency.

The disclosure is only a preferred embodiment of the invention, and is not intended to limit the scope of the invention, so that all equivalent technical changes made by using the contents of the specification and the drawings are included in the scope of the invention.