阅读说明：本技术 阵列基板及其制造方法、阵列基板的图案偏移的检测方法 (Array substrate, manufacturing method thereof and detection method of pattern deviation of array substrate ) 是由 前昌弘 李广圣 于 2019-10-22 设计创作，主要内容包括：本发明提供一种阵列基板及其制造方法、阵列基板的图案偏移的检测方法。阵列基板包括至少一个设置在衬底基板上的薄膜晶体管和偏移监控图形,薄膜晶体管包括第一半导体图形、第一保护图形、同层设置的源极和漏极；偏移监控图形包括：与第一半导体图形同层设置的第二半导体图形、与第一保护图形同层设置的第二保护图形、以及与源极和漏极同层设置的像素漏极,像素漏极和漏极电连接,第二保护图形覆盖在第二半导体图形之上,且在第二保护图形上设有第二过孔,像素漏极通过第二过孔与第二半导体图形接触；像素漏极的外轮廓覆盖第二过孔的外轮廓。本发明能够减少检测不准确的情况的发生。(The invention provides an array substrate, a manufacturing method thereof and a detection method of pattern deviation of the array substrate. The array substrate comprises at least one thin film transistor and an offset monitoring pattern, wherein the thin film transistor is arranged on the substrate and comprises a first semiconductor pattern, a first protection pattern, a source electrode and a drain electrode which are arranged on the same layer; the offset monitoring pattern includes: the second semiconductor pattern is arranged on the same layer as the first semiconductor pattern, the second protection pattern is arranged on the same layer as the first protection pattern, and the pixel drain electrode is arranged on the same layer as the source electrode and the drain electrode; the outer contour of the pixel drain covers the outer contour of the second through hole. The invention can reduce the occurrence of inaccurate detection.)

1. An array substrate, comprising at least one thin film transistor and an offset monitoring pattern disposed on a substrate,

the thin film transistor comprises a first semiconductor pattern, a first protection pattern, and a source electrode and a drain electrode which are arranged on the same layer, wherein the first protection pattern covers the first semiconductor pattern, a first through hole is formed in the first protection pattern, and the source electrode and the drain electrode are respectively contacted with the first semiconductor pattern through the first through hole;

the offset monitoring pattern includes: the second semiconductor pattern is arranged on the same layer as the first semiconductor pattern, the second protection pattern is arranged on the same layer as the first protection pattern, and the pixel drain electrode is arranged on the same layer as the source electrode and the drain electrode; and the outer contour of the pixel drain covers the outer contour of the second through hole.

2. The array substrate of claim 1, wherein a spacing between an outer contour of the second via and an outer contour of the pixel drain is greater than a spacing between an outer contour of the first via and an outer contour of the drain or the source.

3. The array substrate of claim 1, wherein the pixel drain is located in a pixel region of the array substrate.

4. The array substrate of claim 3, further comprising a passivation layer and a pixel electrode, wherein the passivation layer covers the source electrode, the drain electrode and the pixel drain electrode, and a pixel electrode contact via hole is formed in the passivation layer corresponding to the pixel drain electrode to electrically connect the pixel electrode and the pixel drain electrode.

5. The array substrate of claim 4, wherein the second via is disposed below the pixel electrode contact via.

6. The array substrate of claim 4, wherein the pixel drain comprises a plurality of sub-pixel drains spaced apart from each other, the plurality of sub-pixel drains are electrically connected to each other, and the second via is disposed on the sub-pixel drain not corresponding to the pixel electrode contact via.

7. The array substrate of any one of claims 3-6, wherein a storage capacitor electrode is disposed on the substrate, and the pixel drain and the storage capacitor electrode are disposed in a corresponding position to form a storage capacitor.

8. The array substrate of claim 7, wherein the side of the pixel drain is provided with at least one notch recessed toward the center of the second via.

9. A method for manufacturing an array substrate, the method being used for manufacturing the array substrate according to any one of claims 1 to 8, the method comprising:

depositing a semiconductor layer above the substrate base plate, and forming the first semiconductor pattern and the second semiconductor pattern which are arranged at intervals through a composition process;

depositing a protective layer on the first semiconductor pattern and the second semiconductor pattern, and forming the first protective pattern and the second protective pattern through a composition process, wherein the first protective pattern is provided with the first via hole, and the second protective pattern is provided with the second via hole;

depositing a source drain metal layer on the first protection pattern and the second protection pattern, and forming the source electrode, the drain electrode and the pixel drain electrode respectively through a composition process;

and the outer contour of the pixel drain covers the outer contour of the second through hole.

10. A method for detecting a pattern shift of an array substrate, for detecting a shift of a channel of a thin film transistor in the array substrate according to any one of claims 1 to 8, comprising:

detecting an aperture value of the second via hole corresponding to each of the thin film transistors and a distance value between an outer contour of the second via hole or an outer contour of the second semiconductor pattern and each side of the pixel drain,

and judging whether the array substrate is normal or not according to the aperture value of the second via hole and the distance.

Technical Field

The invention relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof, and a pattern deviation detection method of the array substrate.

Background

The liquid crystal display panel is composed of a color filter substrate, a thin film transistor array substrate and a liquid crystal layer arranged between the two substrates. In the manufacturing process of the array substrate, the lamination pattern of the channel of the thin film transistor is deviated, so that the array substrate is in failure at the time of lighting, that is, the periphery of the array substrate is in failure of blurring and non-uniformity. Therefore, in the process of the array substrate, it is often necessary to detect the lamination pattern of the channel of the thin film transistor.

For the channel lamination pattern of the thin film transistor, the conventional detection method generally adopts a measuring instrument to detect the relative position of the outline of the source contact via hole and the side edge of the outline of the source metal. As shown in fig. 1 and 2, the aperture of the source contact via 81 is directly detected, and the pitch of the metal sides of the source contact via 81 and the source 82 is detected, and the aperture and pitch are required to be within a certain range to ensure good product yield, for example, the normal range of the pitch of the metal sides of the source contact via 81 and the source 82 is 2 to 3 μm, and when it is less than 1 μm, the above-mentioned defect at the time of lighting occurs, and when it is 0, the lighting defect occurs.

However, in the above method, when the lamination pattern of the thin film transistor is greatly deviated, that is, the source contact via is closer to the side of the source metal, the situation that the measuring instrument cannot catch the source contact via and the side of the source metal easily occurs, resulting in detection failure.

Disclosure of Invention

The invention provides an array substrate, a manufacturing method thereof and a detection method of pattern deviation of the array substrate, which can reduce the occurrence of inaccurate detection and improve the detection accuracy.

In a first aspect, the invention provides an array substrate, which comprises at least one thin film transistor and an offset monitoring pattern, wherein the thin film transistor is arranged on a substrate and comprises a first semiconductor pattern, a first protection pattern, a source electrode and a drain electrode which are arranged on the same layer, the first protection pattern covers the first semiconductor pattern, a first through hole is formed in the first protection pattern, and the source electrode and the drain electrode are respectively contacted with the first semiconductor pattern through the first through hole; the offset monitoring pattern includes: the second semiconductor pattern is arranged on the same layer as the first semiconductor pattern, the second protection pattern is arranged on the same layer as the first protection pattern, and the pixel drain electrode is arranged on the same layer as the source electrode and the drain electrode; the outer contour of the pixel drain covers the outer contour of the second through hole.

In a second aspect, the present invention provides a method for manufacturing an array substrate, for manufacturing the array substrate, the method including: depositing a semiconductor layer on a substrate, and forming a first semiconductor pattern and a second semiconductor pattern which are arranged at intervals through a composition process; depositing a protective layer on the first semiconductor pattern and the second semiconductor pattern, and forming a first protective pattern and a second protective pattern through a composition process, wherein the first protective pattern is provided with a first through hole, and the second protective pattern is provided with a second through hole; depositing a source drain metal layer on the first protection pattern and the second protection pattern, and respectively forming a source electrode, a drain electrode and a pixel drain electrode through a composition process; the outer contour of the pixel drain covers the outer contour of the second through hole.

In a third aspect, the present invention provides a method for detecting a pattern shift of an array substrate, for detecting a shift of a channel of a thin film transistor in the array substrate, including: and detecting the aperture value of the second via hole corresponding to each thin film transistor and the distance value between each second via hole and each side edge of the pixel drain, and judging whether the array substrate is normal or not according to the aperture value and the distance of the second via hole.

According to the array substrate, the manufacturing method thereof and the detection method of the pattern deviation of the array substrate, the deviation monitoring graph comprises the following steps: a second semiconductor pattern disposed in the same layer as the first semiconductor pattern, a second protection pattern disposed in the same layer as the first protection pattern, and a pixel drain disposed in the same layer as the source and drain, and a second via hole formed on the second protection pattern, therefore, the first semiconductor pattern and the second semiconductor pattern are formed simultaneously in the same process, and similarly, the first protection pattern and the second protection pattern, the source electrode, the drain electrode and the pixel drain electrode, and the second via hole and the first via hole are also formed simultaneously in the same process, and since the pixel drain and the drain are electrically connected, the positional relationship between the pixel drain of the offset monitoring pattern and the second via hole can reflect the relative positional relationship between the source metal or the drain metal and the first via hole, the detection of the source metal (drain metal) and the first via may be replaced with the detection of the shift monitor pattern.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a top view of a prior art array substrate;

FIG. 2 is a cross-sectional view taken along line A-A of a prior art array substrate;

FIG. 3 is a diagram illustrating a situation where the lamination pattern of a thin film transistor in an array substrate of the prior art has a large offset;

fig. 4 is a schematic view of an array substrate according to an embodiment of the invention;

fig. 4a is a schematic structural diagram of performing offset detection on an array substrate according to a first embodiment of the invention;

fig. 4b is a schematic structural diagram of performing offset detection on the array substrate according to the first embodiment of the invention;

fig. 4c is a schematic structural diagram of performing offset detection on the array substrate according to the first embodiment of the invention;

fig. 4d is a schematic structural diagram of performing offset detection on the array substrate according to the first embodiment of the invention;

FIG. 5 is a cross-sectional view taken along line B-B of FIG. 4;

FIG. 6 is a cross-sectional view taken along line C-C of FIG. 4;

fig. 7 is a schematic diagram of an array substrate with a structure according to an embodiment of the present invention;

FIG. 8 is a cross-sectional view taken along line D-D of FIG. 7;

FIG. 9 is a schematic view of the array substrate of FIG. 8 after deposition of pixel electrodes;

FIG. 10 is a cross-sectional view taken along line D-D of FIG. 9;

FIG. 11 is a schematic structural diagram of an offset monitor pattern of another structure according to an embodiment of the present invention;

fig. 12 is a schematic flowchart of a method for manufacturing an array substrate according to a second embodiment of the invention;

fig. 13 is a top view of an array substrate according to a second embodiment of the present invention;

fig. 14 is a cross-sectional view taken along line F-F of an array substrate according to a second embodiment of the present invention;

fig. 15 is a flowchart illustrating a method for detecting a pattern shift of an array substrate according to a third embodiment of the present invention.

Description of reference numerals:

1-a first semiconductor pattern; 2-a first protection pattern; 3. 82-source electrode; 5. 87-a drain electrode; 21. 22-a first via; 6-a second semiconductor pattern; 7-a second protection pattern; 9-pixel drain; 10-a substrate base plate; 71-a second via; 12-a passivation layer; 13-pixel electrode; 14-pixel electrode contact vias; 15-storage capacitor electrodes; 81-source contact vias; 83-substrate base plate; 84-a first insulating layer; 85-a semiconductor pattern; 86-a protection pattern; 88-a drain contact via; 4. 89-a grid; 91. 92-subpixel drain; 100-thin film transistors; 200-offset monitor pattern.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a top view of a prior art array substrate; fig. 2 is a cross-sectional view taken along line a-a of a related art array substrate, and fig. 3 is a schematic view illustrating a case where a lamination pattern of a thin film transistor in the related art array substrate is greatly shifted. As shown in fig. 1, 2 and 3, the array substrate in the prior art includes a substrate 83, a gate electrode 89, a first insulating layer 84, a semiconductor pattern 85, a protective pattern 86, a source electrode 82 and a drain electrode 87. The gate electrode 89 is located on the substrate 83, the first insulating layer 84 covers the gate electrode 89 and the substrate 83, the semiconductor pattern 85 covers a portion of the first insulating layer and is located above the gate electrode 89, the protection pattern 86, i.e., an etching barrier layer, covers the semiconductor pattern 85 and protects the semiconductor pattern 85 when the source and the drain are etched, in addition, an active contact via 81 and a drain contact via 88 are formed on the protection pattern 86, a portion of the source 82 is deposited in the source contact via 81 so that the source 82 contacts the semiconductor pattern 85, and a portion of the drain 87 is deposited in the drain contact via 88 so that the drain 87 contacts the semiconductor pattern 85. The metal of the source contact via 81 and the source 82, and the metal of the drain contact via 88 and the drain 87 can be seen more clearly in the top view. In practice, the lamination pattern of the thin film transistor is monitored by the aperture of the source contact via 81 and the pitch of the sides of the metal of the source contact via 81 and the source 82. In addition, in the present application, for convenience of description, the offset of the channel of the thin film transistor is monitored by using the pattern of the source and source metal vias, or the offset of the channel of the thin film transistor is monitored by using the pattern of the drain and drain metal vias, which is similar to the above process and is not described herein again.

However, when the laminate pattern of the thin film transistor is greatly shifted, for example, as shown in fig. 3, when the distance from the source contact via 81 to the side of the metal of the source 82 is short, that is, close to 0, it is easy to cause a case where the measuring instrument cannot capture the source contact via 81 and the side of the metal of the source 82, which may result in a detection failure. The present invention has been made to solve the above problems.