阅读说明：本技术 金属结构、器件和方法 (Metal structure, device and method ) 是由 D.J.齐拉思 M.麦克斯温尼 J.法默 A.S.乔杜里 于 2019-05-21 设计创作，主要内容包括：本文提供金属结构,所述金属结构可以包括钴合金、镍合金或镍,以及有关的设备和方法。所述金属结构可以通过化学气相沉积(CVD)来被形成,并且可以包括在CVD过程期间所使用的前体材料的痕量。(Provided herein are metal structures, which may include cobalt alloys, nickel alloys, or nickel, and related devices and methods. The metal structure may be formed by Chemical Vapor Deposition (CVD) and may include trace amounts of precursor materials used during the CVD process.)

1. A metal structure, comprising:

a or B; and

one or more of carbon, nitrogen, oxygen, phosphorus, halogen, or hydrogen;

wherein A comprises:

b weight percent Co;

q weight percent Q; and

z weight percent Z;

wherein the sum of b, q and z equals 100%; b is between 50% and 99.99%, q is between 0.01% and 50%; z is between 0% and 49.9%; when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; and Z is selected from Mo or W;

wherein B comprises:

d weight percent Ni;

e weight percent of X; and

f weight percent G;

wherein the sum of d, e and f equals 100%; d is between 50% and 100%, e is between 0% and 50%, f is between 0% and 49.99%; when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

2. The metal structure of claim 1, wherein the metal structure comprises a.

3. The metal structure of claim 1, wherein the metal structure comprises B.

4. The metal structure of claim 1, wherein the metal structure comprises carbon.

5. The metal structure of claim 1, wherein the metal structure comprises nitrogen.

6. The metal structure of claim 1, wherein the metal structure comprises phosphorus.

7. The metal structure of claim 1, wherein the metal structure comprises a halogen.

8. The metal structure of claim 1, wherein the metal structure comprises hydrogen.

9. The metal structure of claim 1, wherein the metal structure is a transistor gate.

10. The metal structure according to any of claims 1-9, wherein the metal structure is a metal interconnect.

11. The metal structure of any of claims 1-9, wherein the metal structure is included in an Integrated Circuit (IC) die.

12. The metal structure according to any of claims 1-9, wherein the metal structure is comprised in a package substrate.

13. The metal structure of any of claims 1-9, wherein the metal structure comprises a seed layer, a fill material, or a cap, and a or B is present in at least one of the seed layer, the fill material, or the cap.

14. An Integrated Circuit (IC) die, comprising:

a metal interconnect, the metal interconnect comprising:

one or more of carbon, nitrogen, oxygen, phosphorus, halogen, or hydrogen; and

a compound according to formula (I) or formula (II) — a compound according to formula (I) or formula (II)

Co_bQ_qZ_z(formula (I)),

Ni_dX_eG_f(formula (II));

wherein b, q and z are weight percentages based on the total weight of the compound according to formula (I), b is between 50% and 99.99%; q is between 0.01% and 50% and z is between 0% and 49.9%;

wherein when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr;

wherein when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta;

wherein Z is selected from Mo or W; and is

Wherein d, e and f are weight percentages based on the total weight of the compound according to formula (II), d is between 50% and 100%, e is between 0% and 50%, f is between 0% and 49.99%;

wherein when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W;

wherein when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and is

Wherein G is selected from Mo or W.

15. The IC die of claim 14, wherein the metal interconnect comprises a compound according to formula (I).

16. The IC die of claim 14, wherein the metal interconnect comprises a compound according to formula (II).

17. The IC die of any of claims 14-16, further comprising:

one or more transistors.

18. The IC die of any of claims 14-16, further comprising:

one or more conductive pads at an outer face of the IC die.

19. A method of forming a metal structure, comprising:

providing an initial structure; and

forming a metal on the initial structure by Chemical Vapor Deposition (CVD);

wherein the precursors used during CVD comprise one or more of carbon, nitrogen, oxygen, phosphorus, halogen, or hydrogen;

wherein the metal comprises A or B;

wherein A comprises:

b weight percent Co;

q weight percent Q; and

z weight percent Z;

wherein the sum of b, q and z equals 100%; b is between 50% and 99.99%, q is between 0.01% and 50%; z is between 0% and 49.9%; when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; and Z is selected from Mo or W;

wherein B comprises:

d weight percent Ni;

e weight percent of X; and

f weight percent G;

wherein the sum of d, e and f equals 100%; d is between 50% and 100%, e is between 0% and 50%, f is between 0% and 49.99%; when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

20. The method of claim 19, wherein forming metal on the initial structure by CVD comprises performing Atomic Layer Deposition (ALD).

21. The method of claim 19, wherein the initial structure comprises:

a dielectric layer deposited on a substrate, the substrate comprising a conductive region; and

an opening in the dielectric layer exposing a conductive region of the substrate, the opening having a lower portion and an upper portion, wherein the upper portion is wider than the lower portion.

22. A computing device, comprising:

an Integrated Circuit (IC) package including an IC die coupled to a package substrate;

a circuit board, wherein the IC package is coupled to the circuit board;

wherein the computing device comprises a metal structure comprising A or B;

wherein the metal structure further comprises a trace amount of a Chemical Vapor Deposition (CVD) precursor material;

wherein A comprises:

b weight percent Co;

q weight percent Q; and

z weight percent Z;

wherein the sum of b, q and z equals 100%; b is between 50% and 99.99%, q is between 0.01% and 50%; z is between 0% and 49.9%; when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; and Z is selected from Mo or W;

wherein B comprises:

d weight percent Ni;

e weight percent of X; and

f weight percent G;

wherein the sum of d, e and f equals 100%; d is between 50% and 100%, e is between 0% and 50%, f is between 0% and 49.99%; when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

23. The computing device of claim 22, wherein the trace amounts of CVD precursor materials include one or more of carbon, nitrogen, oxygen, phosphorous, a halogen, or hydrogen.

24. The computing device of any of claims 22-23, wherein the computing device is a laptop computer, a handheld computing device, or a server.

25. The computing device of any of claims 22-23, further comprising:

a display coupled to the circuit board or an antenna coupled to the circuit board.

Background

Integrated Circuit (IC) devices typically include circuit elements, such as transistors, capacitors, and resistors, that are formed in or on a semiconductor substrate. Interconnect structures are used to electrically couple or connect discrete circuit elements into functional circuits.

Drawings

Fig. 1A-1F are side cross-sectional views of various stages in the manufacture of metal interconnects in accordance with various embodiments.

Fig. 2 is a side cross-sectional view of an embodiment of a metal interconnect.

Fig. 3 is a side cross-sectional view of an embodiment of a metal interconnect including an embodiment of a capping layer (overburden).

Fig. 4 is a side cross-sectional view of an embodiment of a metal interconnect including an embodiment of a cap (cap).

FIG. 5 is a flow chart depicting one embodiment of a method of forming a metal interconnect.

Fig. 6 is a top view of a wafer and a die that may include metal interconnects according to any of the embodiments disclosed herein.

Fig. 7 is a side cross-sectional view of an Integrated Circuit (IC) device that may include metal interconnects in accordance with any of the embodiments disclosed herein.

Fig. 8 is a side cross-sectional view of an IC package that may include metal interconnects in accordance with various embodiments.

Fig. 9 is a side cross-sectional view of an IC device assembly that may include a metal interconnect in accordance with any of the embodiments disclosed herein.

Fig. 10 is a block diagram of an example electrical device that may include a metal interconnect in accordance with any of the embodiments disclosed herein.

Detailed Description

Conventional interconnect structures may be formed of copper (Cu) or tungsten (W). However, copper and tungsten can present difficulties when attempting to shrink the size of the interconnect. For example, when copper or tungsten is used, void-free fabrication of the interconnect is difficult, particularly as the interconnect is reduced in size. When tungsten is used, barrier/adhesion layers (e.g., tantalum (Ta) barriers) and nucleation layers; however, nucleation layers tend to have relatively high resistance, and processing of tungsten typically relies on Chemical Vapor Deposition (CVD) or conformal processes, which can cause undesirable seams, keyholes, or combinations thereof in the interconnect structure. When copper is used, the resistivity of the interconnect structure may increase as the structure size decreases, and undesirable electromigration may deteriorate.

Other materials may be used in the interconnect. For example, cobalt (Co) may have a lower resistivity than tantalum barriers and tungsten nucleation layers, a higher melting point than copper (which results in a relatively high activation energy for diffusion, thereby mitigating electromigration and improving reliability), an ability to recrystallize upon annealing (thereby enabling reflow for better gap fill), and/or a better adhesion strength for oxidation than copper.

Nevertheless, the use of cobalt as a metal interconnect material can be challenging due to the fact that: cobalt interconnects are susceptible to corrosion, especially at pH less than 9. However, it may not be practical or possible to employ a solution with a higher pH during manufacturing. Other challenges that may be associated with cobalt-based interconnect structures may include stress-induced voiding.

Provided herein are metal interconnects comprising cobalt alloys, nickel alloys, or combinations thereof that may be less susceptible to corrosion than cobalt, as well as techniques and precursor materials for fabricating such interconnects. Some embodiments of metal interconnects provided herein may be less susceptible to corrosion than previous cobalt interconnects while having or maintaining low resistance, reliability, or a combination thereof. Some embodiments of metal interconnects provided herein may be less susceptible to at least one of stress-induced voiding or electromigration than previous cobalt interconnects. In particular embodiments, the metal alloys of the interconnects provided herein have higher melting points than previous cobalt interconnects. Some embodiments of the metal interconnects disclosed herein may have higher activation energies than previous cobalt interconnects, reducing interdiffusion, stress-induced voiding, and/or electromigration. Some embodiments of the metal alloys provided herein may be less susceptible to corrosion and void migration than previous cobalt interconnects, which may result in improved end-of-line yield.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

Various operations may then be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. The operations described may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed and/or the operations described may be omitted.

For the purposes of this disclosure, the phrase "a and/or B" means (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C). The drawings are not necessarily to scale. Although many of the figures illustrate straight line structures with flat walls and right angle corners, this is for ease of illustration only, and the actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

The description uses the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, "package" and "Integrated Circuit (IC) package" are synonymous. When used to describe ranges of sizes, the phrase "between X and Y" means a range that includes X and Y. For convenience, the phrase "FIG. 1" may be used to refer to the collection of drawings of FIGS. 1A-1F.

The metal interconnect 100 disclosed herein may include a compound according to formula (I):

Co_bQ_qZ_z(formula (I)),

wherein b, q and z are weight percentages of the total weight of the compound of formula (I); b. the sum of q and z equals 100%; when z is 0%, Q is selected from nickel (Ni), aluminum (Al), manganese (Mn), silicon (Si), chromium (Cr), vanadium (V), molybdenum (Mo), niobium (Nb), Ta, W or zirconium (Zr); when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; and Z is selected from Mo or W.

The metal interconnect 100 disclosed herein may include a compound according to formula (II):

Ni_dX_eG_f (formula (II));

wherein d, e and f are weight percentages of the total weight of the compound of formula (I); d. the sum of e and f equals 100%; when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

For example, the metal interconnect 100 disclosed herein may include a compound according to formula (III) or formula (IV) — formula (III) or formula (IV) —

Co_bQ_qZ_z(formula (III)),

Ni_dX_eG_f (formula (IV));

wherein b is a weight percentage of about 50% to about 99.99% based on the total weight of the compound of formula (I); q is a weight percentage of about 0.01% to about 50% based on the total weight of the compound of formula (I); z is a weight percentage of 0% to about 49.9% based on the total weight of the compound of formula (I); when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; z is selected from Mo or W; d is a weight percentage of about 50% to 100% based on the total weight of the compound of formula (II); e is a weight percent of 0% to about 50% based on the total weight of the compound of formula (II); f is a weight percent of 0% to about 49.99% based on the total weight of the compound of formula (II); when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

The metal interconnect 100 may include a compound of formula (I) or formula (II) in any of a plurality of interconnect regions, such as a barrier and/or adhesion layer, a seed layer, a fill material, or a cap. Such embodiments are discussed in further detail below.

Some examples of metal interconnects 100 disclosed herein may include a compound according to formula (I), wherein Q is Ni; b is from about 80% to about 95%; q is from about 5% to about 20%; and z is 0%. In some embodiments, metal interconnect 100 comprises a compound according to formula (I), wherein Q is Ni; b is about 84% to about 88%; q is from about 12% to about 16%; and z is 0%. In further embodiments, the metal interconnect comprises a compound according to formula (I) wherein Q is Ni; b is about 86%; q is about 14%; and z is 0%. In still further embodiments, the metal interconnect 100 may include a compound according to formula (I), wherein Q is Ni; b is from about 96% to about 99%; q is from about 1% to about 4%; and z is 0%. In further embodiments, the metal interconnect 100 may include a compound according to formula (I), wherein Q is Ni; b is about 96% to about 98%; q is about 2% to about 4%; and z is 0%. In particular embodiments, metal interconnect 100 may include a compound according to formula (I), wherein Q is Ni; b is about 97%; q is about 3%; and z is 0%. In certain embodiments, the metal interconnect 100 comprises a compound according to formula (I), wherein Q is Si, and z is 0%.

Some examples of metal interconnects 100 include compounds according to formula (II) where e and f are 0%.

Some examples of metal interconnects 100 include compounds according to formula (II) where d is from about 90% to about 92%, f is 0%, X is selected from V or W, and e is from about 8% to about 10%. In another embodiment, the metal interconnect 100 includes a compound according to formula (II) wherein d is about 80% to about 84%, e is about 8% to about 10%, X is V, f is about 8% to about 10%, and G is W.

Some examples of the metal interconnect 100 include a compound according to formula (I) or a compound according to formula (II), including at least one of Mo or W, wherein Mo or W are independently present in a weight percentage of about 0.01% to about 1% based on a total weight of the compound according to formula (I) or the compound according to formula (II), respectively.

Without wishing to be bound by any particular theory, it is believed that the inclusion of Mo or W in the compounds of formula (I) and/or formula (II) may lower the bulk resistivity, impart a melting point greater than that of cobalt or nickel, or a combination thereof, possibly improving performance, increasing activation energy, reducing interdiffusion, or a combination thereof. Without wishing to be bound by any particular theory, it is believed that the inclusion of Al, Mn, Si, Cr, V, Ta or Nb in the compounds of formula (I) and/or formula (II) may passivate the cobalt or nickel surface, thereby preventing or reducing the likelihood of corrosion, due to its relatively high affinity for forming metal oxide bonds. It is believed that Al, Mn, Si and Cr are fast diffusers in metals, form very stable metal oxides, or combinations thereof. Al (Al)₂O₃、Cr₂O₃、SiO₂、MnO₂And MnO has a negative heat of formation that is about five to about six times the negative heat of CoO. Without wishing to be bound by any particular theory, it is believed that inclusion of Cr, Ta, Nb, or V in the compounds of formula (I) and/or formula (II) may impart a melting point greater than that of cobalt and/or nickel, which may increase activation energy and/or reduce interdiffusion, thereby improving stress-induced voiding and electromigration. Without wishing to be bound by any particular theory, it is believed that the brazilian diagram (Pourbaix diagram) of Cr compared to Co implies a wider pH window for passive metal oxide layer formation. At neutral pH, Cr can form Cr₂O₃It may be a very stable oxide.

The metal interconnect 100 disclosed herein may include a compound according to formula (I), a compound according to formula (II), or a compound according to formula (I) and a compound according to formula (II).

As noted above, in some embodiments, the metal interconnect 100 provided herein comprises a compound according to formula (I), and the compound according to formula (I) is present in at least one of a barrier and/or adhesion layer, a seed layer, a fill material, or a cap. In other embodiments, the metal interconnect 100 provided herein comprises a compound according to formula (II), and the compound according to formula (II) is present in at least one of a barrier and/or adhesion layer, a seed layer, a fill material, or a cap. For example, a compound of formula (I) or a compound of formula (II) may be present in: [1] barrier and/or adhesion layer, [2] seed layer, [3] fill material, [4] cap, [5] barrier and/or adhesion layer and seed layer, [6] barrier and/or adhesion layer and fill material, [7] seed layer and fill material, [8] fill material and cap, [9] barrier and/or adhesion layer, fill material, seed layer and cap, and the like.

As used herein, the phrase "present in at least one of the barrier and/or adhesion layer, seed layer, fill material, or cap" describes a compound of formula (I) and/or formula (II) present in at least one of the barrier and/or adhesion layer, seed layer, fill material, or cap before, during, or after deposition of the barrier and/or adhesion layer, seed layer, fill material, and cap (e.g., in a damascene or dual damascene process such as the process discussed below). For example, the compounds of formula (I) and/or (II) may be present in the seed layer prior to depositing the seed layer in a damascene or dual damascene structure. As a further example, the compound of formula (I) and/or (II) may not be present in the seed layer before or during deposition of the seed layer in a damascene or dual damascene structure, but after performing further processing, such as annealing, the compound of formula (I) and/or (II) may be present in the seed layer. In each of these examples, the metal interconnect 100 includes a seed layer in which a compound of formula (I) and/or formula (II) is present.

As used herein, the phrase "present in … …" should not be construed to define the composition of a barrier and/or adhesion layer, seed layer, fill material, or cap. For example, in one embodiment, the compound of formula (I) "resides" in the seed layer, and the seed layer may include [1] only the compound of formula (I), or [2] the compound of formula (I) and at least one other component.

In some embodiments, the metal interconnect 100 disclosed herein comprises a compound according to formula (I) and a compound according to formula (II), and the compounds according to formula (I) and formula (II) are independently present in at least one of a barrier and/or adhesion layer, a seed layer, a fill material, or a cap. The compound according to formula (I) and the compound according to formula (II) may be present in one or more of the same layer or material, one or more different layers or materials, or a combination thereof. For example, the compound according to formula (I) may be present in the seed layer, and the compound according to formula (II) may be present in the fill material. As a further example, the compound according to formula (I) and the compound according to formula (II) may be present in the seed layer. As another example, the compound according to formula (I) may be present in the seed layer and the fill material, and the compound according to formula (II) may be present in the fill material and the barrier and/or adhesion layer.

A method of forming a metal interconnect 100, the metal interconnect 100 comprising at least one compound according to formula (I), at least one compound according to formula (II), or a combination thereof, is discussed below with reference to fig. 1-5. In an embodiment, a method of forming metal interconnect 100 includes: providing a damascene or dual damascene structure; depositing a barrier and/or adhesion layer on the damascene or dual damascene structure; depositing a seed layer on the barrier and/or adhesion layer; depositing a fill material in a damascene or dual damascene structure; and depositing (i) a capping layer, or (ii) a cap, over the fill material. At least one of the barrier and/or adhesion layer, the seed layer, the fill material, the cap layer, or the cap can include at least one compound according to formula (I), at least one compound according to formula (II), or a combination thereof. The methods provided herein may also include one or more additional features, such as annealing the metal interconnect, polishing the metal interconnect 100, removing one or more portions of the layer(s) and/or material(s) deposited outside of the damascene or dual damascene structure, or a combination thereof.

When the methods provided herein include depositing an overlayer, the methods can further include [1] annealing the metal interconnect 100, [2] polishing the overlayer, or [3] annealing the metal interconnect 100 and polishing the overlayer. Polishing can be achieved by any known technique, such as Chemical Mechanical Planarization (CMP).

When the methods provided herein include depositing a cap, the methods may further include removing at least a portion of the barrier and/or adhesion layer, the fill material, the seed layer, or a combination thereof deposited outside of the damascene or dual damascene structure. Removing at least a portion of the barrier and/or adhesion layer, the fill material, the seed layer, or a combination thereof may be performed prior to depositing the cap and is accomplished by any known technique. In one embodiment, the removing comprises CMP.

The components of the methods discussed herein may comprise any known structures. In an embodiment, an assembly includes a dielectric layer deposited on a substrate; and an opening in the dielectric layer, the opening having a lower portion and an upper portion, wherein the upper portion is wider than the lower portion. In further embodiments, the assembly includes a dielectric layer deposited on the substrate; and an opening in the dielectric layer, the opening exposing the conductive region of the substrate, the opening having a lower portion and an upper portion, wherein the upper portion is wider than the lower portion.

One embodiment of an assembly 1200 is depicted in FIG. 1A. Fig. 1A depicts a substrate 106 having a top surface 108 that may be used as a substrate to which interconnects may be formed. Substrate 106 may include any portion of a partially fabricated IC on which metal interconnects may be fabricated. For example, the substrate 106 may include or may have formed thereon active and/or passive devices. As depicted at fig. 1A, conductive region 155 is included in substrate 106, to which substrate 106 metal interconnect 100 may be formed. The substrate 106 may be processed through a front end of line (FEOL) process and the conductive regions 155 may be diffusion regions formed in a crystalline semiconductor substrate or layer. For example, the conductive region may be a source or drain region of a transistor. Conductive regions 155 may be underlying metal lines in a back-end-of-line (BEOL) metallization structure. Although embodiments of the assembly 1200 may be ideally suited for fabricating semiconductor integrated circuits, including but not limited to microprocessors, memories, Charge Coupled Devices (CCDs), system on a chip (SoC) ICs, or baseband processors, other applications may also include microelectronic machines, micro-electro-mechanical systems (MEMS), lasers, optics, packaging layers, and so forth. Embodiments of assembly 1200 may also be used to fabricate a single semiconductor device, including but not limited to the gate electrode of a Metal Oxide Semiconductor (MOS) transistor.

The component 1200 depicted in fig. 1A includes a dielectric material 102 formed over a substrate 106. The dielectric material 102 may comprise any suitable dielectric or insulating material, such as silicon dioxide, SiOF, carbon-doped oxides, glass, or polymeric materials. Openings in the dielectric material 102 expose the conductive regions 155 and eventually make contact thereto through interconnects, and include lower openings 114 having sidewalls 116 and upper openings 110 having sidewalls 112. Although two openings are depicted, it is to be appreciated that a single opening may instead be formed in the dielectric material 102, as used, for example, in a single damascene approach where only lines or vias, but not both, are fabricated in a single operation. One or more openings may be fabricated in the dielectric material 102 by: known photolithography and etch processing techniques commonly used in damascene and dual damascene type fabrication. Although only a single dielectric material 102 is depicted, multiple layers of the same or different dielectric materials may be used instead. For example, a first dielectric layer may have an opening 114 therein, and a second dielectric layer may have an opening 110 therein. In the embodiment depicted at fig. 1A, the dielectric material 102 is on an etch stop layer 104 deposited on a substrate 106. The etch stop layer 104 may comprise any suitable material, such as silicon nitride, silicon oxynitride, or a combination thereof.

Embodiments of the methods provided herein include "depositing" a layer or material on another layer or material. "deposition" may be achieved by: any known technique that may be suitable for a particular layer or material includes, but is not limited to, CVD, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), electroplating, electroless plating, one or more other suitable processes to deposit conformal thin films, or a combination thereof.

Thin film deposition methods using processes such as CVD, ALD, and PVD may vary depending on the desired process time, thickness, and uniformity quality. For example, depositing a seed layer using CVD may create a conformal thin film layer faster than it would be expensive for an ALD process to deposit the same layer; however, the quality of thin films deposited by CVD processes may be lower than the quality of thin films deposited by ALD processes. The PVD process can be performed with an increased distance between the receiving substrate and the corresponding sputtering target to form a conformal thin film.

Fig. 1B depicts assembly 1202 after forming barrier/adhesion layer 120 on assembly 1200 (fig. 1A). Barrier/adhesion layer 120 may be formed on top surface 108 of dielectric material 102, as well as on exposed top surface 108 of substrate 106 (e.g., on conductive region 155). In the embodiment depicted at fig. 1B, a barrier/adhesion layer 120 is also formed on the sidewalls 116 of the lower opening 114 and the sidewalls 112 of the upper opening 110. The barrier/adhesion layer 120 disclosed herein may comprise Ta, TaN, TiN, WN, or a combination thereof. In one embodiment, barrier/adhesion layer 120 is a tantalum nitride/tantalum (TNT) layer. In another embodiment, barrier/adhesion layer 120 is a titanium nitride/titanium layer. However, in some embodiments, no barrier/adhesion layer 120 is used in the method or included in the metal interconnect 100 provided herein. When barrier/adhesion layer 120 is not used, a seed layer may be formed directly on dielectric material 102 and, if present, conductive region 155.

Fig. 1C depicts component 1204 after forming seed layer 130 over component 1202 (fig. 1B). The seed layer 130 of fig. 1C is deposited on the barrier/adhesion layer 120. The seed layer 130 disclosed herein may include cobalt, a compound of formula (I), a compound of formula (II), or a combination thereof. The seed layer 130 can be a conformal layer. In one embodiment, the seed layer 130 may have a thickness of less than 3 nanometers. For example, the seed layer 130 may have a thickness between about 1 nanometer and about 3 nanometers. The seed layer 130 may act as a nucleation layer for subsequent growth of fill material. The seed layer 130 may comprise any known seed layer material. The seed layer 130 may include cobalt. For example, in one embodiment, the seed layer 130 includes at least 50% cobalt by weight of the seed layer 130. In a particular embodiment, the seed layer 130 includes about 90% to 100% cobalt by weight of the seed layer 130. Non-limiting examples of the cobalt-based compound seed layer 130 include a cobalt silicide or cobalt germanide seed layer.

In embodiments where the seed layer 130 comprises a compound of formula (I) and/or a compound of formula (II), CVD or ALD processes may be used to deposit the seed layer 130. To do so, one or more precursors 170 can be used as part of the CVD/ALD process.

In embodiments where the seed layer 130 includes cobalt in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(A1) having the general chemical formula (CO)₆Co₂C₂RR's cobalt carbonyls with a bridging acetylene half, where R and R' can be hydrogen, alkyl (methyl, ethyl, propyl, butyl, tert-butyl, isopropyl, sec-butyl, etc.), and SiR₃A group (where R may be an alkyl group according to any of the embodiments discussed above), or other suitable ligand;

(A2) the general chemical formula is Co: (^tBuNC(R)NEt)₂Or Co (ⁱPrNC(R)NEt)₂Wherein R can be Me, Et, n-Bu or other alkyl;

(A3) carbonyl and nitrosyl cobalt compounds, including Co₂(CO)₈Or Co (CO)₃NO；

(A4) Cobalt acetylacetonate (Co (acac)₃）；

(A5) Generalization ofChemical formula is Co (Cp)₂、Co(Cp*)₂、Co(R-Cp)₂、Co(Cp)(CO)₂、Co(Cp*)(CO)₂And Co (R-Cp) (CO)₂Wherein R can be an alkyl group (methyl, ethyl, propyl, isopropyl, butyl, t-butyl, sec-butyl, etc.);

(A6) has a general chemical formula of Co [ N (R)₂]₂Wherein R is alkyl, aryl, or other group, including methyl, ethyl, propyl, isopropyl, butyl, tert-butyl, sec-butyl, and the like;

(A7) perfluorinated phosphine functionalized cobalt precursor, such as Co (PF)₃)₄H；

(A8) Heteronitrogen butadiene functionalized cobalt precursors including, but not limited to: bis (1, 4-di-homo-propyl-1, 4-diazabitadiene) cobalt; or

(A9) Hybrid precursors comprising both cyclopentadienyl and amidino moieties of general formula (R-Cp) Co (AMD) or (Cp) Co (AMD), wherein R functionality of the cyclopentadienyl ligand includes, but is not limited to, methyl, ethyl, propyl, isopropyl, butyl, tert-butyl, or sec-butyl, and amidino includes, but is not limited to: (A)^tBuNC (R) NEt) or (ⁱPrNC(R)NEt)₂Wherein R may be Me, Et, n-Bu or other alkyl.

In embodiments in which the seed layer 130 includes nickel in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(B1) nickel aminoalkoxy precursors, including Ni (dmab)₂、Ni(emab)₂And Ni (deab)₂Or using the general formula (NRR' C)₂H₃R "O), wherein R, R' and R" can be any alkyl group, including methyl, ethyl, propyl, isopropyl, butyl, tert-butyl, or sec-butyl;

(B2) has a general chemical formula of Ni: (^tBuNC(R)NEt)₂Or Ni (ⁱPrNC(R)NEt)₂Nickel amidinate of (1), wherein R can be Me, Et, n-Bu or other alkyl groups;

(B3) tetrakis (perfluorophosphonium) nickel (Ni (PF)₃)₄)；

(B4) Bis (cyclooctadiene) nickel (Ni (COD))₂)；

(B5) Having the general chemical formula Ni (Cp)₂、Ni(Cp*)₂、Ni(R-Cp)₂Wherein R can be an alkyl group (methyl, ethyl, propyl, isopropyl, butyl, t-butyl, sec-butyl, etc.);

(B6) nickel precursors based on allyl and alkylpyrrolidinimine type ligands [ Ni (allyl) (PCAI-R) ];

(B7) has a general chemical formula of Ni (NR)₂)₂The bis (dialkylamino) nickel precursor of (a), wherein R can be an alkyl group (methyl, ethyl, propyl, isopropyl, butyl, tert-butyl, sec-butyl, etc.); or

(B8) Nickel aminoimino complexes such as bis (4-N-ethylamino-3-pentene-2-N-ethylimino) nickel (II).

In embodiments in which the seed layer 130 includes aluminum in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(C1) trialkylaluminum precursors of the general formula AlR3, wherein R can be methyl, ethyl, propyl, isopropyl, butyl, tert-butyl, sec-butyl, and the like;

(C2) has a general chemical formula of AlR₂A dialkylaluminum hydride precursor of H, wherein R can be methyl, ethyl, propyl, butyl, t-butyl, isopropyl, sec-butyl, and the like;

(C3) has a general chemical formula of AlX₃The aluminum trihalide of (a), wherein X can be fluorine, chlorine, bromine or iodine;

(C4) comprising aluminum trihydride molecules AlH₃Including but not limited to the general formula NR, to lewis bases₃Wherein R may be methyl, ethyl, propyl, butyl, tert-butyl, isopropyl, sec-butyl, phenyl, or other complex alkyl or alkyl groups; or

(C5) Aluminum triacetylacetonate (Al (acac) 3).

In embodiments where the seed layer 130 includes manganese in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(D1) of the form (Cp) Mn (CO)₃、(Cp*)Mn(CO)₃And (RCp) Mn (CO)₃The cyclopentadienyl manganese carbonyl of (a), wherein the R-functionalization of the cyclopentadienyl ligand may include, but is not limited to, methyl, ethyl, butyl, t-butyl, isopropyl, propyl, or sec-butyl;

(D2) manganese homoligand compounds with two functionalized piperidinyl ligands, such as bis (2,2,6, 6-tetramethylpiperidinyl) manganese (II), where the piperidinyl groups can be functionalized with other alkyl groups besides methyl groups (such as in the examples above);

(D3) homoleptic compounds of manganese with three functionalized diheptanone ligands, such as Mn (thd)₃Where thd =2,2,6, 6-tetramethylheptane-3, 5-dione, where heptane-3, 5-dione may be functionalized with other alkyl groups than methyl (such as in the examples above);

(D4) general formula Mn (CpR)₂Or mn (CpR) (CpR '), wherein R and/or R' functionalization of the cyclopentadienyl ligand may include, but is not limited to, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, or sec-butyl; or

(D5) Imido-alkoxy compounds of manganese, such as Mn₂(^tBuNCHC(^tBu)(Me)O)₄。

In embodiments where the seed layer 130 includes chromium in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(E1) chromium triacetylacetonate (Cr (acac)₃)；

(E2) Chromium oxychloride (Cr (OCl)₃)；

(E3) In general form of Cr (benzyl)₂Dibenzyl compounds of chromium (iv);

(E4) bis-alkylbenzyl compounds of chromium, typically in the form of Cr (R-benzyl) 2 or Cr (R-benzyl) (R '-benzyl), wherein the R and/or R' functionalization of the benzyl ligand may include, but is not limited to, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, or sec-butyl; or

(E5) General chemical formula of CrX₃Wherein X may be fluorine, chlorine, bromine or iodine.

In embodiments in which the seed layer 130 includes vanadium in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(F1) in the general form of VX₄Wherein X can be fluorine, chlorine, bromine or iodine; or

(F2) In the general form V (NR)₂)₄Or V (NRR')₄Wherein the R and/or R' functionalization of the benzyl ligand can include, but is not limited to, methyl, ethyl, butyl, t-butyl, isopropyl, propyl, or sec-butyl.

In embodiments in which the seed layer 130 includes tantalum in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(G1) of the general form Ta (NR)₂)₅Or Ta (NRR')₅Wherein R and/or R' may be, but are not limited to, methyl, ethyl, butyl, t-butyl, isopropyl, propyl, or sec-butyl; or

(G2) Of the general form Ta (NR)₂)₃(= NR ' ') or Ta (NRR ')₃(= NR ") tantalum amino/imino complex, wherein R, R' and/or R" may be, but are not limited to, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, sec-butyl, pentyl, tert-pentyl, or neopentyl.

In embodiments where the seed layer 130 includes niobium in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(H1) in the general form of Nb (NR)₂)₃(= NR ' ') or Nb (NRR ')₃(= NR ") niobium amino/imino complex, wherein R, R' and/or R" may be, but are not limited to, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, sec-butyl, pentyl, tert-pentyl, or neopentyl;

(H2) of general form NbX₅Wherein X can be fluorine, chlorine, bromine or iodine; or

(H3) General chemical formula is NbX₄Wherein X may be chlorine, bromine or iodine.

In embodiments where the seed layer 130 includes molybdenum in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(I1) the general chemical formula is MoX₅Wherein X can be chlorine, bromine or iodine;

(I2) in the general form of Nb (NR)₂)₂(=NR'')₂Or Nb (NRR')₂(=NR'')₂The molybdenum amino/imino complex of (a), wherein R, R' and/or R "can be, but are not limited to, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, sec-butyl, pentyl, tert-pentyl, or neopentyl;

(I3) molybdenum oxyhalides, including MoOX₃(wherein X may be chlorine or bromine) or MoOX₄(wherein X may be fluorine or chlorine);

(I4) molybdenum carbonyl;

(I5) of general formula Mo (benzyl)₂Or Mo (R-benzyl)₂The bis-benzyl complex of molybdenum of (a), wherein R can be, but is not limited to, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, sec-butyl, pentyl, tert-pentyl, or neopentyl;

(I6) in the general form of Mo (NR)₂)₄Or Mo (NRR')₄Wherein R and/or R' may be, but are not limited to, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, or sec-butyl;

(I7) in the general form of MoX₂(adducts)₂Such as bis (THD) molybdenum (IV) dichloride (MoCl)₂(THD)₂)；

(I8) In the general form of Mo (R-allyl)₄Of molybdenum³-allyl complex, wherein R may be, but is not limited to, hydrogen, methyl, ethyl, butyl, tert-butyl, isopropyl, propyl, or sec-butyl; or

(I9) AThe general chemical formula is Mo (CO)₅(PR₃) And Mo (CO)₄(PR₃)₂Wherein R can be, but is not limited to, methyl, ethyl, butyl, t-butyl, isopropyl, propyl, or sec-butyl.

In embodiments in which the seed layer 130 includes tungsten in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(J1) tungsten carbonyl (W (CO)₆)；

(J2) In the general form WX₅And WX₆Wherein X can be chlorine, bromine, or iodine;

(J3) a bis-imino/amino compound of tungsten, generally of the form W (NRR ')2(NR ") 2, wherein R, R' and R" may be the same or different functionalities and may be, but are not limited to, methyl, trimethylsilyl, ethyl, butyl, tert-butyl, isopropyl, propyl, or sec-butyl; or

(J4) In the general form (RC)₅H₄)₂WH₂Wherein R can be, but is not limited to, methyl, ethyl, butyl, t-butyl, isopropyl, propyl, or sec-butyl.

In embodiments in which the seed layer 130 includes silicon in the compound of formula (I) and/or the compound of formula (II), an example precursor 170 includes:

(K1) silicon amides, substituted silanes (e.g., halosilanes), aminosilanes, azidosilanes, cyclic aminosilanes, and cyclic azidosilanes.

Such silicon precursors 170 may be used with suitable co-reactants to deposit thin silicon layers that may be alloyed using one of the integration schemes described herein (e.g., with reference to fig. 1-4). In some embodiments in which the seed layer 130 includes silicon in the compound of formula (I) and/or the compound of formula (II), silane, disilane, or other higher silanes (trisilane, tetrasilane, n-pentasilane, new n-pentasilane) may be used as co-reactants for one or more steps. In some embodiments in which seed layer 130 includes silicon in the compound of formula (I) and/or the compound of formula (II), silicon-containing ligand (such as trimethylsilyl) groups may replace one or more R groups in any of the compounds discussed above with reference to precursor 170. Many silanes can be strong reducing agents by their very nature.

When the seed layer 130 is deposited by CVD/ALD, the resulting seed layer 130 (and thus the resulting metal interconnect 100) may include trace impurities that are characteristic of the ligand species used in the precursor 170 (many examples of which are given above). In embodiments where the seed layer 130 (and thus the metal interconnect 100) includes carbon, the precursor 170 used in the deposition of the seed layer 130 may include carbonyl, alkyl, aryl, or other similar carbon-containing ligands, including various cyclopentadienyl ligands, cyclooctadiene, acetylene derivatives, and simple alkyl groups. In embodiments where the seed layer 130 (and thus the metal interconnect 100) includes nitrogen, the precursor 170 used in the deposition of the seed layer 130 may include amino, imino, or other nitrogen-containing ligands, such as amidino and nitrosyl groups. In embodiments where the seed layer 130 (and thus the metal interconnect 100) includes oxygen, the precursor 170 used in the deposition of the seed layer 130 may include an alkoxide, carbonyl, acetylacetonate, oxyhalide, or other oxygen-containing ligand. In embodiments where the seed layer 130 (and thus the metal interconnect 100) includes phosphorus, the precursor 170 (or co-reactant) used in the deposition of the seed layer 130 may include phosphine functionality. In embodiments where the seed layer 130 (and thus the metal interconnect 100) includes a halogen, the precursor 170 used in the deposition of the seed layer 130 may include such a halogen as a direct ligand (chloride, bromide, iodide, etc.), an oxygen-containing ligand (e.g., oxychloride), or a ligand that may functionalize another element (such as perfluorophosphine). In embodiments where the seed layer 130 (and thus the metal interconnect 100) includes hydrogen, the precursor 170 used in the deposition of the seed layer 130 may include elemental hydrogen used as a ligand or eliminated hydrogen as part of a larger carbon-containing ligand, or hydrogen may be used as a co-reactant.

When a material according to formula (I) or formula (II) is deposited using CVD/ALD (e.g., seed layer 130, fill material 140, capping layer 150, or cap 440, discussed below), the deposition process may take any of a variety of suitable forms. In some embodiments, the primary element, the secondary element, and the third element may be deposited using blanket deposition; such embodiments may permit the use of precursors 170 (particularly for secondary and tertiary elements), and thus may generate high quality modes, but may have poor gap-fill characteristics relative to some other embodiments. In some embodiments, the primary element may be deposited using bottom-up fill, and the secondary element and the third element may be deposited using blanket deposition; such embodiments may involve the use of selective precursors 170 for the primary element. In some embodiments, the primary elements may be deposited using bottom-up fill, and the secondary elements may be selectively deposited (using two selective precursors 170); the third element may be deposited selectively or with a blanket film. In some embodiments, the primary element may be deposited using blanket deposition, and may then be polished, followed by selective deposition of the secondary element; the third element may be deposited selectively or with a blanket film. In such embodiments, it may be desirable for the deposition process to be directed to the primary element to have reasonable gap-filling properties, and the precursor 170 for the secondary element may be selective. In some embodiments, the primary element, the secondary element, and optionally the third element may be deposited using a nanolaminate process; such embodiments may involve a precursor 170 that has good conformality and may provide an easier final film to alloy in a post-anneal process. When selective deposition is performed, the process may include intrinsically selective precursors 170 or the selectivity may be generated using an appropriate surface treatment (e.g., a self-assembled monolayer, other blocking layer, or an activation process that creates nucleation sites). In the example of the above embodiment where the ALD/CVD compound is according to formula (I), when the third element is not present, the primary element is Co and the secondary element is Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when the third element is present, the main element is Co, the secondary element is Ni, Al, Mn, Si, Cr, V, Nb, or Ta, and the third element is Mo or W. In the example of the above embodiment where the ALD/CVD compound is according to formula (II), when the third element is not present, the primary element is Ni and the secondary element is Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when the third element is present, the main element is Ni, the secondary element may be Co, Al, Mn, Si, Cr, V, Nb, or Ta, and the third element is Mo or W.

Fig. 1D depicts assembly 1206 after forming filler material 140 over assembly 1204 (fig. 1C). Fig. 1D depicts an embodiment in which the fill material 140 is deposited on the seed layer 130 such that the fill material 140 completely fills the openings (110, 114). The filling material 140 may include at least one of a compound of formula (I) or a compound of formula (II). In general, any known filler material may be used as the filler material 140. For example, in one embodiment, the filler material 140 may include at least 50% cobalt by weight based on the weight of the filler material 140. In a particular embodiment, the filler material 140 includes about 90% to 100% cobalt by weight of the filler material 140.

The fill material 140 may have a different composition than the composition of the seed layer 130. For example, the seed layer 130 may include both silicon and cobalt, while the fill material 140 may include only cobalt. In another example, the seed layer 130 may include a first compound of formula (I) or formula (II), and the filling material 140 may include a second compound of formula (I) or formula (II) different from the first compound of formula (I) or formula (II). The fill material 140 may also have a different grain structure than the seed layer 130. For example, the seed layer 130 may have a grain structure smaller than that of the filling material 140. In one embodiment, a fill material 140 comprising cobalt or nickel is deposited on the component 1204.

In some embodiments, the fill material 140 may be formed by a process such as, but not limited to, CVD, ALD, PVD, electroplating, or electroless plating. In one embodiment, the process method for forming the fill material 140 is different from the process for forming the seed layer 130. Further, the seed layer 130 may be formed conformally, while the fill material 140 may be formed in a non-conformal or bottom-up approach. For example, the seed layer 130 may be formed by an ALD deposition process that forms a conformal layer on the exposed surface of the substrate or barrier/adhesion layer 120, while the fill material 140 may be formed by a PVD process that directionally sputters the fill material 140 onto the surface of the seed layer 130 with a greater deposition rate on planar surfaces as opposed to sidewall surfaces. In another example, the seed layer 130 may be formed by an ALD deposition process that forms a conformal layer on the exposed surface of the substrate or receiving barrier/adhesion layer 120, and the fill material 140 may be formed by an electroplating process that grows the fill material 140 from the surface of the seed layer 130. In yet another example, the seed layer 130 may be formed by a CVD deposition process and the fill material 140 may be formed by a PVD process.

In an embodiment, the seed layer 130 and the fill material 140 are deposited by the same process (e.g., ALD, CVD, or PVD) but with different sets of deposition parameters (such as pressure, deposition rate, temperature, etc.). For example, the seed layer 130 and the fill material 140 may be deposited by a CVD process; however, the set of parameters used in the CVD process for the seed layer 130 (such as deposition pressure and temperature) may be different from the set of parameters used in the CVD process for the fill material 140. In another example, the seed layer 130 and the fill material 140 may be formed by a PVD process, but the seed layer 130 may be formed by a PVD process having a greater distance between a target and a receiving substrate than the PVD process used to form the fill material 140. In another embodiment, the metallic filler material 140 may be formed by a collimated PVD process, while the seed layer 130 may be formed by an uncollimated PVD process. Alternatively, the seed layer may be formed by an ALD process that utilizes a lower deposition rate than the deposition rate of the ALD process used to form the fill material 140, such that the seed layer 130 may be formed more conformally than the fill material 140.

A cyclical technique may be used to deposit the fill material 140 within the openings 114 and 110. One cycle may include one deposition and subsequent anneal of the fill material 140. One cycle of annealing may be performed with parameters (e.g., temperature and/or time) to facilitate reflow of the fill material to improve step coverage. One cycle of deposition operations may be a short deposition for depositing less fill material, requiring several operations to completely fill the via and line openings 114 and 110. In one embodiment, less than five cycles are required to deposit the fill material 140.

In embodiments in which the fill material 140 includes a compound of formula (I) and/or a compound of formula (II), a CVD or ALD process may be used to deposit the fill material 140, and to do so, one or more precursors 170 may be used as part of the CVD/ALD process, according to any of the following: precursors 170, co-reactants, or processes discussed above with reference to seed layer 130 (e.g., precursors 170 for cobalt, nickel, aluminum, manganese, chromium, vanadium, tantalum, niobium, molybdenum, tungsten, or silicon). In such embodiments, the resulting fill material 140 (and thus the metal interconnect 100) may include a trace amount of precursor 170 or co-reactant (e.g., carbon, nitrogen, oxygen, phosphorous, halogen, or hydrogen) as used in accordance with any of the embodiments discussed above with reference to the seed layer 130.

Fig. 1E illustrates assembly 1208 after depositing capping layer 150 over assembly 1206 (fig. 1D). The capping layer 150 may be a capping layer of the filling material 140. Fig. 1E depicts an embodiment in which a capping layer 150 is deposited on the exposed surface of the seed layer 130. Capping layer 150 may be formed by a process such as, but not limited to, CVD, ALD, PVD, electroplating, or electroless plating.

In embodiments in which capping layer 150 comprises a compound of formula (I) and/or a compound of formula (II), a CVD or ALD process may be used to deposit capping layer 150, and to do so, one or more precursors 170 may be used as part of the CVD/ALD process, according to any of the following: precursors 170, co-reactants, or processes discussed above with reference to seed layer 130 (e.g., precursors 170 for cobalt, nickel, aluminum, manganese, chromium, vanadium, tantalum, niobium, molybdenum, tungsten, or silicon). In such embodiments, the resulting capping layer 150 (and thus the metal interconnect 100) may include a trace amount of precursor 170 or co-reactant (e.g., carbon, nitrogen, oxygen, phosphorous, halogen, or hydrogen) used in accordance with any of the embodiments discussed above with reference to the seed layer 130.

Fig. 1F illustrates assembly 1210 after removal of cap layer 150, fill material 140, seed layer 130, and barrier/adhesion layer 120 deposited over top surface 108 of dielectric material 102 of assembly 1208 (fig. 1E) or fill material 140, seed layer 130, and barrier/adhesion layer 120 deposited over top surface 108 of dielectric material 102 of assembly 1206 (fig. 1D). In some embodiments, this removal may be the result of a CMP process. The CMP process may be a timed CMP process configured to stop at the top surface 108 of the line dielectric layer. In another embodiment, the CMP process may rely on the top surface 108 of the line dielectric layer as a stop layer. Because the thickness of the fill material deposited over the top surface of the line dielectric layer is believed to vary, utilizing the top surface of the dielectric layer as a stop layer may be a more reliable method. Alternatively or additionally, an etching process may be used to remove the barrier/adhesion layer, the fill material, the seed layer, or a combination thereof deposited over the top surface of the dielectric layer.

An annealing process may optionally be performed. An annealing process may be performed after the capping layer 150 is deposited. One or more annealing processes may also be performed while depositing the fill material 140, as described herein. Annealing may promote growth of larger grain structures within the fill material, which may reduce resistivity, drive off impurities from poor grain structures, or a combination thereof. Annealing may include the use of forming gases including, but not limited to, nitrogen, hydrogen, argon, or combinations thereof. The annealing may be performed at a temperature less than the thermal budget of the backend structure. For example, the annealing may be performed at a temperature of about 300 ℃ to about 400 ℃. As another example, annealing may be performed at a temperature of: the temperature is above the melting point of the filler material 140 but below the thermal budget of the backend structure.

In one embodiment, the component 1208 of fig. 1E may be subjected to an anneal at a temperature of about 300 ℃ to about 400 ℃ for about 1 minute to about 1 hour, followed by CMP, which results in the metal interconnect 100 depicted in fig. 1F. Without wishing to be bound by any particular theory, it is believed that annealing may drive mixing the compounds of formulas (I) and/or (II) of the seed layer 130 into the fully filled features, as depicted in fig. 1F. Without wishing to be bound by any particular theory, it is believed that the film of the compound of formula (I) and/or (II) may passivate the top surface of the trench, thereby preventing or reducing the likelihood of corrosion.

In an embodiment, the seed layer and the fill material comprise a compound of formula (I) and/or formula (II). For example, fig. 2 depicts an assembly 200 into which a barrier/adhesion layer 120, a seed layer 130 comprising a compound of formula (I) and/or formula (II), a fill material 140 comprising a compound of formula (I) and/or formula (II), and a capping layer 150 of cobalt, nickel, or a combination thereof, have been deposited. Filler material 140 and capping layer 150 comprise different materials in the embodiment depicted at fig. 2. The seed layer 130 and the fill material 140 may include different compounds of formulas (I) and/or (II), or different combinations thereof. For example, the seed layer 130 and the filling material 140 may include [1] a compound of formula (I), [2] a compound of formula (II), or [3] a combination thereof. The seed layer 130 may include a compound of formula (I) and the fill material 230 may include a compound of formula (II), or vice versa. The assembly 200 of fig. 2 may include the dielectric material 102 deposited on the substrate 106, and may include one or more of the additional features depicted in fig. 1A. The assembly 200 of fig. 2 may be subjected to annealing, which may drive the mixing of the compounds of formula (I) and/or (II). The assembly may then be polished, such as by CMP. The polishing may remove the capping layer and at least a portion of the barrier and/or adhesion layer 120, the seed layer 130, and/or the fill material 140 deposited over the top surface 108 of the dielectric material 102. Without wishing to be bound by any particular theory, it is believed that the film of the compound of formula (I) and/or (II) may passivate the top surface of the trench, thereby preventing or reducing the likelihood of corrosion. In embodiments where the material comprises a compound of formula (I) and/or a compound of formula (II), a CVD or ALD process may be used to deposit the material, and to do so, one or more precursors 170 may be used as part of the CVD/ALD process, according to any of the following: precursors 170, co-reactants, or processes discussed above with reference to seed layer 130 (e.g., precursors 170 for cobalt, nickel, aluminum, manganese, chromium, vanadium, tantalum, niobium, molybdenum, tungsten, or silicon). In such embodiments, the resulting material (and thus the metal interconnect 100) may include a trace amount of the precursor 170 or co-reactant (e.g., carbon, nitrogen, oxygen, phosphorous, halogen, or hydrogen) used in accordance with any of the embodiments discussed above with reference to the seed layer 130.

In an embodiment, the capping layer comprises a compound of formula (I) and/or formula (II). For example, fig. 3 depicts an assembly 300 into which is a barrier/adhesion layer 120, a seed layer 130 of nickel, cobalt, or a combination thereof, a fill material 140 of cobalt, nickel, or a combination thereof, and a capping layer 150 in which a compound of formula (I) and/or formula (II) is present. Filler material 140 and capping layer 150 comprise different materials in the embodiment depicted at fig. 3. The assembly 300 of fig. 3 may include the dielectric material 102 deposited on the substrate 106, and may include one or more of the additional features depicted in fig. 1A. The assembly 300 of fig. 3 may be subjected to an anneal, which may drive the mixing of compounds of formula (I) and/or (II) into at least one of the fill material 140 or the seed layer 130. The structure may then be polished, such as by CMP. The polishing may remove the capping layer and at least a portion of the barrier/adhesion layer 120, the seed layer 130, and/or the fill material 140 deposited over the top surface 108 of the dielectric material 102. Without wishing to be bound by any particular theory, it is believed that the film of the compound of formula (I) and/or (II) may passivate the top surface of the trench, thereby preventing or reducing the likelihood of corrosion. In embodiments where the material comprises a compound of formula (I) and/or a compound of formula (II), a CVD or ALD process may be used to deposit the material, and to do so, one or more precursors 170 may be used as part of the CVD/ALD process, according to any of the following: precursors 170, co-reactants, or processes discussed above with reference to seed layer 130 (e.g., precursors 170 for cobalt, nickel, aluminum, manganese, chromium, vanadium, tantalum, niobium, molybdenum, tungsten, or silicon). In such embodiments, the resulting material (and thus the metal interconnect 100) may include a trace amount of the precursor 170 or co-reactant (e.g., carbon, nitrogen, oxygen, phosphorous, halogen, or hydrogen) used in accordance with any of the embodiments discussed above with reference to the seed layer 130.

In an embodiment, a cap comprising a compound of formula (I) and/or (II) is applied to one of the components disclosed herein. For example, fig. 4 depicts an embodiment of an assembly 400, the assembly 400 including a barrier/adhesion layer 120, a seed layer 130 of cobalt, nickel, or a combination thereof, a fill material 140 of cobalt, nickel, or a combination thereof, and a cap 440 comprising a compound of formula (I) and/or (II) deposited on a top surface 450 of the fill material 140. The cap 440 may correspond to the dimensions of the top surface 450 of the fill material 140, covering all or a majority of the top surface 450 of the fill material 140, as depicted at fig. 4. The cap 440 may also cover at least a portion of the exposed surface of the seed layer 130, the barrier/adhesion layer 120, or a combination thereof. After depositing the filler material 140 in the assembly 400, a cap 440 may be applied. After the CMP process is performed, a cap 440 may be applied. The caps may be deposited using any known technique, including those described herein (such as ALD, CVD), or electroless plating. In some embodiments, cap 440 is a "selective" cap 440 that is deposited on exposed surfaces of at least one of fill material 140, seed layer 130, and barrier/adhesion layer 120, or a combination thereof, but "selective" cap 440 is not deposited on dielectric material 102. In other embodiments, the cap 440 is a "non-selective" cap 440 applied to the top surface of the component by blanket deposition in the following manner: the approach may deposit a portion of a "non-selective" cap 440 on the dielectric material 102. After its deposition, the "non-selective" cap 440 may be annealed and then removed by polishing. The "non-selective" cap 440 can include compounds of formula (I) and/or (II). The "non-selective" cap 440 may also include one or more elements (such as elements from which the variables "Q" and "Z" herein may be selected), and upon annealing, the one or more elements may be combined with at least one of the fill material 140, the seed layer 130, or the barrier/adhesion layer 120. Annealing of the "non-selective" cap 440 may thus result in the formation of alloys, including but not limited to alloys according to formulas (I) and/or (II). In embodiments in which cap 440 includes a compound of formula (I) and/or a compound of formula (II), a CVD or ALD process may be used to deposit cap 440, and to do so, one or more precursors 170 may be used as part of the CVD/ALD process, according to any of the following: precursors 170, co-reactants, or processes discussed above with reference to seed layer 130 (e.g., precursors 170 for cobalt, nickel, aluminum, manganese, chromium, vanadium, tantalum, niobium, molybdenum, tungsten, or silicon). In such embodiments, the resulting cap 440 (and thus the metal interconnect 100) may include traces of the precursor 170 or co-reactant (e.g., carbon, nitrogen, oxygen, phosphorous, halogen, or hydrogen) used in accordance with any of the embodiments discussed above with reference to the seed layer 130.

Fig. 5 is a flow chart 500 depicting an embodiment of a method of forming a metal structure, such as those depicted at fig. 1, 2, 3, and 4, or any of the others disclosed herein. At 510, an initial component is provided. At 520, a barrier and/or adhesion layer is deposited on the initial assembly. In other embodiments, the methods provided herein do not include depositing a barrier and/or adhesion layer on the initial assembly. At 530, a seed layer is deposited on the barrier and/or adhesion layer. At 540, a fill material is deposited over the seed layer. At 550, a capping layer or cap is deposited over the fill material, wherein one or more of the seed layer, the fill material, the capping layer, and/or the cap are formed using a CVD/ALD process and any of the precursors disclosed herein. At 560, an optional anneal of the metal structure is performed. At 570, optional polishing of the metal structure is performed, such as by CMP. At 580, an optional deposition of a cap is performed, which may be performed with the overcoat layer previously deposited on the assembly and removed by polishing.

The metal interconnect 100 disclosed herein may be included in any suitable electronic component. Fig. 6-10 illustrate various examples of devices that may include any of the metal interconnects 100 disclosed herein.

Fig. 6 is a top view of a wafer 1500 and a die 1502, which wafer 1500 and die 1502 may include one or more metal interconnects 100, or may be included in an IC package that includes one or more metal interconnects 100 according to any of the embodiments disclosed herein (e.g., as discussed below with reference to fig. 8). Wafer 1500 may be composed of semiconductor materials and may include one or more dies 1502, the dies 1502 having IC structures formed on a surface of wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product that includes any suitable IC. After fabrication of the semiconductor product is complete, the wafer 1500 may be subjected to a singulation process in which the dies 1502 are separated from one another to provide discrete "chips" of the semiconductor product. Die 1502 may include one or more metal interconnects 100 (e.g., as discussed below with reference to fig. 7), one or more transistors (e.g., some of transistors 1640 of fig. 7 discussed below), and/or supporting circuitry for routing electrical signals to the transistors, as well as any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., Random Access Memory (RAM) devices, such as static RAM (sram) devices, magnetic RAM (mram) devices, resistive RAM (rram) devices, conductive-bridged RAM (cbram) devices, etc.), logic devices (e.g., and, or, nand, or nor gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed of a plurality of memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of fig. 10) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

Fig. 7 is a side cross-sectional view of an IC device 1600, which IC device 1600 may include one or more metal interconnects 100, or may be included in an IC package that includes one or more metal interconnects 100 according to any of the embodiments disclosed herein (e.g., as discussed below with reference to fig. 8). One or more of the IC devices 1600 may be included in one or more dies 1502 (fig. 6). IC device 1600 may be formed on a substrate 1602 (e.g., wafer 1500 of fig. 6) and may be included in a die (e.g., die 1502 of fig. 6). Substrate 1602 may be a semiconductor substrate that is composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). Substrate 1602 may comprise a crystalline substrate formed, for example, using bulk silicon (bulk silicon) or silicon-on-insulator (SOI) substructures. In some embodiments, substrate 1602 may be formed by using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as groups II-VI, III-V, or IV may also be used to form substrate 1602. Although a few examples of materials from which the substrate 1602 may be formed are described here, any material that may serve as a foundation for the IC device 1600 may be used. Substrate 1602 may be a portion of a singulated die (e.g., die 1502 of fig. 6) or a wafer (e.g., wafer 1500 of fig. 6).

The IC device 1600 can include one or more device layers 1604 disposed on a substrate 1602. The device layer 1604 may include features of one or more transistors 1640, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 for controlling current flow in a transistor 1640 between the S/D regions 1620, and one or more S/D contacts 1624 for routing electrical signals to/from the S/D regions 1620. The transistor 1640 may include additional features that are not depicted for the sake of clarity, such as device isolation regions, gate contacts, etc. The transistors 1640 are not limited to the types and configurations depicted in fig. 7, and may comprise a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. The planar transistor may include a Bipolar Junction Transistor (BJT), a Heterojunction Bipolar Transistor (HBT), or a High Electron Mobility Transistor (HEMT). Non-planar transistors may include FinFET transistors, such as double-gate or triple-gate transistors, as well as wrap-around or fully-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor 1640 may include a gate 1622, the gate 1622 being formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may comprise a layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or high-k dielectric materials. The high-k dielectric material may include elements such as: hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when using high-k materials.

The gate electrode may be formed on a gate dielectric and may include at least one p-type workfunction metal or n-type workfunction metal, depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode can include a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one of the metal layers is a fill metal layer. Additional metal layers may be included for other purposes, such as barrier layers. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

In some embodiments, when considered as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure comprising a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the substrate top surface. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

In some embodiments, a pair of sidewall spacers (spacers) may be formed on opposite sides of the gate stack to enclose the gate stack. The sidewall spacers may be formed of materials such as: silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

The S/D region 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. For example, the S/D region 1620 may be formed using an implantation/diffusion process or an etching/deposition process. In a previous process, a dopant such as boron, aluminum, antimony, phosphorous, or arsenic may be ion implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse further into the substrate 1602 may follow the ion implantation process. In a later process, the substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant, such as boron, arsenic, or phosphorous. In some embodiments, S/D regions 1620 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further embodiments, one or more layers of metals and/or metal alloys may be used to form S/D regions 1620.

In some embodiments, the gate 1622 of the transistor 1640 may be formed using the techniques disclosed herein with reference to the metal interconnect 100. For example, gate 1622 can include a compound according to formula (I) and/or formula (II).

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from devices (e.g., transistors 1640) of device layer 1604 through one or more interconnect layers (illustrated in fig. 7 as interconnect layer 1606-1610). For example, conductive features of device layer 1604, such as gate 1622 and S/D contact 1624, may be electrically coupled with interconnect structure 1628 of interconnect layer 1606 and 1610. The one or more interconnect layers 1606-1610 may form a metallization stack (which may also be referred to as an "ILD stack") 1619 of the IC device 1600. In some embodiments, interconnect structure 1628 may take the form of any of the metal interconnects 100 disclosed herein. One or more metal interconnects 100 in metallization stack 1619 may be coupled to any suitable ones of the devices in device layer 1604 and/or to one or more of conductive contacts 1636 (discussed below).

Interconnect structure 1628 may be arranged within interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structure 1628 depicted in fig. 7). Although a particular number of interconnect layers 1606-1610 are depicted in fig. 7, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, interconnect structure 1628 may include wires 1628a and/or vias 1628b that are filled with a conductive material, such as a metal. The wires 1628a may be arranged to route electrical signals in a direction in a plane substantially parallel to the following surface of the substrate 1602: a device layer 1604 is formed on the surface of substrate 1602. For example, line 1628a may route electrical signals in a direction into and out of the page from the perspective of fig. 7. The vias 1628b may be arranged to route electrical signals in a direction of a plane substantially perpendicular to the following surface of the substrate 1602: a device layer 1604 is formed on the surface of substrate 1602. In some embodiments, vias 1628b may electrically couple lines 1628a of different interconnect layers 1606-1610 together.

Interconnect layer 1606-1610 may comprise a dielectric material 1626 disposed between interconnect structures 1628, as shown in fig. 7. In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different ones of the interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

A first interconnect layer 1606 may be formed above the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The wires 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., S/D contacts 1624) of the device layer 1604.

A second interconnect layer 1608 may be formed over the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although lines 1628a and vias 1628b are structurally delineated within each interconnect layer (e.g., within second interconnect layer 1608) with a line for clarity reasons, lines 1628a and vias 1628b may be contiguous in some embodiments structurally and/or materially (e.g., filled simultaneously during a dual damascene process).

Third interconnect layer 1610 (and additional interconnect layers as desired) may be successively formed on second interconnect layer 1608 according to similar techniques and configurations described in connection with second interconnect layer 1608 or first interconnect layer 1606. In some embodiments, interconnect layers "higher up" (i.e., further from the device layer 1604) in the metallization stack 1619 in the IC device 1600 may be thicker.

IC device 1600 may include solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layer 1606-1610. In fig. 7, the conductive contacts 1636 are illustrated as taking the form of bond pads. Conductive contact 1636 may be electrically coupled with interconnect structure 1628 and configured to route electrical signals of transistor(s) 1640 to other external devices. For example, a solder joint may be formed on the one or more conductive contacts 1636 to mechanically and/or electrically couple the chip including the IC device 1600 with another component (e.g., a circuit board). IC device 1600 may include additional or alternative structures to route electrical signals from interconnect layer 1606 and 1610; for example, the conductive contacts 1636 may include other similar features (e.g., posts) that route electrical signals to external components.

Fig. 8 is a side cross-sectional view of an example IC package 1650 that may include one or more metal interconnects 100. In some embodiments, the IC package 1650 may be a System In Package (SiP).

The package substrate 1652 may be formed of a dielectric material (e.g., ceramic, reinforced film, epoxy film with filler particles therein, etc.) and may have conductive vias extending through the dielectric material: the dielectric material is between face 1672 and face 1674, or between different locations on face 1672, and/or between different locations on face 1674. These conductive paths may take the form of any of the interconnects 1628 discussed above with reference to fig. 7. In some embodiments, the conductive path through the package substrate 1652 (and/or through the interposer 1657) may include any of the metal interconnects 100 disclosed herein; in other embodiments, the conductive paths through the package substrate 1652 (and/or through the interposer 1657) may comprise other materials and/or structures.

The package substrate 1652 may include conductive contacts 1663, the conductive contacts 1663 being coupled to conductive pathways 1662 through the package substrate 1652, thereby allowing circuits within the die 1656 and/or the interposer 1657 to be electrically coupled to different ones of the conductive contacts 1664 (or to other devices included in the package substrate 1652, not shown).

The IC package 1650 may include an interposer 1657, the interposer 1657 being coupled to a package substrate 1652 via conductive contacts 1661 of the interposer 1657, first level interconnects 1665, and conductive contacts 1663 of the package substrate 1652. The first level interconnects 1665 illustrated in fig. 8 are solder bumps, but any suitable first level interconnect 1665 may be used. In some embodiments, no interposer 1657 may be included in the IC package 1650; alternatively, die 1656 may be directly coupled to conductive contacts 1663 at face 1672 by first level interconnects 1665.

The IC package 1650 may include one or more dies 1656, the dies 1656 being coupled to interposers 1657 via conductive contacts 1654 of the dies 1656, first level interconnects 1658, and conductive contacts 1660 of interposers 1657. The conductive contacts 1660 may be coupled to conductive paths (not shown) through the interposer 1657, thereby allowing circuitry within the die 1656 to be electrically coupled to different ones of the conductive contacts 1661 (or to other devices included in the interposer 1657, not shown). The first level interconnect 1658 illustrated in fig. 8 is a solder bump, but any suitable first level interconnect 1658 may be used. As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an interface between different components; the conductive contacts may be recessed in, flush with, or extend away from the surface of the component, and may take any suitable form (e.g., conductive pads or slots).

In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first level interconnects 1665, and a molding compound 1668 may be disposed around the die 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the molding compound 1668. Exemplary materials that can be used for the underfill 1666 and the molding compound 1668 are, for example, suitable epoxy molding materials. The second level interconnect 1670 may be coupled to a conductive contact 1664. The second level interconnects 1670 illustrated in fig. 8 are solder balls (e.g., for a ball grid array arrangement), but any suitable second level interconnects 16770 may be used (e.g., pins in a pin grid array arrangement or pads in a land grid array arrangement). The second level interconnect 1670 may be used to couple the IC package 1650 to another component, such as a circuit board (e.g., motherboard), interposer, or another IC package, as is known in the art and as discussed below with reference to fig. 9.

The die 1656 may take the form of any of the embodiments of the die 1502 discussed herein (e.g., may include any of the embodiments of the IC device 1600). In embodiments where IC package 1650 includes multiple dies 1656, IC package 1650 may be referred to as a multi-chip package (MCP). The die 1656 may include circuitry for performing any desired functionality. For example, one or more of the dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of the dies 1656 may be memory dies (e.g., high bandwidth memory). In some embodiments, die 1656 may include one or more metal interconnects 100 (e.g., as discussed above with reference to fig. 6 and 7); in other embodiments, die 1656 may not include any metal interconnects 100.

Although the IC package 1650 illustrated in fig. 8 is a flip chip package, other package architectures may be used. For example, the IC package 1650 may be a Ball Grid Array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 1650 may be a Wafer Level Chip Scale Package (WLCSP) or a panel Fan Out (FO) package. Although two dies 1656 are illustrated in the IC package 1650 of fig. 8, the IC package 1650 may include any desired number of dies 1656. The IC package 1650 may include additional passive components, such as surface mounted resistors, capacitors, and inductors, disposed on the first face 1672 or the second face 1674 of the package substrate 1652 or on either face of the interposer 1657. More generally, the IC package 1650 may include any other active or passive component known in the art.

Fig. 9 is a side cross-sectional view of an IC device assembly 1700 that may include one or more IC packages or other electronic components (e.g., dies) that include one or more metal interconnects 100 in accordance with any of the embodiments disclosed herein. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). IC device assembly 1700 includes components disposed on a first side 1740 of circuit board 1702 and an opposite second side 1742 of circuit board 1702; generally, components may be disposed on one or both of faces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any of the embodiments of the IC package 1650 discussed above with reference to fig. 8 (e.g., one or more metal interconnects 100 may be included in the package substrate 1652 or in the die 1656).

In some embodiments, the circuit board 1702 may be a Printed Circuit Board (PCB) that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed with a desired circuit pattern to route electrical signals between components coupled to the circuit board 1702 (optionally in combination with other metal layers). In other embodiments, the circuit board 1702 may be a non-PCB substrate.

The IC device assembly 1700 illustrated in fig. 9 includes a package-on-interposer structure 1736, which package-on-interposer structure 1736 is coupled to a first side 1740 of the circuit board 1702 by a coupling member 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in fig. 9), male and female portions of a socket, adhesive, underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 1736 may include an IC package 1720, the IC package 1720 coupled to a package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the form discussed above with reference to the coupling component 1716. Although a single IC package 1720 is shown in fig. 9, multiple IC packages may be coupled to the package insert 1704; indeed, additional interposers may be coupled to package interposer 1704. The package insert 1704 may provide an intervening substrate for bridging the circuit board 1702 and the IC package 1720. IC package 1720 may be or include, for example, a die (die 1502 of fig. 6), an IC device (e.g., IC device 1600 of fig. 7), or any other suitable component. In general, the package insert 1704 may spread the connections out to a wider pitch or reroute the connections to different connections. For example, the package insert 1704 may couple the IC package 1720 (e.g., a die) to a set of BGA conductive contacts of the coupling component 1716 for coupling to the circuit board 1702. In the embodiment illustrated in fig. 9, IC package 1720 and circuit board 1702 are attached to opposite sides of package insert 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the package insert 1704. In some embodiments, three or more components may be interconnected by package insert 1704.

In some embodiments, the package insert 1704 may be formed as a PCB including a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the package insert 1704 may be formed from an epoxy, a fiberglass reinforced epoxy, an epoxy with inorganic fillers, a ceramic material, or a polymeric material (such as polyimide). In some embodiments, the package insert 1704 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The package insert 1704 may include metal interconnects 1708 and vias 1710, including but not limited to Through Silicon Vias (TSVs) 1706. The package insert 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical system (MEMS) devices may also be formed on the package insert 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.

IC device assembly 1700 may include an IC package 1724, the IC package 1724 coupled to a first side 1740 of circuit board 1702 via coupling members 1722. The coupling component 1722 may take the form of any of the embodiments discussed above with reference to the coupling component 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.

The IC device assembly 1700 illustrated in fig. 9 includes a package-on-package structure 1734, which 1734 is coupled to a second side 1742 of the circuit board 1702 by a coupling member 1728. Package-on-package structure 1734 may include IC package 1726 and IC package 1732, which are coupled together by coupling member 1730 such that IC package 1726 is disposed between circuit board 1702 and IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. Package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

Fig. 10 is a block diagram of an example electrical device 1800 that may include one or more metal interconnects 100 in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of electrical device 1800 may include one or more of the following: the IC device assembly 1700, IC package 1650, IC device 1600, or die 1502 disclosed herein. A number of components are illustrated in fig. 10 as being included in electrical device 1800, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.

Additionally, in various embodiments, electrical device 1800 may not include one or more of the components illustrated in fig. 10, but electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

The electrical device 1800 can include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Central Processing Units (CPUs), Graphics Processing Units (GPUs), cryptographic processors (special purpose processors that perform cryptographic algorithms in hardware), server processors, or any other suitable processing device. The electrical device 1800 can include memory 1804, which memory 1804 can itself comprise one or more memory devices, such as volatile memory (e.g., Dynamic Random Access Memory (DRAM)), non-volatile memory (e.g., Read Only Memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin-transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, electrical device 1800 can include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for communicating data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data by using modulated electromagnetic radiation (which passes through a non-solid medium). The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (the IEEE 802.11 family), IEEE802.16 standards (e.g., IEEE802.16-2005 amendment), Long Term Evolution (LTE) project, along with any amendments, updates, and/or revisions (e.g., LTE-advanced project, Ultra Mobile Broadband (UMB) project (also referred to as "3 GPP 2"), etc.). IEEE802.16 compliant Broadband Wireless Access (BWA) networks, commonly referred to as WiMAX networks, represent an acronym for Worldwide Interoperability for Microwave Access (Worldwide Interoperability for Microwave Access), which is an authentication mark for products that pass compliance and Interoperability tests for the IEEE802.16 standard. The communication chip 1812 may operate in accordance with a global system for mobile communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), optimized evolution data (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 1812 may operate according to other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communication and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For example, the first communication chip 1812 may be dedicated for closer range wireless communication, such as Wi-Fi or bluetooth, and the second communication chip 1812 may be dedicated for longer range wireless communication, such as Global Positioning System (GPS), ‎ EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated for wireless communication and the second communication chip 1812 may be dedicated for wired communication.

The electrical device 1800 may include battery/power circuitry 1814. Battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of electrical device 1800 to an energy source (e.g., AC line power) separate from electrical device 1800.

The electrical device 1800 can include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a Liquid Crystal Display (LCD), a light emitting diode display, or a flat panel display.

The electrical device 1800 can include an audio output device 1808 (or corresponding interface circuitry, as discussed above). Audio output devices 1808 may include any device that generates an audible indicator, such as a speaker, headphones, or ear buds.

The electrical device 1800 can include an audio input device 1824 (or corresponding interface circuitry, as discussed above). Audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). GPS device 1818 may communicate with a satellite-based system and may receive the location of electrical device 1800, as is known in the art.

The electrical device 1800 can include other output devices 1810 (or corresponding interface circuits, as discussed above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter to provide information to other devices, or an additional storage device.

The electrical device 1800 can include other input devices 1820 (or corresponding interface circuits, as discussed above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device, such as a mouse, a stylus, a touch pad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a Radio Frequency Identification (RFID) reader.

The electrical device 1800 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, smart phone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, Personal Digital Assistant (PDA), ultramobile personal computer, etc.), desktop electrical device, server device, or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some embodiments, electrical device 1800 can be any other electronic device that processes data.

The following paragraphs provide examples of different ones of the embodiments disclosed herein.

Example 1 is a metal structure comprising: a or B; and one or more of carbon, nitrogen, oxygen, phosphorus, halogen, or hydrogen; wherein A comprises: b weight percent Co; q weight percent Q; and Z weight percent Z; wherein the sum of b, q and z equals 100%; b is between 50% and example 99.99%; q is between example 0.01% and 50%; z is between 0% and example 49.9%; when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; and Z is selected from Mo or W; wherein B comprises: d weight percent Ni; e weight percent of X; and f weight percent G; wherein the sum of d, e and f equals 100%; d is between 50% and 100%, e is between 0% and 50%, f is between 0% and example 49.99%; when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

Example 2 includes the subject matter of example 1, and further specifies that the metal structure includes a.

Example 3 includes the subject matter of example 1, and further specifies that the metal structure includes B.

Example 4 includes the subject matter of any of examples 1-3, and further specifies that the metal structure includes carbon.

Example 5 includes the subject matter of any of examples 1-3, and further specifies that the metal structure includes nitrogen.

Example 6 includes the subject matter of any of examples 1-3, and further specifies that the metal structure includes phosphorus.

Example 7 includes the subject matter of any of examples 1-3, and further specifies that the metal structure includes a halogen.

Example 8 includes the subject matter of any of examples 1-3, and further specifies that the metal structure includes hydrogen.

Example 9 includes the subject matter of any of examples 1-8, and further specifies that the metal structure is a transistor gate.

Example 10 includes the subject matter of any of examples 1-8, and further specifies that the metal structure is a metal interconnect.

Example 11 includes the subject matter of any of examples 1-10, and further specifies that the metal structure is included in an Integrated Circuit (IC) die.

Example 12 includes the subject matter of any of examples 1-10, and further specifies that the metal structure is included in a package substrate.

Example 13 includes the subject matter of any of examples 1-12, and further specifies that the metal structure includes a seed layer, a fill material, or a cap, and a or B is present in at least one of the seed layer, the fill material, or the cap.

Example 14 is an Integrated Circuit (IC) die, comprising: a metal interconnect, the metal interconnect comprising: one or more of carbon, nitrogen, oxygen, phosphorus, halogen, or hydrogen; and a compound according to formula (I) or formula (II) -Co_bQ_qZ_z(chemical formula (I)), Ni_dX_eG_f(formula (II)); wherein b, q and z are weight percentages based on the total weight of the compound according to formula (I), b is between 50% and example 99.99%, q is between example 0.01% and 50%, and z is between 0% and example 49.9%; wherein when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; wherein when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; wherein Z is selected from Mo or W; and wherein d, e and f are weight percentages based on the total weight of the compound according to formula (II), d is between 50% and 100%, e is between 0% and 50%, fBetween 0% and example 49.99%; wherein when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; wherein when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and wherein G is selected from Mo or W.

Example 15 includes the subject matter of example 14, and further specifies that the metal interconnect includes a compound according to formula (I).

Example 16 includes the subject matter of example 14, and further specifies that the metal interconnect includes a compound according to formula (II).

Example 17 includes the subject matter of any one of examples 14-16, and further specifies that the metal interconnect comprises carbon.

Example 18 includes the subject matter of any of examples 14-16, and further specifies that the metal interconnect comprises nitrogen.

Example 19 includes the subject matter of any of examples 14-16, and further specifies that the metal interconnect comprises phosphorus.

Example 20 includes the subject matter of any of examples 14-16, and further specifies that the metal interconnect comprises a halogen.

Example 21 includes the subject matter of any one of examples 14-16, and further specifies that the metal interconnect includes hydrogen.

Example 22 includes the subject matter of any one of examples 14-21, and further includes: one or more transistors.

Example 23 includes the subject matter of any one of examples 14-22, and further includes: one or more conductive pads at an outer face of the IC die.

Example 24 includes the subject matter of any of examples 14-23, and further specifies that the metal interconnect includes a seed layer, a fill material, or a cap, and that the compound according to formula (I) or formula (II) is present in at least one of the seed layer, the fill material, or the cap.

Example 25 is a method of forming a metal structure, comprising: providing an initial structure; and forming a metal on the initial structure by Chemical Vapor Deposition (CVD); wherein the precursors used during CVD comprise one or more of carbon, nitrogen, oxygen, phosphorus, halogen, or hydrogen; wherein the metal comprises A or B; wherein A comprises: b weight percent Co; q weight percent Q; and Z weight percent Z; wherein the sum of b, q and z equals 100%; b is between 50% and example 99.99%; q is between example 0.01% and 50%; z is between 0% and example 49.9%; when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; and Z is selected from Mo or W; wherein B comprises: d weight percent Ni; e weight percent of X; and f weight percent G; wherein the sum of d, e and f equals 100%; d is between 50% and 100%, e is between 0% and 50%, f is between 0% and example 49.99%; when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

Example 26 includes the subject matter of example 25, and further includes: an initial structure is formed.

Example 27 includes the subject matter of example 26, and further specifies that forming the initial structure comprises depositing a barrier and/or adhesion layer on the damascene or dual damascene structure.

Example 28 includes the subject matter of any of examples 25-27, and further specifies that the metal is a seed layer.

Example 29 includes the subject matter of any of examples 25-27, and further specifies that the metal is a filler material.

Example 30 includes the subject matter of any of examples 25-27, and further specifies that the metal is a cap.

Example 31 includes the subject matter of any of examples 25-30, and further specifies that forming the metal on the initial structure by CVD includes performing Atomic Layer Deposition (ALD).

Example 32 includes the subject matter of any of examples 25-31, and further specifies that the initial structure comprises: a dielectric layer deposited on a substrate, the substrate comprising a conductive region; and an opening in the dielectric layer, the opening exposing the conductive region of the substrate, the opening having a lower portion and an upper portion, wherein the upper portion is wider than the lower portion.

Example 33 is a computing device, comprising: an Integrated Circuit (IC) package including an IC die coupled to a package substrate; a circuit board, wherein the IC package is coupled to the circuit board; wherein the computing device comprises a metal structure comprising A or B; wherein the metal structure further comprises a trace amount of a Chemical Vapor Deposition (CVD) precursor material; wherein A comprises: b weight percent Co; q weight percent Q; and Z weight percent Z; wherein the sum of b, q and z equals 100%; b is between 50% and example 99.99%; q is between example 0.01% and 50%; z is between 0% and example 49.9%; when z is 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Mo, Nb, Ta, W or Zr; when z is other than 0%, Q is selected from Ni, Al, Mn, Si, Cr, V, Nb or Ta; and Z is selected from Mo or W; wherein B comprises: d weight percent Ni; e weight percent of X; and f weight percent G; wherein the sum of d, e and f equals 100%; d is between 50% and 100%, e is between 0% and 50%, f is between 0% and example 49.99%; when f is 0%, X is selected from Co, Al, Mn, Si, Cr, V, Mo, Nb, Ta or W; when f is not 0%, X is selected from Co, Al, Mn, Si, Cr, V, Nb or Ta; and G is selected from Mo or W.

Example 34 includes the subject matter of example 33, and further specifies that the trace amount of CVD precursor material includes one or more of carbon, nitrogen, oxygen, phosphorus, a halogen, or hydrogen.

Example 35 includes the subject matter of any of examples 33-34, and further specifies that the metal structure is included in an IC die.

Example 36 includes the subject matter of any of examples 33-34, and further specifies that the metal structure is included in a package substrate.

Example 37 includes the subject matter of any of examples 33-36, and further specifies that the metal structure is a metal interconnect.

Example 38 includes the subject matter of any of examples 33-37, and further specifies that the computing device is a laptop computer, a handheld computing device, or a server.

Example 39 includes the subject matter of any of examples 33-38, and further comprising: a display coupled to the circuit board.

Example 40 includes the subject matter of any of examples 33-39, and further comprising: an antenna coupled to the circuit board.

Example 41 is a material comprising any of the precursor materials disclosed herein.

Example 42 is a method of forming a metal structure, comprising forming a metal on an initial structure by chemical vapor deposition using any of the precursor materials disclosed herein.

Example 43 is a metal formed using chemical vapor deposition and any of the precursor materials disclosed herein.