阅读说明：本技术 一种用于铜互联电路中的扩散阻挡层 (Diffusion barrier layer for copper interconnection circuit ) 是由 马旭梁 任义 于 2019-09-27 设计创作，主要内容包括：一种用于铜互联电路中的扩散阻挡层材料及其制备方法,本发明涉及一种新型有机材料的成分设计并对新型有机材料进行初选及优选。本发明主要解决目前传统的Ta/TaN扩散阻挡层的耐温性及覆盖性问题,新型有机扩散阻挡层的覆盖率远高于Ta/TaN材料。本有机物由C、H、O、N、Si五种元素组成。本发明以Si(100)为基体,通过有机物自组装生长的方法制得。本材料的力学性能和电学性能良好。本发明制备的材料可用于集成电路中阻止铜的硅相互扩散。(The invention discloses a diffusion barrier layer material for a copper interconnection circuit and a preparation method thereof, and relates to component design of a novel organic material and primary selection and optimization of the novel organic material. The invention mainly solves the problems of temperature resistance and covering property of the traditional Ta/TaN diffusion barrier layer at present, and the covering rate of the novel organic diffusion barrier layer is far higher than that of a Ta/TaN material. The organic matter consists of C, H, O, N, Si kinds of elements. The invention takes Si (100) as a matrix and is prepared by a method of organic matter self-assembly growth. The material has good mechanical property and electrical property. The material prepared by the invention can be used for preventing the silicon interdiffusion of copper in integrated circuits.)

1. A diffusion barrier material used in a copper interconnection circuit is characterized in that an organic matter is composed of C, H, O, N, Si elements, wherein the content of C is 40%, the content of H is 9.4%, the content of O is 26.7%, the content of N is 8.2%, and the content of Si is 15.7%.

2. The novel organic material according to claim 1, wherein the novel organic material is prepared by self-assembly growth of organic materials using Si (100) as a matrix, and the assembly conditions are optimized by orthogonal experiments.

Technical Field

The invention relates to a composition design of a novel organic material.

Background

The design concept of the main chain of the diffusion barrier layer and the selection of terminal groups play an important role in further realizing the miniaturization of the device. Copper, due to its higher electromigration resistance and superior electrical conductivity properties, is the metal of choice for creating multilevel interconnect structures in very large scale integrated circuits. Since copper has a high diffusion coefficient in a low dielectric constant medium such as silicon, a diffusion barrier layer film needs to be prepared on a silicon substrate to prevent copper from diffusing into an interlayer medium, so that device failure caused by increased leakage current caused by the diffusion barrier layer film is avoided.

The traditional inorganic diffusion barrier layer is a Ta/TaN double-layer structure, and the barrier layer has the following advantages: tantalum is a transition metal, whose melting point is very high; the tantalum has good thermal stability and cannot be mutually dissolved with the copper under the high-temperature condition; tantalum reacts with silicon at 650 ℃ to form compounds, mainly TaSi₂. However, with the rapid development of integrated circuits, the size requirement of devices is smaller and smaller, and the traditional Ta/TaN-diffusion barriers have also met with several technical challenges. Particularly in the trench with a large aspect ratio, the Ta diffusion barrier layer coverage is reduced, so that copper cannot completely cover the trench, a hole is formed, and further the resistance of the wire is increased, thereby causing open circuit. To address such issues, many transition metals are selected as alternative materials, such as Pd, Ir, Ru, Co, Mo, and the like. However, these metals are relatively rare and expensive, and are not suitable for use in the actual large scale integrated circuit process. Furthermore, according to the development route requirements of the international semiconductor technology, the diffusion barrier layer thickness of the first layer metal wiring is required to be 1.9nm in 2015, and the thickness is reduced year by year. New materials and processes must be sought for improvements to achieve reduced barrier layer thickness and improved device lifetime. Considering that the traditional diffusion barrier materials are all inorganic, the research direction is shifted to organic materials, and an organic thin film which can be used as a diffusion barrier layer is searched.

Through the research in the last 15 years, organic nano molecular layers (MNLs) are used as novel copper diffusion barrier layers, and show specific advantages and potentials. Self-assembled monolayers (SAM) have three parts: head group, alkyl chain and terminal functional group. Each portion can be customized to achieve a particular layer surface chemistry, structure, and thickness. In particular, in selecting suitable SAM molecules as diffusion barriers, several structural factors should be considered. For example, the selectivity and viscous strength between the SAM capping groups and the substrate affect the packing density and thermal stability of the film; the length of the SAM chain influences the packing density and the arrangement sequence of the film; the terminal groups of the selected SAM affect the adhesion between the SAM layer and the Cu layer. In recent years, Ramanath et al have demonstrated that SAM films can act not only as a barrier to Cu in the underlying SiO layer₂Inhibitors of layer diffusion and may also enhance Cu/SiO₂Adhesion of the interface.

Disclosure of Invention

Aiming at the defects of the prior art, the invention aims to provide a diffusion barrier layer material for a copper interconnection circuit and a preparation method thereof, wherein the barrier layer has good coverage, good electrical property and temperature resistance, and the thinnest can be 1.3 nm. In order to solve the problems of the prior art, the invention adopts the technical scheme that: a diffusion barrier material for copper interconnects comprising APTMS, modified with 3, 5-dichlorobenzoic acid.

Drawings

Fig. 1 is a three-dimensional AMF image of APTMS.

FIG. 2 is a three-dimensional AFM image of modified SAMs.

FIG. 3 is an SEM image of modified SAMs.

FIG. 4 is an EDS elemental map analysis of modified SAMs.

Detailed Description

The preparation method of the barrier layer material for copper interconnection comprises the following steps.

Step 1, cutting the silicon wafer into test pieces with the size of 10mm x 10mm, then sequentially ultrasonically cleaning the test pieces for 10min by using acetone, absolute ethyl alcohol and deionized water to remove organic matters on the surface of the silicon wafer, and placing the silicon wafer in an inert environment for later use.

And 2, taking out the silicon wafer during the experiment, and cleaning the silicon wafer with deionized water. Then, under the condition of a constant-temperature oil bath kettle at 120 ℃, the silicon wafer is soaked in a mixed solution (volume ratio is 4: 1) of concentrated sulfuric acid and hydrogen peroxide for 10 min. Because the solution has high oxidizing capacity, the metal can be dissolved in the solution after being oxidized, and organic matters are oxidized into CO₂And H₂And removing the O.

And 3, taking the silicon wafer out of the step 2, and ultrasonically oscillating and cleaning the silicon wafer by using deionized water. Then soaking the substrate for 10min by using 10% HF at room temperature, and washing off a natural oxide layer on the surface. At this point it can be observed that the surface changes from hydrophilic to hydrophobic.

And 4, taking the silicon wafer out of the step 3, and cleaning the silicon wafer with deionized water. In a constant-temperature oil bath kettle at 85 ℃, the silicon wafer is soaked in a mixed solution (volume ratio is 5: 1: 1) of deionized water, hydrogen peroxide and ammonia water for 10 min. Due to the action of H2O2, a thin SiO2 layer is generated on the surface of the silicon wafer, and the hydrophobic layer is changed into hydrophilic layer when the thin SiO2 layer is attached to the surface of the silicon wafer.

And 5, taking the silicon wafer out of the step 4, and washing the silicon wafer with deionized water. In a constant-temperature oil bath kettle at 85 ℃, the silicon wafer is soaked in a mixed solution (volume ratio is 6: 1: 1) of deionized water, hydrogen peroxide and concentrated hydrochloric acid for 10 min. And removing metal contamination of sodium, magnesium, iron and the like on the surface.

And 6, finally, taking out the silicon wafer, cleaning the silicon wafer with deionized water, and blow-drying the silicon wafer with nitrogen for later use.

And 7, adding 2mmol of 3-aminopropyl trimethoxy siloxane (APTMS) into 20ml of toluene, uniformly dispersing the solution by using an ultrasonic oscillator, then putting the hydroxylated silicon wafer into the solution, adding trace deionized water, and allowing APTMS to self-assemble for 2 hours.

And 8, taking out the silicon wafer, sequentially ultrasonically cleaning the silicon wafer for 5min by using toluene and ethanol, and then blow-drying the silicon wafer by using nitrogen.

Step 9, 192mg of 1-ethyl- (3-dimethylaminopropyl) carbodiimide hydrochloride (EDC) and 116mg of N-hydroxysuccinimide (NHS) were dissolved in 20ml of ethanol, and 3, 5-dichlorobenzoic acid was added thereto and reacted for half an hour.

And step 10, adding sodium hydrosulfide, carrying out ultrasonic oscillation to fully dissolve the sodium hydrosulfide, soaking the silicon wafer with the APTMS in the silicon wafer, and carrying out in-situ modification for 2 hours in a stable water bath at 70 ℃.

And 11, mounting the sample on a target table of a vacuum chamber, and preparing a Cu film in an argon environment by adopting a direct-current magnetron sputtering technology and taking high-purity Cu as a target material in a vacuum environment. The sputtering pressure was 0.3pa, the flow rate of argon gas was 30sccm, the sputtering power was 120W, and the deposition thickness was 50 nm.

The performance test of the prepared device shows that the resistance of the device can still be ensured to be 0.2 omega at 500 ℃, and a Cu-Si compound does not appear.