阅读说明：本技术 Mim电容的制造方法及一mim电容 (MIM capacitor and manufacturing method thereof ) 是由 毛永吉 于 2019-09-12 设计创作，主要内容包括：本发明涉及MIM电容的制造方法及一MIM电容,涉及半导体集成电路制造技术,在形成金属栅极结构的过程中形成MIM电容的下极板,并在半导体集成电路的制造必须工艺过程中形成MIM电容的上极板以及位于下极板和上极板之的电容介电层,以将MIM电容的制造工艺集成在半导体集成电路制造的固有的工艺中,从而在半导体集成电路制造过程中同时完成MIM电容的制造,不增加半导体集成电路制造工艺步骤,成本低,且形成的MIM电容具有高电容密度、低漏电及小电压线性的特性。(The invention relates to a manufacturing method of an MIM capacitor and the MIM capacitor, relating to the manufacturing technology of a semiconductor integrated circuit, wherein a lower pole plate of the MIM capacitor is formed in the process of forming a metal gate structure, an upper pole plate of the MIM capacitor and a capacitor dielectric layer positioned between the lower pole plate and the upper pole plate are formed in the necessary process of manufacturing the semiconductor integrated circuit, so that the manufacturing process of the MIM capacitor is integrated in the inherent process of manufacturing the semiconductor integrated circuit, thereby simultaneously completing the manufacturing of the MIM capacitor in the manufacturing process of the semiconductor integrated circuit, not increasing the manufacturing process steps of the semiconductor integrated circuit, having low cost, and the formed MIM capacitor has the characteristics of high capacitance density, low electric leakage and small voltage linearity.)

1. A method of fabricating a MIM capacitor, comprising:

s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of well regions, a polycrystalline silicon grid structure is formed on the surface of each well region, the polycrystalline silicon grid structure comprises a grid dielectric layer formed on the surface of the semiconductor substrate and a polycrystalline silicon pseudo grid positioned on the grid dielectric layer, the polycrystalline silicon pseudo grid is removed, a metal grid is formed in the removal area of the polycrystalline silicon pseudo grid to form a metal grid structure, the metal grid structure comprises a grid dielectric layer, an electrode blocking layer and a metal grid, the grid dielectric layer is formed on the surface of the semiconductor substrate, the electrode blocking layer is positioned between the grid dielectric layer and the metal grid, and a lower polar plate of an MIM capacitor is formed in the process of forming the metal;

s2: forming a capacitor dielectric layer above a lower electrode plate of the MIM capacitor; and

s3: and forming an upper electrode plate of the MIM capacitor above the capacitor dielectric layer, so that the capacitor dielectric layer is positioned between the lower electrode plate and the upper electrode plate, and the lower electrode plate, the upper electrode plate and the capacitor dielectric layer form the MIM capacitor.

2. The method of claim 1, wherein a sidewall is formed on a side surface of the metal gate structure in step S1, an interlayer film is formed on a region outside the sidewall of the metal gate structure, the sidewall is formed on the side surface of the polysilicon dummy gate before the polysilicon dummy gate is removed, the interlayer film is also formed before the polysilicon dummy gate is removed, and the lower plate of the MIM capacitor is formed in the interlayer film.

3. The method of claim 2, wherein the lower plate of the MIM capacitor is formed during the formation of the metal gate.

4. The method of claim 3, wherein after the inter-layer film is formed in step S1, the polysilicon dummy gate is removed, the electrode barrier layer is formed on the gate dielectric layer in the removed region of the polysilicon dummy gate, and then a photoresist is coated thereon, and a photoresist etching process is performed on the photoresist to form a trench on the inter-layer film, and then the photoresist is removed, and a metal layer is coated thereon, wherein the metal layer covers the removed region of the polysilicon dummy gate, the trench, and the surface of the inter-layer film, and then a planarization process is performed to form a metal gate on the electrode barrier layer in the removed region of the polysilicon dummy gate, and simultaneously form the bottom plate of the MIM capacitor in the trench.

5. The method of claim 4, wherein the lower plate and the metal gate of the MIM capacitor are both made of aluminum.

6. The method of claim 2, wherein the electrode barrier layer comprises a TiN layer and a TiAL layer.

7. The method of claim 6, wherein the bottom plate of the MIM capacitor is formed during the TiN layer formation process of the metal gate structure.

8. The method of claim 7, wherein after the formation of the interlayer film in step S1, the polysilicon dummy gate is removed, then covered with a layer of photoresist, and the photoresist is subjected to a photolithography etching process to form a trench on the interlayer film, then the photoresist is removed, and covered with a layer of TiN covering the surface of the removed region of the polysilicon dummy gate, the trench, and the surface of the interlayer film, and then a planarization process is performed to form a TiN layer in the electrode barrier layer on the gate dielectric layer in the removed region of the polysilicon dummy gate and simultaneously form the bottom plate of the MIM capacitor in the trench, and then form a TiAL layer in the electrode barrier layer and the metal gate to form the metal gate structure.

9. The method of claim 8, wherein the lower plate of the MIM capacitor is made of the same material as the TiN layer in the electrode barrier layer.

10. The method of claim 6, wherein the lower plate of the MIM capacitor is formed during the formation of the TiAL layer of the metal gate structure.

11. The method of claim 10, wherein after the formation of the interlayer film in step S1, the polysilicon dummy gate is removed, a TiN layer in the electrode barrier layer is formed on the gate dielectric layer in the removed region of the polysilicon dummy gate, and then a photoresist is coated thereon, a photoresist etching process is performed on the photoresist to form a trench on the interlayer film, and then the photoresist is removed, and a TiAL layer is coated thereon, the TiAL layer covers the surface of the removed region of the polysilicon dummy gate, the trench, and the surface of the interlayer film, and then a planarization process is performed to form a TiAL layer on the TiN layer in the electrode barrier layer in the removed region of the polysilicon dummy gate, and simultaneously a lower plate of the MIM capacitor is formed in the trench, and then a metal gate is formed to form the metal gate structure.

12. The method of claim 11, wherein the lower plate of the MIM capacitor is made of the same material as the TiAL layer in the electrode barrier layer.

13. The method of claim 1, wherein the capacitor dielectric layer formed in step S2 covers the bottom plate of the MIM capacitor.

14. The method of claim 2, wherein the capacitor dielectric layer formed in step S2 covers the lower plate and the interlayer film of the MIM capacitor.

15. The method of claim 1, wherein the capacitor dielectric layer is SIN, HFO2, ZrO, Al2O3, or ZrO.

16. The method of claim 13, wherein a titanium nitride layer is formed over the capacitor dielectric layer in step S3, and then a photolithography process is performed to form the top plate of the MIM capacitor, such that the bottom plate, the top plate and the capacitor dielectric layer form the MIM capacitor.

17. The method of manufacturing a MIM capacitor according to claim 16 further comprising:

s4: and forming a second interlayer film after forming the upper plate of the MIM capacitor, wherein the second interlayer film covers all exposed areas on the semiconductor substrate, and then performing a photoetching process to form a plurality of grooves in the second interlayer film and fill metal in the grooves to form a plurality of via holes, so that one via hole is connected with the metal gate of the metal gate structure to form the gate of the CMOS device, one via hole is connected with the upper plate of the MIM capacitor to form one plate of the MIM capacitor, and one via hole penetrates through the capacitor dielectric layer to be connected with the lower plate of the MIM capacitor to form the other plate of the MIM capacitor.

18. The method of claim 14, wherein a titanium nitride layer is formed over the capacitor dielectric layer in step S3, and a photolithography process is performed to form a plurality of titanium nitride layer plates, wherein a titanium nitride layer plate is disposed over the capacitor dielectric layer to form an upper plate of the MIM capacitor, such that the lower plate, the upper plate and the capacitor dielectric layer form the MIM capacitor.

19. The method of manufacturing a MIM capacitor according to claim 18 further comprising:

s4: forming a second interlayer film after forming an upper polar plate of the MIM capacitor, wherein the second interlayer film covers all exposed areas on the semiconductor substrate, then carrying out a photoetching process to form a plurality of grooves in the second interlayer film, and filling metal in the grooves to form a plurality of via holes, so that one via hole is connected with a metal gate of a metal gate structure to form a gate of a CMOS device, one via hole is connected with the upper polar plate of the MIM capacitor to form one polar plate of the MIM capacitor, one via hole penetrates through a capacitor dielectric layer to be connected with a lower polar plate of the MIM capacitor to form the other polar plate of the MIM capacitor, and the via holes further comprise a via hole connected with other titanium nitride layer polar plates except the upper polar plate of the MIM capacitor.

20. An MIM capacitor manufactured by the method of claim 1.

Technical Field

The present invention relates to semiconductor integrated circuit manufacturing technologies, and in particular, to a method for manufacturing an MIM capacitor and an MIM capacitor.

Background

In the field of semiconductor integrated circuit manufacturing technology, with the development of semiconductor technology, the requirements for the performance of semiconductor devices are higher and higher. The capacitor is an important component unit in an integrated circuit, is widely applied to chips such as a memory, a microwave chip, a radio frequency chip, a smart card chip, a high voltage chip, a filter chip and the like, and has specific applications such as a band-pass filter, a phase-locked loop chip, a dynamic random access memory chip and the like. With the development of semiconductor technology, it is desirable to have high capacitance density, low leakage and small voltage linearity for the capacitors in the integrated circuit, and this also becomes a challenge for the fabrication of the capacitors in the integrated circuit.

The integrated circuit chip has various capacitor structures, such as a MOS field effect transistor (mosfet) capacitor, a poly-insulator-poly (PIP) capacitor, a variable junction capacitor, and a metal-insulator-metal (MIM) capacitor and a metal-oxide-metal (MOM) capacitor in a back-end interconnect. The capacitor structure existing in the back-end interconnection layer does not occupy the area of the device layer, and the linear characteristic of the capacitor is far better than that of other types of capacitors. However, currently, common back-end capacitor structures such as MIM capacitors and MOM capacitors need a special process flow to be manufactured, that is, the process flow for manufacturing MIM capacitors and MOM capacitors cannot be completed simultaneously in the manufacturing processes of other semiconductor devices in a semiconductor integrated circuit, so that the manufacturing process of the originally extremely complex integrated circuit is more complex and the cost is higher.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a manufacturing process of a MIM capacitor according to the prior art. Two layers of masks 110 and 120 are required in the process of forming two vias 210 and 220 for forming two metal electrodes 230 as shown in fig. 1. The MIM capacitor thus formed has a high capacitance density, small leakage current, and high accuracy, but the MIM capacitor is expensive to manufacture.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating a manufacturing process of a MOM capacitor in the prior art. As shown in fig. 2, three different MOM capacitors are shown, including a MOM capacitor, an APMOM capacitor and a VNCAP capacitor, and the MOM capacitor mainly utilizes the overall capacitance between the upper and lower metal wires and the metal in the same layer. Although the existing MOM capacitor manufacturing process is low in cost, the conventional MOM capacitor manufacturing process also needs a special process flow for manufacturing, has large leakage current and affects the size of a chip.

Disclosure of Invention

The invention aims to provide a manufacturing method of an MIM capacitor, which is used for simultaneously finishing the manufacturing of the MIM capacitor in the manufacturing process of a semiconductor integrated circuit, does not increase the manufacturing process steps of the semiconductor integrated circuit, has low cost, and the formed MIM capacitor has the characteristics of high capacitance density, low leakage and small voltage linearity.

The manufacturing method of the MIM capacitor provided by the invention comprises the following steps: s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of well regions, a polycrystalline silicon grid structure is formed on the surface of each well region, the polycrystalline silicon grid structure comprises a grid dielectric layer formed on the surface of the semiconductor substrate and a polycrystalline silicon pseudo grid positioned on the grid dielectric layer, the polycrystalline silicon pseudo grid is removed, a metal grid is formed in the removal area of the polycrystalline silicon pseudo grid to form a metal grid structure, the metal grid structure comprises a grid dielectric layer, an electrode blocking layer and a metal grid, the grid dielectric layer is formed on the surface of the semiconductor substrate, the electrode blocking layer is positioned between the grid dielectric layer and the metal grid, and a lower polar plate of an MIM capacitor is formed in the process of forming the metal; s2: forming a capacitor dielectric layer above a lower electrode plate of the MIM capacitor; and S3: and forming an upper electrode plate of the MIM capacitor above the capacitor dielectric layer, so that the capacitor dielectric layer is positioned between the lower electrode plate and the upper electrode plate, and the lower electrode plate, the upper electrode plate and the capacitor dielectric layer form the MIM capacitor.

Further, in step S1, a side wall is formed on a side surface of the metal gate structure, an interlayer film is formed in a region outside the side wall of the metal gate structure, the side wall is formed on the side surface of the polysilicon dummy gate before the polysilicon dummy gate is removed, the interlayer film is also formed before the polysilicon dummy gate is removed, and the lower plate of the MIM capacitor is formed in the interlayer film.

Furthermore, the lower plate of the MIM capacitor is formed in the formation process of the metal gate.

Further, in step S1, after the inter-layer film is formed, the polysilicon dummy gate is removed, an electrode blocking layer is formed on the gate dielectric layer in the removal region of the polysilicon dummy gate, and then a layer of photoresist is covered, a photolithography etching process is performed on the photoresist to form a trench on the inter-layer film, and then the photoresist is removed and a metal layer is covered, the metal layer covers the removal region of the polysilicon dummy gate, the trench and the surface of the inter-layer film, and then a planarization process is performed to form a metal gate on the electrode blocking layer in the removal region of the polysilicon dummy gate, and simultaneously a lower plate of the MIM capacitor is formed in the trench.

Furthermore, the lower plate of the MIM capacitor and the metal gate are both made of aluminum.

Further, the electrode barrier layer includes a TiN layer and a TiAL layer.

Furthermore, the lower plate of the MIM capacitor is formed in the process of forming the TiN layer of the metal gate structure.

Further, after forming the interlayer film in step S1, the polysilicon dummy gate is removed, then a photoresist layer is covered, a photoresist etching process is performed on the photoresist layer to form a trench on the interlayer film, then the photoresist layer is removed, and a TiN layer is covered, the TiN layer covers the surface of the removal region of the polysilicon dummy gate, the trench and the surface of the interlayer film, then a planarization process is performed to form a TiN layer in the electrode barrier layer on the gate dielectric layer in the removal region of the polysilicon dummy gate, and simultaneously a bottom plate of the MIM capacitor is formed in the trench, and then a TiAL layer in the electrode barrier layer and the metal gate are formed to form the metal gate structure.

Furthermore, the material of the lower plate of the MIM capacitor is the same as that of the TiN layer in the electrode barrier layer.

Furthermore, the lower plate of the MIM capacitor is formed in the process of forming the TiAL layer of the metal gate structure.

Further, after forming the interlayer film in step S1, the polysilicon dummy gate is removed, a TiN layer in the electrode barrier layer is formed on the gate dielectric layer in the removed region of the polysilicon dummy gate, and then a layer of photoresist is covered, a photoresist etching process is performed on the photoresist to form a trench on the interlayer film, and then the photoresist is removed, and a layer of TiAL is covered, the TiAL layer covers the surface of the removed region of the polysilicon dummy gate, the trench, and the surface of the interlayer film, and then a planarization process is performed to form a TiAL layer on the TiN layer in the electrode barrier layer in the removed region of the polysilicon dummy gate, and simultaneously a bottom plate of the capacitor is formed in the trench, and then a metal gate is formed to form a metal gate structure.

Furthermore, the material of the lower plate of the MIM capacitor is the same as that of the TiAL layer in the electrode barrier layer.

Further, the capacitor dielectric layer formed in step S2 covers the lower plate of the MIM capacitor.

Further, the capacitor dielectric layer formed in step S2 covers the lower plate and the interlayer film of the MIM capacitor.

Furthermore, the material of the capacitor dielectric layer is SIN, HFO2, ZrO, Al2O3 or ZrO.

Further, in step S3, a titanium nitride layer is formed over the capacitor dielectric layer, and then a photolithography process is performed to form an upper plate of the MIM capacitor, such that the lower plate, the upper plate and the capacitor dielectric layer form the MIM capacitor.

Further, the method also comprises the following steps: s4: and forming a second interlayer film after forming the upper plate of the MIM capacitor, wherein the second interlayer film covers all exposed areas on the semiconductor substrate, and then performing a photoetching process to form a plurality of grooves in the second interlayer film and fill metal in the grooves to form a plurality of via holes, so that one via hole is connected with the metal gate of the metal gate structure to form the gate of the CMOS device, one via hole is connected with the upper plate of the MIM capacitor to form one plate of the MIM capacitor, and one via hole penetrates through the capacitor dielectric layer to be connected with the lower plate of the MIM capacitor to form the other plate of the MIM capacitor.

Further, in step S3, a titanium nitride layer is formed over the capacitor dielectric layer, and then a photolithography etching process is performed to form a plurality of titanium nitride layer plates, wherein a titanium nitride layer plate is disposed over the capacitor dielectric layer to form an upper plate of the MIM capacitor, such that the lower plate, the upper plate and the capacitor dielectric layer form the MIM capacitor.

Further, the method also comprises the following steps: s4: forming a second interlayer film after forming an upper polar plate of the MIM capacitor, wherein the second interlayer film covers all exposed areas on the semiconductor substrate, then carrying out a photoetching process to form a plurality of grooves in the second interlayer film, and filling metal in the grooves to form a plurality of via holes, so that one via hole is connected with a metal gate of a metal gate structure to form a gate of a CMOS device, one via hole is connected with the upper polar plate of the MIM capacitor to form one polar plate of the MIM capacitor, one via hole penetrates through a capacitor dielectric layer to be connected with a lower polar plate of the MIM capacitor to form the other polar plate of the MIM capacitor, and the via holes further comprise a via hole connected with other titanium nitride layer polar plates except the upper polar plate of the MIM capacitor.

The invention also provides the MIM capacitor which is manufactured by the manufacturing method of the MIM capacitor.

The manufacturing method of the MIM capacitor and the MIM capacitor provided by the invention form the lower pole plate of the MIM capacitor in the process of forming the metal gate structure, and form the upper pole plate of the MIM capacitor and the capacitor dielectric layer positioned between the lower pole plate and the upper pole plate in the necessary process of manufacturing the semiconductor integrated circuit, so that the manufacturing process of the MIM capacitor is integrated in the inherent process of manufacturing the semiconductor integrated circuit, thereby simultaneously finishing the manufacturing of the MIM capacitor in the manufacturing process of the semiconductor integrated circuit, not increasing the manufacturing process steps of the semiconductor integrated circuit, having low cost, and the formed MIM capacitor has the characteristics of high capacitance density, low electric leakage and small voltage linearity.

Drawings

Fig. 1 is a schematic diagram illustrating a process of manufacturing a MIM capacitor according to the prior art.

FIG. 2 is a schematic diagram of a process for fabricating a MOM capacitor in the prior art.

Fig. 3 is a flowchart illustrating a method of fabricating a MIM capacitor according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an MIM capacitor integrated in a semiconductor integrated circuit according to an embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating a bottom plate fabricating process of a MIM capacitor according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a lower plate fabricating process of a MIM capacitor according to another embodiment of the present invention.

Fig. 7 is a schematic diagram of a lower plate fabricating process of a MIM capacitor according to another embodiment of the present invention.

Detailed Description

The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In an embodiment of the present invention, a method for manufacturing an MIM capacitor is provided, and specifically, referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing an MIM capacitor according to an embodiment of the present invention. Referring to fig. 4, fig. 4 is a schematic structural diagram of an MIM capacitor integrated in a semiconductor integrated circuit according to an embodiment of the present invention. The manufacturing method of the MIM capacitor of an embodiment of the invention comprises the following steps: s1: providing a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a plurality of well regions, a polysilicon gate structure is formed on the surface of each well region, the polysilicon gate structure comprises a gate dielectric layer 210 formed on the surface of the semiconductor substrate 100 and a polysilicon dummy gate positioned on the gate dielectric layer 210, the polysilicon dummy gate is removed, a metal gate is formed in a removal region 220 of the polysilicon dummy gate to form a metal gate structure 300, the metal gate structure 300 comprises a gate dielectric layer 210, an electrode barrier layer 330 and a metal gate 340, the gate dielectric layer 210 is formed on the surface of the semiconductor substrate 100, the electrode barrier layer 330 is positioned between the gate dielectric layer 210 and the metal gate 340, and a lower plate 410 of the MIM capacitor 200 is formed in the process of forming the metal gate structure 300; s2: forming a capacitor dielectric layer 420 over the lower plate 410 of the MIM capacitor; s3: the top plate 430 of the MIM capacitor is formed over the capacitor dielectric layer 420 such that the capacitor dielectric layer 420 is located between the bottom plate 410 and the top plate 430, such that the bottom plate 410, the top plate 430, and the capacitor dielectric layer 420 form the MIM capacitor 200.

As described above, the lower plate of the MIM capacitor is formed during the formation of the metal gate structure, and the upper plate of the MIM capacitor and the capacitor dielectric layer located between the lower plate and the upper plate are formed during the fabrication of the semiconductor integrated circuit, so as to integrate the fabrication process of the MIM capacitor into the intrinsic process of the semiconductor integrated circuit fabrication, thereby simultaneously completing the fabrication of the MIM capacitor during the semiconductor integrated circuit fabrication without increasing the steps of the semiconductor integrated circuit fabrication process, resulting in low cost and the MIM capacitor having the characteristics of high capacitance density, low leakage current and small voltage linearity.

In an embodiment of the present invention, in step S1, a sidewall 510 is formed on a side surface of the metal gate structure 300, an interlayer film 520 is formed in a region outside the sidewall 510 of the metal gate structure 300, the sidewall 510 is formed on a side surface of the polysilicon dummy gate before the polysilicon dummy gate is removed, the interlayer film 520 is also formed before the polysilicon dummy gate is removed, and the lower plate 410 of the MIM capacitor is formed in the interlayer film 520.

More specifically, in an embodiment of the present invention, the lower plate 410 of the MIM capacitor is formed during the formation process of the metal gate 340 of the metal gate structure 300. Specifically, referring to fig. 5, fig. 5 is a schematic diagram illustrating a lower plate manufacturing process of an MIM capacitor according to an embodiment of the present invention. Specifically, in step S1, after the interlayer film 520 is formed, the polysilicon dummy gate is removed, the electrode blocking layer 330 is formed on the gate dielectric layer 210 in the removal region 220 of the polysilicon dummy gate, and then a layer of photoresist 610 is covered, a photolithography etching process is performed on the photoresist 610 to form a trench 521 on the interlayer film 520, and then the photoresist 610 is removed and a layer of metal layer 710 is covered, the metal layer 710 covers the removal region 220 of the polysilicon dummy gate, the trench 521 and the surface of the interlayer film 520, and then a planarization process is performed to form the metal gate 340 on the electrode blocking layer 330 in the removal region 220 of the polysilicon dummy gate, and simultaneously the lower plate 410 of the MIM capacitor is formed in the trench 521. I.e., the formation process of the lower plate 410 of the MIM capacitor is integrated into the formation of the metal gate structure 300. Specifically, in an embodiment of the present invention, the material of the lower plate 410 of the MIM capacitor and the material of the metal gate 340 are both Aluminum (AL).

More specifically, as shown in fig. 4, in an embodiment of the present invention, the electrode barrier layer 330 includes a TiN layer 332 and a TiAL layer 331. The lower plate 410 of the MIM capacitor is formed during the formation process of the TiN layer 332 of the metal gate structure 300. Specifically, referring to fig. 6, fig. 6 is a schematic diagram illustrating a lower plate manufacturing process of an MIM capacitor according to another embodiment of the present invention. Specifically, in step S1, after the interlayer film 520 is formed, the polysilicon dummy gate is removed, and then covered with a layer of photoresist 610, the photoresist 610 is subjected to a photolithography etching process to form a trench 521 on the interlayer film 520, and then the photoresist 610 is removed, and covered with a layer of TiN 720, which covers the surface of the removal region 220 of the polysilicon dummy gate, the trench 521 and the surface of the interlayer film 520, and then a planarization process is performed to form the TiN layer 332 in the electrode barrier layer 330 on the gate dielectric layer 210 in the removal region 220 of the polysilicon dummy gate, and simultaneously form the lower plate 410 of the MIM capacitor in the trench 521, and then form the TiAL layer 331 in the electrode barrier layer 330 and the metal gate 340 to form the metal gate structure 300. I.e., the formation process of the lower plate 410 of the MIM capacitor is integrated into the formation of the metal gate structure 300. Specifically, in an embodiment of the present invention, the material of the lower plate 410 of the MIM capacitor is the same as the material of the TiN layer 332 in the electrode barrier 330.

More specifically, in an embodiment of the present invention, the lower plate 410 of the MIM capacitor is formed during the formation process of the TiAL layer 331 of the metal gate structure 300. Specifically, referring to fig. 7, fig. 7 is a schematic diagram illustrating a lower plate manufacturing process of an MIM capacitor according to another embodiment of the present invention. Specifically, in step S1, after forming the interlayer film 520, the polysilicon dummy gate is removed, the TiN layer 332 in the electrode barrier layer 330 is formed on the gate dielectric layer 210 in the removal region 220 of the polysilicon dummy gate, and then a layer of photoresist 610 is covered, a photolithography etching process is performed on the photoresist 610 to form a trench 521 on the interlayer film 520, and then the photoresist 610 is removed and a layer of TiAL layer 730 is covered, the TiAL layer 730 covers the surface of the removal region 220 of the polysilicon dummy gate, the trench 521 and the surface of the interlayer film 520, and then a planarization process is performed to form a TiAL layer 321 on the TiN layer 332 in the electrode barrier layer 330 in the removal region 220 of the polysilicon dummy gate, and simultaneously form the lower plate 410 of the MIM capacitor in the trench 521, and then form the metal gate 340 to form the metal gate structure 300. I.e., the formation process of the lower plate 410 of the MIM capacitor is integrated into the formation of the metal gate structure 300. Specifically, in an embodiment of the present invention, a material of the lower plate 410 of the MIM capacitor is the same as a material of the TiAL layer in the electrode barrier 330.

As described above, the forming process of the lower plate 410 of the MIM capacitor is integrated into the forming processes of the metal gate 340, the TiN layer 332 and the TiAL331, but the invention is not limited thereto, and the forming process of the lower plate 410 of the MIM capacitor may be integrated into any forming process of the layer that can be used as a capacitor plate in the metal gate structure 300, so that the lower plate 410 of the MIM capacitor can be formed simultaneously in the manufacturing process of the gate of the CMOS device of the semiconductor device, thereby reducing the manufacturing process of the semiconductor integrated circuit and reducing the cost.

More specifically, as shown in fig. 4, the gate dielectric layer 210 includes an interfacial layer 211, a high-k layer 212, and etch stoppers 213a and 213 b.

The interface layer 211 is located between the high dielectric constant layer 212 and the semiconductor substrate 100.

The etch stoppers 213a and 213b are positioned between the high dielectric constant layer 212 and the electrode stopper 330.

The material of the interfacial layer 211 comprises silicon oxide.

The material of the high-k layer 212 includes silicon dioxide, silicon nitride, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, hafnium dioxide, lanthanum oxide, zirconium dioxide, strontium titanate, or zirconium silicate oxide.

The material of the etch stop layers 213a and 213b includes metal nitride; preferably, as shown in fig. 4, the metal nitride of the etch stop layer 213a is titanium nitride, and the metal nitride of the etch stop layer 213b is tantalum nitride.

In an embodiment of the present invention, the capacitor dielectric layer 420 may be any insulating material capable of forming a capacitor with a capacitor plate, and in an embodiment of the present invention, the material of the capacitor dielectric layer 420 is SIN, HFO2, ZrO, Al2O3, or ZrO. In an embodiment of the present invention, the capacitor dielectric layer 420 is formed by a deposition process.

As shown in fig. 4, in an embodiment of the present invention, the capacitor dielectric layer 420 formed in step S2 covers the lower plate 410 of the MIM capacitor. More specifically, in step S3, a titanium nitride layer is formed on the capacitor dielectric layer 420, and then a photolithography process is performed to form the upper plate 430 of the MIM capacitor, such that the lower plate 410, the upper plate 430 and the capacitor dielectric layer 420 form the MIM capacitor. I.e., high resistance titanium nitride as the top plate. More specifically, in an embodiment of the present invention, the method for manufacturing the MIM capacitor further includes S4: after the upper plate 430 of the MIM capacitor is formed, a second interlayer film 530 is formed, the second interlayer film 530 covers all the exposed regions on the semiconductor substrate, and then a photolithography and etching process is performed to form a plurality of trenches in the second interlayer film 530, and a plurality of vias 800 are formed by filling metal in the plurality of trenches, such that one of the vias connects to the metal gate 340 of the metal gate structure 300 to form a gate of the CMOS device, one of the vias connects to the upper plate 430 of the MIM capacitor to form one plate of the MIM capacitor, and one of the vias passes through the capacitor dielectric layer 420 to connect to the lower plate 410 of the MIM capacitor to form the other plate of the MIM capacitor.

More specifically, in the embodiment of the present invention, the capacitor dielectric layer 420 formed in step S2 covers the lower plate 410 and the interlayer film 520 of the MIM capacitor. As shown in fig. 4, in an embodiment of the invention, in step S3, a titanium nitride layer is formed over the capacitor dielectric layer 420, and then a photolithography etching process is performed to form a plurality of titanium nitride layer plates 700, wherein a titanium nitride layer plate is located over the capacitor dielectric layer 420 to form the upper plate 430 of the MIM capacitor, so that the lower plate 410, the upper plate 430 and the capacitor dielectric layer 420 form the MIM capacitor. As shown in fig. 4, in an embodiment of the present invention, the method for manufacturing the MIM capacitor further includes S4: after the upper plate 430 of the MIM capacitor is formed, a second interlayer film 530 is formed, the second interlayer film 530 covers all exposed regions of the semiconductor substrate, and then a photolithography and etching process is performed to form a plurality of trenches in the second interlayer film 530, and a plurality of vias 800 are formed by filling metal in the plurality of trenches, such that one of the vias connects to the metal gate 340 of the metal gate structure 300 to form a gate of the CMOS device, one of the vias connects to the upper plate 430 of the MIM capacitor to form one plate of the MIM capacitor, and one of the vias connects to the lower plate 410 of the MIM capacitor through the capacitor dielectric layer 420 to form the other plate of the MIM capacitor, and the plurality of vias 800 further include a via connecting to the other titanium nitride layer plate 700 except the upper plate 430 of the MIM capacitor to form an active device or a passive device in the semiconductor integrated circuit. I.e., the fabrication of the upper plate 430 of the MIM capacitor is done simultaneously during the fabrication of active or passive devices in the semiconductor integrated circuit.

In the manufacturing process of the semiconductor integrated circuit, the manufacturing of the titanium nitride layer is a necessary process in the manufacturing process of the semiconductor integrated circuit, one of the titanium nitride layer polar plates 700 formed by the titanium nitride layer is used as the upper polar plate 430 of the MIM capacitor, namely, the manufacturing process of the upper polar plate 430 of the MIM capacitor is integrated in the manufacturing process of the titanium nitride layer necessary in the semiconductor integrated circuit, so that the manufacturing of the MIM capacitor is completed simultaneously in the manufacturing process of the semiconductor integrated circuit, the manufacturing process steps of the semiconductor integrated circuit are not increased, the cost is low, and the formed MIM capacitor has the characteristics of high capacitance density, low electric leakage and small voltage linearity.

More specifically, in one embodiment of the present invention, the method for fabricating the MIM capacitor of the present invention is applied to small-scale processes of 28nm and 14nm and below.

In an embodiment of the present invention, the planarization process is any suitable planarization process, such as a Chemical Mechanical Polishing (CMP) process.

In an embodiment of the invention, the forming process of any of the material layers may be any film forming process, such as a deposition process, suitable in the industry.

In an embodiment of the present invention, a MIM capacitor is further provided, and the MIM capacitor is manufactured by the manufacturing method of the MIM capacitor.

In summary, the lower plate of the MIM capacitor is formed during the formation of the metal gate structure, and the upper plate of the MIM capacitor and the capacitor dielectric layer located between the lower plate and the upper plate are formed during the necessary processes of the semiconductor integrated circuit manufacturing, so as to integrate the MIM capacitor manufacturing process into the inherent processes of the semiconductor integrated circuit manufacturing, thereby completing the MIM capacitor manufacturing simultaneously during the semiconductor integrated circuit manufacturing process, without increasing the semiconductor integrated circuit manufacturing process steps, with low cost, and the formed MIM capacitor has the characteristics of high capacitor density, low leakage current, and small voltage linearity.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.