阅读说明：本技术 一种紧密集成的芯片封装结构及由其形成的相控阵列射频收发装置 (Closely integrated chip packaging structure and phased array radio frequency transceiver formed by same ) 是由 徐志伟 李娜雨 厉敏 张梓江 王绍刚 高会言 于 2019-08-01 设计创作，主要内容包括：本发明公开一种紧密集成的芯片封装结构及由其形成的相控阵列射频收发装置,该封装结构整合多颗不同生产工艺的芯片设计封装,而非独立设计每颗芯片的封装再在板级互连,从而有效减小了整体的面积,提高了系统集成度,同时改善了射频性能,降低了应用成本,使得在高频卫星通信相控阵中应用多颗不同生产工艺芯片成为可能。(The invention discloses a tightly integrated chip packaging structure and a phased array radio frequency transceiver formed by the same, wherein the packaging structure integrates chip design packaging of a plurality of different production processes, and packaging of each chip is not independently designed and then is interconnected at a board level, so that the whole area is effectively reduced, the system integration level is improved, the radio frequency performance is improved, the application cost is reduced, and the application of a plurality of different production process chips in a high-frequency satellite communication phased array is possible.)

1. A tightly integrated chip packaging structure is characterized in that n chips are sequentially arranged on the top layer of a substrate, and the signal line positions and the ground plane of the chips are coated with copper. Each chip is adhered to the top layer of the substrate, the top layer of the substrate is also coated with copper below the position where the chip is arranged, the copper coating below the chip is connected with the bottom metal of the substrate through a via hole, and the ground planes of the top layer and the bottom layer of the substrate are also connected through a via hole; the bonding pads of the n chips are connected through bar wires or metal connecting wires with the length of less than 2mm in the horizontal direction, the bonding pads of the chips are also connected with the bonding pads of the substrate through the bar wires or the metal connecting wires, and n is more than or equal to 2.

2. A tightly integrated chip packaging structure is characterized in that a cavity with a top opening is formed in the top of a substrate, n chips are sequentially arranged in the cavity of the substrate, a signal line position and a ground plane of a part, which is not opened, of the top of the substrate are coated with copper, each chip is adhered to the bottom surface of the cavity, the cavity is also coated with copper below the position where the chip is arranged, the copper coating below the chip is connected with the bottom surface metal of the substrate through a through hole, and a ground metal layer of the substrate is connected through the through hole; the bonding pads of the n chips are connected through bar wires or metal connecting wires with the length of less than 2mm in the horizontal direction, the bonding pads of the chips are also connected with the bonding pads of the substrate through the bar wires or the metal connecting wires, and n is more than or equal to 2.

3. A phased array radio frequency transmission device formed by the package structure of claim 1 or 2, wherein the transmission device comprises a chip a produced based on a semiconductor process one, a chip B produced based on a semiconductor process two, and M antennas, the chip a comprises a path power divider, an M-channel gain/phase control circuit and an M-channel signal amplifier, and the chip B comprises an M-channel power amplifier; the radio frequency input signal is obtained through a power divider of a chip A, the output of an M channel is subjected to phase shift weighting through a gain/phase control circuit of the chip A, then passes through a signal amplifier of the chip A and a power amplifier of the chip B, and finally is emitted out in an electromagnetic wave form at an antenna; the chip A and the packaging substrate, the chip B and the packaging substrate and the chips A and B are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip A and the chip B in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

4. A phased array radio frequency transmitter formed by the package structure of claim 1 or 2, wherein the transmitter comprises a chip C produced by a semiconductor process one, two chips B produced by a semiconductor process two and N antennas, N is 2 · M, the chip C comprises a single path power divider, an N-channel gain/phase control circuit and an N-channel signal amplifier, each chip B comprises an M-channel power amplifier, a radio frequency input signal passes through the power divider of the chip C to obtain N-channel outputs, which are weighted by the gain/phase control circuit of the chip C, then pass through the signal amplifier of the chip C and the power amplifier of the chip B, and finally are transmitted in the form of electromagnetic waves at the antennas. The chip B is connected with the chip C through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip B and the chip C in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

5. A phased array radio frequency transmission apparatus as claimed in claim 4 or 5, wherein said first semiconductor process is a Si CMOS process and said second semiconductor process is a SiGe BiCMOS process or a III-V compound semiconductor process.

6. a phased array single beam forming radio frequency receiving device formed by the package structure of claim 1 or 2, wherein the receiving device includes P antennas, a chip D produced using a semiconductor process three, and a chip E produced using a semiconductor process four; the chip D comprises a P-channel low noise amplifier; the chip E comprises a P-channel signal amplifier, a P-channel gain/phase control circuit and a power combiner, wherein P-channel radio-frequency signals received by the antenna are subjected to phase shift weighting through the low-noise amplifier of each channel of the chip D, the signal amplifier and the gain/phase control circuit of each channel of the chip E, and are summed and output at the power combiner of the chip E; the chip D and the packaging substrate, the chip D and the chip E are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip E in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

7. A phased-array single-beam forming radio frequency receiving device formed by the package structure of claim 1 or 2, wherein the receiving device includes Q antennas, two chips D produced based on semiconductor process three and one chip F produced based on semiconductor process four, Q being 2 · P; the chip D comprises a P-channel low noise amplifier; the chip F comprises a Q channel signal amplifier, a Q channel gain/phase control circuit and a power combiner; the radio frequency signal of the Q channel received by the antenna passes through a low noise amplifier of each channel of the chip D, is subjected to phase shift weighting through a signal amplifier and a gain/phase control circuit of each channel of the chip F, and is summed and output at a power combiner of the chip F; the chip D and the packaging substrate are connected through a bar wire or a metal connecting wire, and the length of the bar wire or the metal connecting wire between the chip D and the chip F in the horizontal direction is less than 2mm, so that the purpose of tight integration is achieved.

8. A phased array two-beam forming radio frequency receiving device formed by the package structure of claim 1 or 2, wherein the receiving device includes P antennas, a chip D produced using a semiconductor process three, and a chip G produced using a semiconductor process four, the chip D including a P-channel low noise amplifier; the chip G comprises a P channel signal amplifier, a P channel gain/phase control circuit and two paths of power combiners; p channel radio frequency signals pass through a low noise amplifier of each channel of the chip D, pass through a signal amplifier and a gain/phase control circuit of each channel of the chip G to be subjected to phase shifting weighting, are respectively connected to two paths of power combiners to be subjected to summation output, and finally generate two paths of radio frequency output signals B₁、B₂(ii) a The chip D and the packaging substrate, the chip D and the chip G and the packaging substrate are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip G in the horizontal direction<2mm for the purpose of tight integration.

9. a phased-array two-beam synthesis radio frequency receiving device formed by the package structure of claim 1 or 2, wherein the receiving device has Q antennas, a chip D produced by using a semiconductor process three, and a chip H produced by using a semiconductor process four, Q being 2 · P; chip D comprises P channel low noiseAn amplifier; the chip H comprises a Q channel signal amplifier, a Q channel gain/phase control circuit and two paths of power combiners; the radio frequency signal of the Q channel received by the antenna passes through the low noise amplifier of each channel of the chip D, the signal amplifier of each channel of the chip H and the gain/phase control circuit for phase shifting and weighting, and is respectively connected to the two paths of power combiners for summation output, and finally two paths of radio frequency output signals B are generated₁、B₂(ii) a The chip D and the packaging substrate, and the chip D and the chip H are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip H in the horizontal direction<2mm for the purpose of tight integration.

10. the radio frequency receiving device according to any one of claims 6 to 9, wherein the semiconductor process three is a SiGe BiCMOS process or a III-V compound semiconductor process, and the semiconductor process four is a Si CMOS process.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a tightly integrated chip packaging structure and a phased array radio frequency transceiver formed by the same.

Background

Unlike the 5G era that the rapid development of the ground wireless communication is low in delay, high in capacity and large in bandwidth, the satellite communication still mainly demands voice, and is limited in capacity and insufficient in coverage. This is due to the manufacturing, transmission and operating costs of satellites that make the construction of satellite constellations far behind terrestrial wireless communication base stations. Although the traditional geostationary orbit synchronous satellite has a large area coverage area, the problems of long distance, large volume and weight and high manufacturing and transmitting cost exist, and in addition, the synchronous orbit resources are limited, so that the broadband terminal service is difficult to support. With the rapid development of information technology, the successful development of high-frequency large-bandwidth small satellites and the remarkable improvement of rocket carrying technology enable large-scale mass launching of low-orbit satellites to be feasible in a commercial mode. The lower orbit is beneficial to the real-time broadband transmission of information; the high-frequency phased array technology can be used for realizing large data volume and large bandwidth of low-orbit satellite communication.

The phased array transceiver for low-earth-orbit satellite communication consists of dozens of channels to thousands of channels, and the radio frequency receiving and transmitting chip determines the power consumption, the area and the cost of the system to a certain extent. The radio frequency chip based on the silicon-based complementary metal oxide semiconductor process has the advantages of low cost and high integration level, but also has the problems of large substrate loss, high noise coefficient and the like, and the radio frequency chip based on the III-V group compound semiconductor process or the SiGe BiCMOS process has high cost and is difficult to integrate although the circuit performance is outstanding. The integration of chips of different production processes is beneficial to realizing high performance and low cost of the satellite communication phased array transceiver.

The array element spacing of the phased array is proportional to the wavelength and gradually decreases with increasing frequency. In a compactly arranged K-Ka waveband satellite communication phased array, the traditional scheme that chips of different production processes are respectively packaged and interconnected at a board level is limited by array element spacing and is difficult to realize.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a tightly integrated chip packaging structure and a phased array radio frequency transceiver formed by the same, so that the area of a phased array radio frequency receiving and transmitting module is reduced, and the limitation of the array element spacing of a satellite communication phased array is removed. Meanwhile, the method effectively reduces the parasitics of the interconnection lines in the chip packaging and improves the radio frequency performance.

The technical scheme for realizing the purpose of the invention is as follows:

A tightly integrated chip packaging structure is characterized in that n chips are sequentially arranged on the top layer of a substrate, the signal line position and the ground plane of each chip are coated with copper, each chip is adhered to the top layer of the substrate, the top layer of the substrate is also coated with copper below the position where the chip is arranged, the copper coating below the chip is connected with the bottom metal of the substrate through a via hole, and the top layer of the substrate and the ground plane of the bottom layer are also connected through the via hole; the bonding pads of the n chips are connected through bar wires or metal connecting wires with the length of less than 2mm in the horizontal direction, the bonding pads of the chips are also connected with the bonding pads of the substrate through the bar wires or the metal connecting wires, and n is more than or equal to 2.

A tightly integrated chip packaging structure is characterized in that a cavity with a top opening is formed in the top of a substrate, n chips are sequentially arranged in the cavity of the substrate, a signal line position and a ground plane of a part, which is not opened, of the top of the substrate are coated with copper, each chip is adhered to the bottom surface of the cavity, the cavity is also coated with copper below the position where the chip is arranged, the copper coating below the chip is connected with the bottom surface metal of the substrate through a through hole, and a ground metal layer of the substrate is connected through the through hole; the bonding pads of the n chips are connected through bar wires or metal connecting wires with the length of less than 2mm in the horizontal direction, the bonding pads of the chips are also connected with the bonding pads of the substrate through the bar wires or the metal connecting wires, and n is more than or equal to 2.

A phased array radio frequency transmitting device formed by the packaging structure is characterized by comprising a chip A produced based on a semiconductor process I, a chip B produced based on a semiconductor process II and M antennas, wherein the chip A comprises a path of power divider, an M-channel gain/phase control circuit and an M-channel signal amplifier, and the chip B comprises an M-channel power amplifier; the radio frequency input signal is obtained through a power divider of a chip A, the output of an M channel is subjected to phase shift weighting through a gain/phase control circuit of the chip A, then passes through a signal amplifier of the chip A and a power amplifier of the chip B, and finally is emitted out in an electromagnetic wave form at an antenna; the chip A and the packaging substrate, the chip B and the packaging substrate and the chips A and B are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip A and the chip B in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

The phased array radio frequency transmitting device is characterized by comprising a chip C produced based on a semiconductor process I, two chips B produced based on a semiconductor process II and N antennas, wherein N is 2. M, the chip C comprises a path power divider, an N-channel gain/phase control circuit and an N-channel signal amplifier, each chip B comprises an M-channel power amplifier, radio frequency input signals pass through the power divider of the chip C to obtain N-channel output, the N-channel output is subjected to phase shifting weighting through the gain/phase control circuit of the chip C, then passes through the signal amplifier of the chip C and the power amplifier of the chip B, and finally is transmitted in the form of electromagnetic waves at the antennas. The chip B is connected with the chip C through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip B and the chip C in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

Furthermore, the first semiconductor process is a Si CMOS process, and the second semiconductor process is a SiGe BiCMOS process or a III-V compound semiconductor process.

A phased array single beam synthesis radio frequency receiving device formed by the packaging structure is characterized by comprising P antennas, a chip D produced by using a semiconductor process III and a chip E produced by using a semiconductor process IV; the chip D comprises a P-channel low noise amplifier; the chip E comprises a P-channel signal amplifier, a P-channel gain/phase control circuit and a power combiner, wherein P-channel radio-frequency signals received by the antenna are subjected to phase shift weighting through the low-noise amplifier of each channel of the chip D, the signal amplifier and the gain/phase control circuit of each channel of the chip E, and are summed and output at the power combiner of the chip E; the chip D and the packaging substrate, the chip D and the chip E are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip E in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

The phased array single beam synthesis radio frequency receiving device formed by the packaging structure is characterized by comprising Q antennas, two chips D produced based on a semiconductor process III and one chip F produced based on a semiconductor process IV, wherein Q is 2. P; the chip D comprises a P-channel low noise amplifier; the chip F comprises a Q channel signal amplifier, a Q channel gain/phase control circuit and a power combiner; the radio frequency signal of the Q channel received by the antenna passes through a low noise amplifier of each channel of the chip D, is subjected to phase shift weighting through a signal amplifier and a gain/phase control circuit of each channel of the chip F, and is summed and output at a power combiner of the chip F; the chip D and the packaging substrate are connected through a bar wire or a metal connecting wire, and the length of the bar wire or the metal connecting wire between the chip D and the chip F in the horizontal direction is less than 2mm, so that the purpose of tight integration is achieved.

A phased array two-beam synthesis radio frequency receiving device formed by the packaging structure is characterized by comprising P antennas, a chip D produced by using a semiconductor process III and a chip G produced by using a semiconductor process IV, wherein the chip D comprises a P-channel low noise amplifier; the chip G comprises a P channel signal amplifier, a P channel gain/phase control circuit and two paths of power combiners; p channel radio frequency signals pass through a low noise amplifier of each channel of the chip D, pass through a signal amplifier and a gain/phase control circuit of each channel of the chip G to be subjected to phase shifting weighting, are respectively connected to two paths of power combiners to be subjected to summation output, and finally generate two paths of radio frequency output signals B₁、B₂(ii) a Between chip D and package substrate, between chip D and chipThe chips G are connected with each other and the chip G is connected with the packaging substrate through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip G in the horizontal direction<2mm for the purpose of tight integration.

A phased array two-beam synthesis radio frequency receiving device formed by the above package structure, wherein the receiving device has Q antennas, a chip D produced by using a semiconductor process three, and a chip H produced by using a semiconductor process four, Q being 2 · P; the chip D comprises a P-channel low noise amplifier; the chip H comprises a Q channel signal amplifier, a Q channel gain/phase control circuit and two paths of power combiners; the radio frequency signal of the Q channel received by the antenna passes through the low noise amplifier of each channel of the chip D, the signal amplifier of each channel of the chip H and the gain/phase control circuit for phase shifting and weighting, and is respectively connected to the two paths of power combiners for summation output, and finally two paths of radio frequency output signals B are generated₁、B₂(ii) a The chip D and the packaging substrate, and the chip D and the chip H are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip H in the horizontal direction<2mm for the purpose of tight integration.

Furthermore, the third semiconductor process is a SiGe BiCMOS process or a III-V group compound semiconductor process, and the fourth semiconductor process is a Si CMOS process.

Compared with the prior art, the invention has the following beneficial effects:

(1) The packaging structure of the tightly integrated chip provided by the invention integrates the chip design packaging of a plurality of different production processes, but not independently designs the packaging of each chip and interconnects the chips at the board level, thereby effectively reducing the whole area, improving the system integration level and enabling the application of a plurality of chips with different production processes in a high-frequency satellite communication phased array to be possible;

(2) The tightly integrated packaging method reduces the chip spacing and also reduces the parasitic of the interconnecting wires, which is beneficial to reducing the loss and improving the radio frequency performance;

(3) Compared with other complex three-dimensional packaging processes, the packaging structure of the tightly integrated chip provided by the invention is based on a planar process, has a simple structure, is easy to realize, has lower cost and is more suitable for batch production.

Drawings

Fig. 1(a) is a single-layer substrate package structure diagram of a package structure of a tightly integrated chip according to the present invention;

FIG. 1(b) is a diagram of a multi-layer substrate package structure of a tightly integrated chip according to the present invention;

FIGS. 2(a) and 2(b) are block diagrams of two phased array radio frequency transmission devices for high performance satellite communications formed by the packaging structure of the tightly integrated chip of the present invention;

FIGS. 3(a) and 3(b) are structural diagrams of two phased array single beam forming receivers for high performance satellite communications formed by the package structure of the tightly integrated chip according to the present invention;

Fig. 4(a) and 4(b) are structural diagrams of two phased array two-beam synthesis receiving apparatuses for high performance satellite communication formed by the package structure of the tightly integrated chip according to the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the objects and effects of the invention will become more apparent. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 1(a), as an embodiment, a single-layer substrate package structure diagram of a tightly integrated chip package structure is given, in which the integrated chips are chip 1, chip 2 and chip 3, the 3 chips on the package structure are sequentially arranged on the top layer of the substrate, the signal line position and the ground plane of the chip are copper-clad, each chip is adhered to the top layer of the substrate, and the top layer of the substrate is also copper-clad below the position where the chip is arranged, the copper-clad below the chip and the bottom metal of the substrate are connected by a via, and the ground planes of the top layer and the bottom layer of the substrate are also connected by a via; the bonding pads of the 3 chips are connected through bar wires or metal connecting wires with the length of <2mm in the horizontal direction, and the bonding pads of the chips are also connected with the bonding pads of the substrate through the bar wires or the metal connecting wires.

The packaging structure is also suitable for the multilayer substrate.

As shown in fig. 1(b), as another embodiment, a structure diagram of a multi-layer substrate of a tightly integrated chip package structure is provided, in which the integrated chips are also chip 1, chip 2 and chip 3, a cavity with an open top is opened on the top of the substrate, 3 chips are sequentially arranged in the cavity of the substrate, a signal line and a ground plane of a non-open top portion of the substrate are plated with copper, each chip is adhered to the bottom surface of the cavity, the cavity is also plated with copper under the position where the chip is arranged, the copper plating under the chip is connected with the bottom surface metal of the substrate through a via, and the ground metal layer of the substrate is connected through a via; the bonding pads of the 3 chips are connected through bar wires or metal connecting wires with the length of <2mm in the horizontal direction, and the bonding pads of the chips are also connected with the bonding pads of the substrate through the bar wires or the metal connecting wires.

Likewise, the package substrate is also applicable to a single-layer substrate.

The number of chips integrated in the two packaging structures is two or more, but both are preferably 3.

Fig. 2(a) is a structural diagram of one of phased array radio frequency transmission apparatuses for high performance satellite communication formed by a tightly integrated chip package structure according to the present invention, which includes a chip a produced based on a semiconductor process 1, a chip B produced based on a semiconductor process 2, and M antennas. The chip A comprises a path of power divider, an M-channel gain/phase control circuit and an M-channel signal amplifier; chip B includes an M-channel power amplifier. The radio frequency input signals are subjected to phase shift weighting through a gain/phase control circuit of the chip A, then pass through a signal amplifier of the chip A and a power amplifier of the chip B, and finally are emitted in the form of electromagnetic waves at an antenna. The chip A and the packaging substrate, the chip B and the packaging substrate and the chips A and B are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip A and the chip B in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

fig. 2(B) is a structural diagram of another phased array radio frequency transmitting apparatus for high performance satellite communication formed by a tightly integrated chip package structure according to the present invention, which includes one chip C produced based on semiconductor process 1, two chips B produced based on semiconductor process 2, and N antennas (N-2 · M). The chip C comprises a path of power divider, an N-channel gain/phase control circuit and an N-channel signal amplifier; each chip B includes an M-channel power amplifier. The radio frequency input signal is subjected to N-channel output by a power divider of a chip C, phase shift weighting is carried out on the radio frequency input signal through a gain/phase control circuit of the chip C, then the radio frequency input signal passes through a signal amplifier of the chip C and a power amplifier of the chip B, and finally the radio frequency input signal is emitted in the form of electromagnetic waves at an antenna. The chip B is connected with the chip C through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip B and the chip C in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

Preferably, the semiconductor process 1 is a Si CMOS process, and the semiconductor process 2 is a SiGe BiCMOS process or a III-V compound semiconductor process.

Fig. 3(a) is a phased array single beam forming rf receiving device for high performance satellite communication formed by a package structure of tightly integrated chips according to the present invention, which includes P antennas, a chip D produced using a semiconductor process 3, and a chip E produced using a semiconductor process 4. The chip D comprises a P-channel low noise amplifier; chip E includes P channel signal amplifier, P channel gain/phase control circuit and power combiner. P-channel radio-frequency signals received by the antenna are subjected to phase shifting weighting through a low-noise amplifier of each channel of the chip D, a signal amplifier and a gain/phase control circuit of each channel of the chip E respectively, and are summed and output at a combiner of the chip E. The chip D and the packaging substrate, the chip D and the chip E are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip E in the horizontal direction is less than 2mm, so that the purpose of tight integration is realized.

fig. 3(b) is a phased array single beam forming rf receiving device for high performance satellite communication formed by a tightly integrated chip package structure according to the present invention, which includes Q antennas (Q2 · P), two chips D produced based on the semiconductor process 3 and one chip F produced based on the semiconductor process 4. The chip D comprises a P-channel low noise amplifier; chip F includes Q channel signal amplifier, Q channel gain/phase control circuit and power combiner. The radio frequency signal of the Q channel received by the antenna is respectively subjected to phase shift weighting through a low noise amplifier of each channel of the chip D, a signal amplifier and a gain/phase control circuit of each channel of the chip F, and is summed and output at a combiner of the chip F. The chip D and the packaging substrate are connected through a bar wire or a metal connecting wire, and the length of the bar wire or the metal connecting wire between the chip D and the chip F in the horizontal direction is less than 2mm, so that the purpose of tight integration is achieved.

Fig. 4(a) is a phased array two-beam synthesis receiving apparatus for high performance satellite communication formed by a package structure of tightly integrated chips according to the present invention, which includes P antennas, a chip D produced using a semiconductor process 3, and a chip G produced using a semiconductor process 4. The chip D comprises a P-channel low noise amplifier; the chip G comprises a P-channel signal amplifier, a P-channel gain/phase control circuit and two paths of power combiners. P channel radio frequency signals pass through a low noise amplifier of each channel of the chip D, pass through a signal amplifier and a gain/phase control circuit of each channel of the chip G to be subjected to phase shifting weighting, are respectively connected to two paths of power combiners to be subjected to summation output, and finally generate two paths of radio frequency output signals B₁、B₂. The chip D and the packaging substrate, the chip D and the chip G and the packaging substrate are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip G in the horizontal direction<2mm for the purpose of tight integration.

FIG. 4(b) is a phased array two-beam synthesis receiving apparatus for high performance satellite communications formed by the tightly integrated chip package structure according to the present inventionIncluding Q antennas (Q ═ 2 · P), a chip D produced using the semiconductor process 3, and a chip H produced using the semiconductor process 4. The chip D comprises a P-channel low noise amplifier; the chip H comprises a Q channel signal amplifier, a Q channel gain/phase control circuit and two paths of power combiners. The radio frequency signal of the Q channel received by the antenna passes through the low noise amplifier of each channel of the chip D, the signal amplifier of each channel of the chip H and the gain/phase control circuit for phase shifting and weighting, and is respectively connected to the two paths of power combiners for summation output, and finally two paths of radio frequency output signals B are generated₁、B₂. The chip D and the packaging substrate, and the chip D and the chip H are connected through a bar wire or a metal connecting wire, wherein the length of the bar wire or the metal connecting wire between the chip D and the chip H in the horizontal direction<2mm for the purpose of tight integration.

Preferably, the semiconductor process 3 is a SiGe BiCMOS process or a III-V compound semiconductor process, and the semiconductor process 4 is a Si CMOS process.

It will be understood by those skilled in the art that the foregoing is not intended to limit the invention, and although the invention has been described in detail with reference to the foregoing examples, those skilled in the art will recognize that changes may be made in the form and details of the embodiments described in the foregoing examples, or that equivalents may be substituted for elements thereof. All modifications, equivalents and the like which come within the spirit and principle of the invention are intended to be included within the scope of the invention.