阅读说明：本技术 电子封装 (Electronic Packaging ) 是由 林岷臻 李怡慧 周哲雅 陈南诚 于 2019-05-10 设计创作，主要内容包括：本发明提供了一种电子封装。该电子封装包括矩形的封装基板和芯片封装。该芯片封装包括第一高速接口电路裸晶,安装在封装基板的上表面上,其中芯片封装与封装基板具有同轴配置,且芯片封装相对于封装基板具有角度偏移。根据本发明的电子封装,可以减轻信号扭曲和改善信号延迟,提高芯片封装的电性能。(The present invention provides a kind of Electronic Packagings.The Electronic Packaging includes the package substrate and chip package of rectangle.The chip package includes the first high-speed interface circuit bare crystalline, is mounted on the upper surface of package substrate, and wherein chip package and package substrate have arranged coaxial, and chip package has angle offset relative to package substrate.Electronic Packaging according to the present invention can mitigate signal skew and improve signal delay, improve the electrical property of chip package.)

1. a kind of Electronic Packaging, comprising:

The package substrate of rectangle；And

Chip package including the first high-speed interface circuit bare crystalline, the chip package are mounted on the upper surface of the package substrate On, wherein the chip package and the package substrate have arranged coaxial, and the chip package is relative to the encapsulation base Plate has angle offset.

2. Electronic Packaging according to claim 1, wherein the upper surface of the package substrate in a two-dimensional plane by Two quadrature axis are divided into four quadrants, wherein the side at the edge of the first high-speed interface circuit bare crystalline and the chip package Edge is parallel to each other.

3. Electronic Packaging according to claim 2, wherein the first high-speed interface circuit bare crystalline includes being directly facing institute The first edge on the vertex of package substrate is stated, wherein being provided with first row input/output I/O pad along the first edge.

4. Electronic Packaging according to claim 3, wherein the first high-speed interface circuit bare crystalline includes perpendicular to described The second edge of first edge, wherein being provided with second row I/O pad along the second edge.

5. Electronic Packaging according to claim 4, wherein along two of the apex engagement in the package substrate A side is disposed with first group of soldered ball, and wherein the first row I/O pad pass through respectively the package substrate it is described on Multiple first traces in one of quadrant in four quadrants on surface are electrically connected to first group of soldered ball.

6. Electronic Packaging according to claim 5, wherein along the institute of the apex engagement in the package substrate It states one of two sides and is disposed with second group of soldered ball, and wherein the second row I/O pad passes through the encapsulation respectively Multiple second traces in one of quadrant in four quadrants on the upper surface of substrate are electrically connected to Second group of soldered ball.

7. Electronic Packaging according to claim 1, wherein the chip package is in the vertical axis orthogonal with the upper surface On relative to the package substrate rotation substantially 45 degree.

8. Electronic Packaging according to claim 1, wherein the first high-speed interface circuit bare crystalline include the first serializer/ Deserializer circuit block.

9. Electronic Packaging according to claim 1, further includes:

Close to the second high-speed interface circuit bare crystalline of the first high-speed interface circuit bare crystalline.

10. Electronic Packaging according to claim 9, wherein the second high-speed interface circuit bare crystalline includes second serial Device/deserializer circuit block.

11. Electronic Packaging according to claim 9, wherein the first high-speed interface circuit bare crystalline passes through redistribution layer knot Structure is electrically connected to the second high-speed interface circuit bare crystalline.

12. a kind of Electronic Packaging, comprising:

The package substrate of rectangle；And

Chip package including the first high-speed interface circuit bare crystalline, the chip package are mounted on the upper surface of the package substrate On, wherein multiple input/output I/O pads of the first high-speed interface circuit bare crystalline pass through the institute of the package substrate respectively State the soldered ball that multiple traces in one of quadrant in four on upper surface quadrants are electrically connected to the package substrate.

13. Electronic Packaging according to claim 12, wherein the upper surface of the package substrate is in a two-dimensional plane Four quadrants are divided by two quadrature axis.

14. Electronic Packaging according to claim 12, wherein the chip package has coaxial match with the package substrate It sets, and the chip package has angle offset relative to the package substrate.

15. Electronic Packaging according to claim 14, wherein the chip package is orthogonal with the upper surface vertical Relative to substantially 45 degree of package substrate rotation on axis.

16. Electronic Packaging according to claim 14, wherein the first high-speed interface circuit bare crystalline includes being directly facing The first edge on the vertex of the package substrate, and the first edge is provided with first row I/O pad, described first High-speed interface circuit bare crystalline includes the second edge perpendicular to the first edge, wherein being provided with along the second edge Two row's I/O pads.

17. Electronic Packaging according to claim 16, wherein along the apex engagement in the package substrate Two sides are disposed with first group of soldered ball, and wherein the first row I/O pad passes through the described of the package substrate respectively Multiple first traces in one of quadrant of four quadrants on upper surface are electrically connected to first group of soldered ball.

18. Electronic Packaging according to claim 17, wherein along the apex engagement in the package substrate One of described two sides are disposed with second group of soldered ball, and wherein the second row I/O pad passes through the envelope respectively Fill multiple second traces electrical connection in one of quadrant in four quadrants on the upper surface of substrate To second group of soldered ball.

19. Electronic Packaging according to claim 12, wherein the first high-speed interface circuit bare crystalline includes first serial Device/deserializer circuit block.

20. Electronic Packaging according to claim 12, further includes:

Close to the second high-speed interface circuit bare crystalline of the first high-speed interface circuit bare crystalline, wherein second high-speed interface is electric Road bare crystalline includes the second serializer/deserializer circuit block.

21. Electronic Packaging according to claim 20, wherein the first high-speed interface circuit bare crystalline passes through redistribution layer Structure is electrically connected to the second high-speed interface circuit bare crystalline.

Technical field

The present invention generally relates to the semiconductor packages of high data rate (high-data rate) communications applications necks Domain.More particularly it relates to a kind of Electronic Packaging comprising the chip package with igh-speed wire-rod production line circuit, high speed Signal processing circuit can such as be used to send and receive serializer/deserializer of data from serial communication link (serializer/deserializer, SerDes) circuit.

Background technique

In general, data communication network includes multiple communication equipments and the connection for these communication equipments to be interconnected or networked Infrastructure or medium.Communication equipment may include embedded controller.Communication equipment can be with operation in gigabit per second High Speed Analog serial data under (Gigabit-per-second, Gbps) data rate (for example, 56Gbps or 112Gbps) connects Mouth or port connection.Serial data interface is configured according to known data transmission standard.Connecting infrastructure can be with this height Speed simulation serial data interface interaction.

The case where high-speed serial communication link is used in electronic system is in sustainable growth.As it is known in the art, high Speed data link is via transmission line (transmission line) from a position to another location transmission data.These numbers It may include serializer/deserializer (i.e. SerDes) data link according to link, with parallel form (parallel Format data) are received and convert data to serial form (serial format) to carry out high-speed transfer.SerDes data Link can be a part of communication system insole board (backplane).

However, the prior art chip package for high data rate communication application comprising SerDes circuit, usually meets with It is lost by the so-called SerDes as caused by signal skew (signal skew) or signal delay, this is degrading chip in turn The electrical property of encapsulation.

Summary of the invention

It is an object of the present invention to provide a kind of improved semiconductor electronic envelopes for high data rate communication application Dress, can reduce signal skew or signal delay, so as to improve the electrical property of semiconductor electronic package.

According to one embodiment, a kind of Electronic Packaging is disclosed.The Electronic Packaging includes the package substrate and chip of rectangle Encapsulation.The chip package includes the first high-speed interface circuit bare crystalline, is mounted on the upper surface of package substrate, wherein chip package There is arranged coaxial with package substrate, and chip package has angle offset relative to package substrate.

According to one embodiment, chip package is on the vertical axis orthogonal with upper surface relative to package substrate rotation about 45 Degree.

First high-speed interface circuit bare crystalline includes the first serializer/deserializer (SerDes) circuit block.

According to one embodiment, the upper surface of package substrate in a two-dimensional plane by two quadrature axis be divided into four as Limit.First high-speed interface circuit bare crystalline includes being directly facing the first edge on the vertex of package substrate, wherein along first edge It is provided with first row input/output (I/O) pad.First high-speed interface circuit bare crystalline includes the second side perpendicular to first edge Edge, wherein being provided with second row I/O pad along second edge.

It is disposed with first group of soldered ball along two sides of the apex engagement in package substrate, and wherein in encapsulation base In one of quadrant in four quadrants on the upper surface of plate, first row I/O pad passes through multiple first trace electricity respectively It is connected to first group of soldered ball.

It is disposed with second group of soldered ball along one of two sides of the apex engagement in package substrate, and wherein In one of quadrant in four quadrants on the upper surface of package substrate, second row I/O pad passes through multiple respectively Two traces are electrically connected to second group of soldered ball.

Electronic Packaging further includes the second high-speed interface circuit bare crystalline close to the first high-speed interface circuit bare crystalline.Second High-speed interface circuit bare crystalline includes the 2nd SerDes circuit block.First high-speed interface circuit bare crystalline is electrically connected by redistribution layer structure It is connected to the second high-speed interface circuit bare crystalline.

According to one embodiment, a kind of Electronic Packaging is disclosed.The Electronic Packaging include rectangular package substrate and including The chip package of first high-speed interface circuit bare crystalline.The chip package is mounted on the upper surface of package substrate, wherein first is high Multiple I/O pads of fast interface circuit bare crystalline pass through its in four quadrants on the upper surface of the package substrate respectively In multiple traces in a quadrant be electrically connected to the soldered ball of the package substrate.

Electronic Packaging according to the present invention can mitigate signal skew and improve signal delay, improve the electricity of chip package Performance.

Read attached drawing and preferred embodiment shown in the accompanying drawings it is described in detail below after, those skilled in the art Member can undoubtedly have a clear understanding of the purpose of the present invention.

Detailed description of the invention

Fig. 1 is the perspective top view of Electronic Packaging according to an embodiment of the invention.

Fig. 2 is the schematic cross section along the line I-I' interception in Fig. 1.

Fig. 3 is the perspective view of Electronic Packaging according to an embodiment of the invention.

Specific embodiment

Below in the detailed description of the embodiment of the present invention, with reference to the attached drawing for constituting present invention a part, and its In shown by way of diagram particularly advantageous embodiment of the invention may be implemented.

The embodiment of the present invention sufficiently is described in detail so that those skilled in the art can implement, it should be appreciated that Also can use other embodiments and can carry out without departing from the spirit and scope of the present invention mechanically, structure Change in upper and program.Therefore, described in detail below to be not be considered in a limiting sense, the scope of embodiments of the invention It is defined solely by the appended claims.

It will be appreciated that though term first, second, third, main, secondary etc. may be used herein to describe various members Part, component, regions, layers, and/or portions, but these elements, component, regions, layers, and/or portions should not be by the limits of these terms System.These terms are only used to by an element, component, region, layer or part and another element, component, region, layer or part It distinguishes.Therefore, under the introduction for not departing from thought of the invention, discussed below first or main element, component, region, Layer or part are referred to as second or secondary element, component, region, layer or part.

The relationship of an elements or features and another elements or features shown in the drawings for ease of description, herein Used spatially relative term, " under ", " lower section ", " lower part ", " being lower than ", " on ", " top ", " top " etc..It answers Work as understanding, other than orientation shown in figure (orientation), spatially relative term is intended to include in use or operation The different direction of device.For example, if the device in figure is reversed, be described as being located at other elements or feature " under " Or the element of " lower section " or " following " will be directed positioned at other elements or feature " on " or " top ".Therefore, exemplary art Language " following " and " lower section " may include above and below two orientation.Device can otherwise orient (be rotated by 90 ° or With other orientation), and space used herein is interpreted accordingly and describes language relatively.Also, it is to be understood that when some layer is referred to as Two layers " between " when, it can be the sole layer between two layers, or there may also be one or more middle layers.

Terms used herein are only used for description specific embodiment, it is no intended to limit thought of the invention.It uses herein Singular " one " and "the" be intended to also include plural form, unless the context clearly indicates otherwise.It will be further understood that, When using term " includes " in the present specification, refer to there are the feature, integer, step, operation, element and/or component, But other one or more features, integer, step, operation, element, component and/or group are not precluded the presence or addition of.This paper institute The term "and/or" used includes any and all combinations of one or more projects in listed relevant item, and can contract It is written as "/".

It should be appreciated that when certain element or layer referred to as " on being located at ... ", " being connected to ", " being couple to " or " neighbouring " are another When a element or layer, it can be directly connected to thereon, with another element or layer located immediately at another element or layer, coupling It connects or adjacent, or may exist intermediary element or layer.On the contrary, when element is referred to as " on another element or layer ", Or when " being directly connected to ", " being directly coupled to " or " close to " another element or layer, then intermediary element or layer is not present.

Serializer/deserializer (SerDes) is common a pair of functional block in high-speed communication, limited defeated to compensate Enter/exports.These blocks change data in each direction between serial data and parallel interface.Term " SerDes " is often referred to The interface used in various technologies and application.Being mainly used for of SerDes provides number on single route or differential pair of lines According to transmission, so that I/O pin (pin) and the quantity of interconnection (interconnect) minimize.The transmission of SerDes data is realized can To be used for various communication systems and equipment, such as mobile device, desktop computer and server, computer network and telecommunications network Network.

Electronic Packaging of the disclosed operation in gigabit per second (Gigabit-per-second, Gbps) data rate, energy It enough reduces signal skew and therefore improves the electrical property of chip package, this is suitable for high data rate communication application, including but not It is limited to, ultra-large data center, the very-high performance network switch, router or calculating application program and 4G and 5G service mention For quotient (backhaul (backhaul)) infrastructure, the application of AI/ deep learning and novel calculating application.

Referring to figs. 1 to Fig. 3.Fig. 1 is the perspective top view of Electronic Packaging according to an embodiment of the invention.Fig. 2 is edge The schematic cross section of line I-I' interception in Fig. 1.Fig. 3 is the perspective of Electronic Packaging according to an embodiment of the invention Figure.

As shown in Figure 1 to Figure 3, according to one embodiment, Electronic Packaging 1 includes chip package 10, and chip package 10 is to fall Cored sheet mode (flip-chip manner) is mounted on the upper surface 201 of package substrate 20.When viewed from above, chip Encapsulation 10 and package substrate 20 all have rectangular shape.For example, chip package 10 and package substrate 20 may have four sides The square shape of equal length.There are four side (side) 10a~10d for the tool of chip package 10.There are four the tools of package substrate 20 Vertex A~D, and four side 20a~20d between four vertex A~D respectively.

As shown in Figure 1, the upper surface 201 of package substrate 20 can be in two-dimensional surface (being parallel to upper surface 201) by two A quadrature axis (with reference to X and Y-axis) is divided into four 90 degree of quadrant Q₁~Q₄.Quadrant Q₁And Q₃It is diagonally to each other opposite.Quadrant Q₂With Q₄It is diagonally to each other opposite.Referring to figs. 1 to Fig. 3, the reference Z axis orthogonal with upper surface 201 or X-Y plane is shown.

According to one embodiment, package substrate 20 be can be including laminated organic materials (laminated organic ) or the organic substrate of core (core) 200 (epoxy resin etc.) material.As shown in Fig. 2, multiple soldered ball (solder Ball it) 230 can be set on the bottom surface 202 of package substrate 20.Chip package 10 passes through multiple solder joint (solder Joint) or convex block (bump) 30 is mounted on the upper surface 201 of package substrate 20.It provides bottom filler (underfill) 40, to fill the gap between chip package 10 and package substrate 20 (or interval).Package substrate 20 may include multiple traces Layer, such as trace 211 and 221.

In Fig. 2, trace 211 is intended to be arranged in the top of multiple trace layers of package substrate 20.In general, trace 211 are covered by the protective layer 280 of solder mask (solder mask) etc., and but not limited to this.Convex block 30, which is joined to, to be located at The correspondence bump pad 210 of one far-end of trace 211, and it is aligned.Trace 211 extends towards the turning at the A of vertex Or extend towards two adjacent sides 20a and 20b of corner.

Trace 211 for being electrically connected corresponding bump pad 210 is generally arranged in the quadrant Q2 of exemplary presentation.Trace 211 are conductively coupled to connection pad 212.Electroplating ventilating hole (plated through hole, PTH) 213 can be provided, connection is welded Disk 212 is electrically connected to the solder ball pads 214 at the bottom surface 202 of package substrate 20.Soldered ball 230 is welded in solder ball pads 214, Further to be connected with system board or printed circuit board (printed circuit board, PCB).

For simplicity, it only presents only in perspective view as shown in Figure 1 in quadrant Q₂Interior trace and soldered ball cloth It sets.Soldered ball 230 is not explicitly shown in Fig. 1.It should be understood, however, that since connection pad 212 and solder ball pads 214 are right It is neat and thus be aligned with soldered ball 230, so in Fig. 1 each connection pad 212 position, each soldered ball 230 is indicated generally Position.It should be appreciated that in other embodiments, in quadrant Q₂In configuration can be used in other quadrants Q₁、Q₃And Q₄In.

As shown in figures 1 and 3, chip package 10 and package substrate 20 can have identical central point CP, therefore encapsulate Substrate 20 and chip package 10 have arranged coaxial (concentric configuration), and wherein the chip package 10 is opposite There is angle offset in package substrate 20.According to one embodiment, it is preferable that chip package 10 is relative to package substrate 20 around Z Substantially 45 degree of axis rotation.Here substantially 45 degree refer to chip package 10 relative between the angle offset of package substrate 20 and 45 degree Difference skilled artisans appreciate that predictive error within the scope of, even if chip package 10 is relative to package substrate 20 Angle offset be not point-device 45 degree, as long as within an acceptable error range, also substantially can be realized the present invention Predetermined purpose and technical effect.According to one embodiment, either of which in four side 10a~10d of chip package 10 It is not parallel with any one of four side 20a~20d of package substrate 20.

Rotary chip encapsulation 10, so that one side 10a is directly facing the turning at the vertex A of package substrate 20.Envelope Two side 20a and 20b of dress substrate 20 are connected at the A of vertex.Two sides 20a and 20b limit the boundary of 90 degree of quadrant Q2.

According to one embodiment, chip package 10 includes the first high-speed interface circuit bare crystalline (die) 11, can be higher than It is operated under the frequency of 500MHz with the high data transfer rates of at least 1000Mbps.As shown in Fig. 2, the first high-speed interface circuit Bare crystalline 11 can be encapsulated in moulding compound 50.According to one embodiment, the first high-speed interface circuit bare crystalline 11 includes first serial Device/deserializer (SerDes) circuit block, the first SerDes circuit block is close to be directly facing at the vertex A of package substrate 20 The side 10a at turning.

According to one embodiment, as shown in Figure 1, the first high-speed interface circuit bare crystalline 11 includes being directly facing package substrate 20 Vertex A at turning first edge 11a, perpendicular to first edge 11a and be joined to first edge 11a second edge 11b, Perpendicular to first edge 11a and it is joined to the third edge 11c of first edge 11a.According to one embodiment, first edge 11a Parallel with the side 10a of chip package 10, second edge 11b is parallel with the side 10d of chip package 10, third edge 11c with The side 10b of chip package 10 is parallel.Second edge 11b and third edge 11c and pair extended between vertex A and vertex C Linea angulata DL is parallel.

According to one embodiment, as shown in Figure 1, first row input/output (I/O) pad 111a is set along first edge 11a It sets, second row I/O pad 111b is arranged along second edge 11b, and third is arranged I/O pad 111c and is arranged along third edge 11c.It can be with Understand, the bottom of the first high-speed interface circuit bare crystalline 11 is arranged in these I/O pads.

According to one embodiment, can the upper surface 201 of the first high-speed interface circuit bare crystalline 11 and package substrate 20 it Between provide redistribution layer (redistribution layer, RDL) structure 100, to be fanned out to (fan-out) I/O pad.This field Known RDL structure 100 can be made of the interconnection structure in dielectric layer and dielectric layer, which is used for will be high The I/O pad of fast interface circuit bare crystalline 11 is electrically connected to the respective bump pad 101 to form solder joint (solder joint) 30.Root According to one embodiment, chip package 10 can be fanned out to formula wafer-level packaging (fan-out wafer level package, FOWLP)。

According to one embodiment, the first SerDes circuit block of the first high-speed interface circuit bare crystalline 11, edge 11a~11c, I/O pad row 111a~111c is generally arranged at exemplary quadrant Q₂It is interior.It is appreciated that chip package 10 is reversed as it effectively (active surface) is mounted in a flip-chip manner on the upper surface 201 of package substrate 20 on surface.

As shown in Figure 1, according to one embodiment, first group of soldered ball P₁(soldered ball is not explicitly shown in Fig. 1, but with connection Pad 212a alignment) it is arranged along two the sides 20a and 20b engaged at the vertex A of package substrate 20.It is arranged in high quick access First row I/O pad 111a at the first edge 11a of mouth circuit bare crystalline 11 passes through respectively on the upper surface 201 of package substrate 20 Quadrant Q₂Interior trace 211a is electrically connected to first group of soldered ball P₁。

According to one embodiment, second group of soldered ball P₂(soldered ball is not explicitly shown in Fig. 1, but with connect 212b pairs of pad It is arranged together) along the side 20a adjacent with the turning at the A of vertex.Second row I/O pad 111b passes through package substrate 20 respectively Quadrant Q on upper surface 201₂Interior trace 211b is electrically connected to second group of soldered ball P₂。

According to one embodiment, third group soldered ball P₃(soldered ball is not explicitly shown in Fig. 1, but with connect 212c pairs of pad It is arranged together) along the side 20b adjacent with the turning at the A of vertex.Third row I/O pad 111c passes through package substrate 20 respectively Quadrant Q on upper surface 201₂Interior trace 211c is electrically connected to third group soldered ball P₃。

According to one embodiment, as shown in Fig. 2, chip package 10 can also include close to the first high-speed interface circuit bare crystalline 11 the second high-speed interface circuit bare crystalline 12.Second high-speed interface circuit bare crystalline 12 may include SerDes circuit block and can be with Quadrant Q in the upper surface of package substrate 20 201₄In have similar trace and ball layout.First high-speed interface circuit bare crystalline 11 can be electrically connected to the second high-speed interface circuit bare crystalline 12 by RDL structure 100.For example, the first high-speed interface circuit bare crystalline 11 I/O pad 111c is electrically connected to the I/O of the second high-speed interface circuit bare crystalline 12 by the interconnection line 103 in RDL structure 100 Pad 121c.

It is advantageous using the present invention, because of the corresponding mark by the chip package configuration for providing rotation, on package substrate Line and ball layout concentrate on four quadrant Q₁~Q₄In in one of them, cause peak signal length to reduce 14.3% (for example, right In 60 × 60mm~90 × 90mm package substrate, from about 35mm to about 30mm) and trace length difference (maximum length subtracts Minimum length) being substantially reduced from 20mm to 13mm.Therefore, distortion can be mitigated, and Electronic Packaging can be significantly improved The signal delay and electrical property (for example, improving 18% or about -0.5dB) of SerDes circuit.

Those skilled in the art will readily appreciate that, can while retaining the teachings of the present invention to device and method into The a variety of modifications and changes of row.Therefore, above disclosure should be interpreted the only limit by scope of the appended claims and boundary System.