阅读说明：本技术 半导体封装结构及其制造方法 (Semiconductor package and its manufacturing method ) 是由 涂清镇 于 2018-08-28 设计创作，主要内容包括：本发明提供一种半导体封装结构,包括晶圆、图案化介电层、多个第二芯片以及底填胶体。晶圆包括多个第一芯片及将这些第一芯片分隔开来的多条切割道。各第一芯片上具有一芯片接合区。图案化介电层配置于晶圆上,并包括多个开口、多个点胶槽以及多个流道。开口分别暴露出芯片接合区。点胶槽分别位于切割道上。流道分别连通点胶槽与芯片接合区。各芯片接合区对应连通至少一点胶槽。第二芯片分别配置于芯片接合区。底填胶体位于点胶槽与流道内,并填充于第一芯片与第二芯片之间。本发明更提供一种半导体封装结构的制造方法。(The present invention provides a kind of semiconductor package, including wafer, pattern dielectric layer, multiple second chips and bottom filler body.Wafer includes multiple first chips and a plurality of Cutting Road of separating these first chips.There is a chip bonding area on each first chip.Pattern dielectric layer is configured on wafer, and including multiple openings, multiple glue grooves and multiple runners.Opening exposes chip bonding area respectively.Point glue groove is located on Cutting Road.Runner is respectively communicated with a glue groove and chip bonding area.Each chip bonding area correspondence is connected to a little less glue groove.Second chip is respectively arranged at chip bonding area.Bottom filler body is located in point glue groove and runner, and is filled between the first chip and the second chip.The present invention more provides a kind of manufacturing method of semiconductor package.)

1. a kind of semiconductor package characterized by comprising

Wafer, including multiple first chips and a plurality of Cutting Road for separating the multiple first chip, wherein each institute Stating has chip bonding area on the first chip；

Pattern dielectric layer is configured on the wafer, the pattern dielectric layer include it is multiple opening, multiple glue grooves and Multiple runners, the multiple opening expose the multiple chip bonding area respectively, and the multiple glue groove is located at described On multiple Cutting Roads, the multiple runner is respectively communicated with the multiple glue groove and the multiple chip bonding area, wherein each institute State at least one described glue groove of the corresponding connection in chip bonding area；

Multiple second chips, are respectively arranged at the multiple chip bonding area；And

Bottom filler body, in the multiple glue groove and the multiple runner and be filled in the multiple first chip with it is described Between multiple second chips.

2. semiconductor package according to claim 1, which is characterized in that wherein the multiple first chip respectively with The multiple first chip of adjacent two marks off multiple first chipsets area for one group, in each first chipset area In separate there is a described glue groove on the Cutting Roads of described two first chips, and on described two first chips The multiple chip bonding area is connected to described glue groove.

3. semiconductor package according to claim 1, which is characterized in that wherein the multiple first chip respectively with The multiple first chip of four of the matrix arrangement of 2x2 is one group and marks off multiple first chipsets area, in each described the The intersection for the two the multiple Cutting Roads for separating four first chips in one chipset area and intersecting with each other has one A described glue groove, and the multiple chip bonding area on four first chips is connected to described glue groove.

4. semiconductor package according to claim 1, which is characterized in that wherein the multiple second chip respectively with Multiple convex blocks are electrically connected the multiple first chip.

5. semiconductor package according to claim 1, which is characterized in that wherein the quantity of the multiple runner is corresponding Quantity in the multiple chip bonding area, and the quantity of the multiple runner is greater than the quantity of the multiple glue groove.

6. a kind of manufacturing method of semiconductor package characterized by comprising

Wafer is provided, including multiple first chips and a plurality of Cutting Road for separating the multiple first chip, wherein There is chip bonding area on each first chip；

Pattern dielectric layer is formed on the wafer, wherein the pattern dielectric layer includes multiple openings, multiple glue grooves And multiple runners, the multiple opening expose the multiple chip bonding area respectively, the multiple glue groove is located at On the multiple Cutting Road, the multiple runner is respectively communicated with the multiple glue groove and the multiple chip bonding area, wherein At least one described glue groove of each corresponding connection in the chip bonding area；

Multiple second chips are respectively configured to the multiple chip bonding area；And

Bottom filler body is configured to the multiple glue groove, makes the part bottom filler body from the multiple glue groove along described more A runner and toward the flowing of the multiple chip bonding area of connection, and be filled in the multiple first chip and the multiple second Between chip.

7. the manufacturing method of semiconductor package according to claim 6, which is characterized in that wherein form the pattern In the step of changing dielectric layer, further includes:

Dielectric layer is formed on the wafer；And

It removes the dielectric layer of the part on the wafer and forms the multiple opening, the multiple glue groove and described more A runner, wherein the multiple first chip is respectively with two adjacent the multiple first chips are one group and are marked off multiple First chipset area has one on the Cutting Road for separating described two first chips in each first chipset area Described glue groove, and the multiple chip bonding area on described two first chips is connected to described glue groove.

8. the manufacturing method of semiconductor package according to claim 6, which is characterized in that wherein form the pattern In the step of changing dielectric layer, further includes:

Dielectric layer is formed on the wafer；And

It removes the dielectric layer of the part on the wafer and forms the multiple opening, the multiple glue groove and described more A runner, wherein the multiple first chip respectively with four of the matrix arrangement of 2x2 the multiple first chips be one group and Multiple first chipsets area is marked off, separate four first chips in each first chipset area and is intersected with each other The intersection of two the multiple Cutting Roads has a described glue groove, and the multiple core on four first chips Chip bonding area is connected to described glue groove.

9. the manufacturing method of semiconductor package according to claim 6, which is characterized in that wherein the multiple second Chip is electrically connected the multiple first chip respectively with multiple convex blocks.

10. the manufacturing method of semiconductor package according to claim 6, which is characterized in that wherein the multiple stream The quantity in road corresponds to the quantity of the multiple chip bonding area, and the quantity of the multiple runner is greater than the multiple glue groove Quantity.

Technical field

The present invention relates to a kind of semiconductor package and manufacturing method more particularly to a kind of half for wafer-level packaging Conductor package structure and its manufacturing method.

Background technique

As the demand of electronic product is towards multifunction, signal transmission high speed and circuit unit densification, and Electronic product it is lightening, current structure dress technology gradually move towards single structure and fills system (System in Package, SIP) be Multiple electronic building bricks are stacked in same structure dress by system conformity stage.Stacking used at present for example has stacked chip Storehouse.For being attached at wafer (Chip on Wafer, CoW) with chip, there are multiple first chips on wafer (Wafer), it is more A second chip is respectively docked on these first chips of wafer (Wafer), and is inserted bottom filler body and fixed, thereafter edge again The Cutting Road of wafer be cut into multiple semiconductor packages.In existing semiconductor package, each first chip The upper dispensing region that can reserve certain size, and dispenser need to correspond to the dispensing region of each first chip and configure bottom filler one by one Body jointly influences the size of existing semiconductor package, and dispensing institute so that the size of the first chip is difficult to reduce It takes time and also can not effectively be reduced using glue amount, so that production efficiency can not be promoted.

Summary of the invention

The present invention be directed to a kind of semiconductor package, size can reduce and have the production efficiency promoted.

The present invention be directed to a kind of manufacturing methods of semiconductor package, can produce above-mentioned semiconductor packages knot Structure.

According to an embodiment of the invention, semiconductor package, including wafer, pattern dielectric layer, multiple second chips And bottom filler body.Wafer includes multiple first chips and a plurality of Cutting Road of separating these first chips.Each There is a chip bonding area on one chip.Pattern dielectric layer is configured on wafer.Pattern dielectric layer include it is multiple opening, it is more A glue groove and multiple runners.These openings expose these chip bonding areas respectively.These glue grooves are located at these On Cutting Road.These runners circulate these glue grooves and these chip bonding areas respectively.The corresponding connection in each chip bonding area is at least Some glue grooves.These second chips are respectively arranged at these chip bonding areas.Bottom filler body is located at these glue grooves and these streams In road, and it is filled between these first chips and these second chips.

According to an embodiment of the invention, the manufacturing method of semiconductor package, including the following steps: provide wafer, packet The a plurality of Cutting Road for including multiple first chips and separating these first chips, wherein having a core on each first chip Chip bonding area；Pattern dielectric layer is formed on wafer, wherein pattern dielectric layer include multiple openings, multiple glue grooves and Multiple runners, these openings expose these chip bonding areas respectively, these glue grooves are located on these Cutting Roads, these Runner is respectively communicated with these glue grooves and these chip bonding areas, and each chip bonding area correspondence is connected to a little less glue groove；Point Multiple second chips are not configured to these chip bonding areas；And one bottom filler body of configuration fills out part bottom to these glue grooves Colloid is flowed along these runners toward these chip bonding areas of connection from these glue grooves, and is filled in these the first chips Between these second chips.

Based on the manufacturing method of above-mentioned, of the invention semiconductor package and semiconductor package, by wafer On pattern dielectric layer formed expose chip bonding area opening, point glue groove and connectivity points glue groove and chip bonding area stream Road, and a glue groove is configured on Cutting Road, it guides the bottom filler body for being configured at a glue groove by runner and flows into chip engagement Area.Therefore it is not required to reserve dispensing region on the first chip.In this way, the design on the surface of the first chip can be simplified, and the The size of one chip can be contracted by, and the size of semiconductor package is reduced.Further, since on the first chip not Dispensing region need to be reserved, therefore the design of the first chip on the surface can be made more to have nargin.In addition, multiple first chips can be with A shared glue groove carries out the filling processing procedure of bottom filler body.Therefore, it is possible to reduce the quantity of point glue groove setting can more be reduced Time needed for number for dispensing glue and glue amount, shortening dispensing simultaneously promotes efficiency for dispensing glue, to promote the life of semiconductor package Produce efficiency.

Detailed description of the invention

Comprising attached drawing to further understand the present invention, and attached drawing is incorporated to and in this specification and constitutes one of this specification Point.Detailed description of the invention the embodiment of the present invention, and principle for explaining the present invention together with the description.

Figure 1A is shown as the upper schematic diagram of wafer；

Figure 1B is shown as the partial cutaway schematic of the wafer of Figure 1A；

Fig. 2, Fig. 3 B, Fig. 4 B, Fig. 5 B are shown as the partial cutaway schematic of the manufacturing method of semiconductor package；

It is regarded on the partial enlargement for the semiconductor package that Fig. 3 A, Fig. 4 A, Fig. 5 A are shown as Fig. 3 B, Fig. 4 B, Fig. 5 B Schematic diagram；

Fig. 6 is shown as partial cutaway schematic of the semiconductor package along hatching B-B ' of Fig. 5 A；

Fig. 7 is shown as partial cutaway schematic of the semiconductor package along hatching C-C ' of Fig. 5 A；

Fig. 8 is shown as the partial enlargement upper schematic diagram in the first chipset area.

Drawing reference numeral explanation

10: semiconductor package；

20: dispenser；

100: wafer；

105, the 105a: the first chipset area；

110: the first chips；

112: chip bonding area；

120: Cutting Road；

130: pattern dielectric layer；

130 ': dielectric layer；

132: opening；

134,134a: point glue groove；

136,136a: runner；

140: the second chips；

142: convex block；

150: bottom filler body；

A-A ', B-B ', C-C ': hatching；

D1: first direction；

D2: second direction.

Specific embodiment

With detailed reference to exemplary embodiment of the invention, the example of exemplary embodiment is illustrated in attached drawing.Only It is possible that same components symbol is used to indicate same or similar part in the accompanying drawings and the description.

Figure 1A is shown as the upper schematic diagram of wafer.Figure 1B is shown as the partial cutaway schematic of the wafer of Figure 1A.Fig. 2, Fig. 3 B, Fig. 4 B and Fig. 5 B are shown as the partial cutaway schematic of the manufacturing method of semiconductor package.Fig. 3 A, Fig. 4 A and Fig. 5 A is shown as the partial enlargement upper schematic diagram of the semiconductor package of Fig. 3 B, Fig. 4 B and Fig. 5 B.Specifically, Fig. 3 B, Fig. 4 B and Fig. 5 B are shown as office of the semiconductor package along hatching A-A ' of Fig. 3 A, Fig. 4 A and Fig. 5 A Portion's diagrammatic cross-section.The manufacturing method of the semiconductor package 10 of the present embodiment includes the following steps: firstly, providing a wafer 100.In the present embodiment, wafer 100 includes multiple first chips 110 and separates these first chips 110 more Cutting Road 120 has a chip bonding area 112 on each first chip 110.It should be noted that, Figure 1A is schematically herein Multiple Cutting Roads 120 with the first chip 110 of matrix arrangement and a plurality of crossed loops around each first chip 110 are shown, but Invention is not limited thereto.Separated in addition, Figure 1B schematically shows two the first chips 110 by a Cutting Road 120, but this Invention is not limited.Also that is, the quantity of these first chips 110 and these Cutting Roads 120, arrangement mode and size ratio Example shown in Figure 1A and Figure 1B not to be limited.

Specifically, with the separation of Cutting Road 120 between these first chips 110 of wafer 100, so as to after dicing can shape At independent chip.In other words, region of the Cutting Road 120 between the first adjacent chip 110.In addition, Cutting Road 120 Around four sides of the first chip 110, a waffle-like pattern is constituted, but invention is not limited thereto.

Then, a pattern dielectric layer 130 is formed in (as shown in Figure 3A) on wafer 100.It please refer to Fig. 2, above-mentioned shape At the step of pattern dielectric layer 130 include formed on 130 ' Yu Jingyuan 100 of a dielectric layer.The material of above-mentioned dielectric layer 130 ' can For general sensing optical activity photoresist, polyimides (polyimide, PI) layer or polyphenyl oxazole (Polybenzoxazole, PBO) layer, then a light shield (not shown) is provide on dielectric layer 130 ', and is exposed (Exposure) program.The pattern of light shield corresponds to the pattern for the wafer 100 to be exposed.

Then, developed the program of (Develop), unexposed dielectric layer 130 ' is dissolved and removed with developer solution. Please refer to Fig. 2, Fig. 3 A and Fig. 3 B, for example, remove wafer 100 on part of dielectric layer 130 ' and formed it is multiple opening 132, Multiple glue grooves 134 and multiple runners 136.Then, solidify the dielectric layer that (Curing) is not removed by way of heating 130 ', then for example, by be oxygen plasma mode to cured dielectric layer 130 ', these opening 132, these glue grooves 134 and These runners 136 are surface-treated, and pattern dielectric layer 130 can be completed.

In the present embodiment, pattern dielectric layer 130 includes multiple openings 132, multiple glue grooves 134 and multiple runners 136.These openings 132 expose the chip bonding area 112 on these first chips 110 respectively.In addition, these glue grooves 134 It is respectively arranged on these Cutting Roads 120.These runners 136 respectively correspond connection these glue grooves 134 and these 132 institutes of opening These chip bonding areas 112 exposed, and each chip bonding area 112 corresponds at least one point glue groove 134 of connection.

It is worth noting that, in the present embodiment, multiple first chips 110 are respectively with adjacent two these first chips 110 mark off multiple first chipsets area 105 for one group.For example, as shown in Figure 3A, with the phase on a first direction D1 For two first adjacent chips 110 are one group, two the first chips 110 in each first chipset area 105 are with a Cutting Road 120 separate, but invention is not limited thereto.In other embodiments, the first chipset area 105 can also be in a second direction D2 Two adjacent the first chips 110 are one group.First direction D1 is perpendicular to second direction D2.In the present embodiment, each first core Separating in the area Pian Zu 105 has glue groove 134 on the Cutting Road 120 of two the first chips 110.For example, glue groove is put 134 are overlapped in Cutting Road 120, and are located between two the first chips 110, but invention is not limited thereto.Two runners 136 divide Chip bonding area 112 in other connectivity points glue groove 134 and two the first chips 110.In other words, each first chipset area 105 These chip bonding areas 112 on two the first chips 110 are connected to glue groove 134.Specifically, corresponding chip bonding area 112 opening 132, point glue groove 134 and runner 136 can communicate with each other in the first direction dl, and in pattern dielectric layer A channel patterns are formed on 130.

Fig. 4 A and Fig. 4 B is please referred to, then, is respectively configured on multiple second chips 140 to these first chips 110 These chip bonding areas 112.In the present embodiment, the size of the first chip 110 be greater than the second chip 140 size, size compared with The second small chip 140 is covered on larger-size first chip 110.As shown in Figure 4 B, the second chip 140 is with multiple convex blocks 142 are electrically connected the first chip 110.Specifically, the first chip 110 may include multiple first in chip bonding area 112 Connection pad (does not indicate), and the second chip 140 also includes multiple second connection pads (not indicating).Multiple convex blocks 142 can be set in multiple On second connection pad and be electrically connected the first connection pad keeps the second chip 140 electrical with the first connection pad and the second connection pad of electrically conducting It is connected to the first chip 110, but invention is not limited thereto.

In the present embodiment, convex block 142 can be plated bumps, tie lines convex block or solder bump, material may include gold, Silver, copper, tin, nickel or combinations thereof.In attached drawing of the present invention, 142 system of convex block is enumerated as square, however, its face shaping Not only may be molded to spherical, cylindric or dome column, selected by material single kind of metal material or use also can be used Two or more metal material electroforming, for example, forming one layer of tin (Solder in copper post (Copper Pillar) Cap) or copper post outer wall covers one layer of gold.

Fig. 5 A and Fig. 5 B is please referred to, finally, one bottom filler body 150 (underfill) of configuration makes portion to point glue groove 134 Bottom filler body 150 is divided to flow from glue groove 134 along runner 136 toward the chip bonding area 112 of connection.It for example, can be with Bottom filler body 150 is instilled in point glue groove 134 by dispenser 20 (as shown in Figure 5 B), but invention is not limited thereto.At this In embodiment, in each first chipset area 105, bottom filler body 150 is along two runners 136 from point glue groove 134 toward corresponding Two chip bonding areas 112 are flowed, and the gap being filled between corresponding first chip 110 and the second chip 140, with cladding These convex blocks 142 cause bottom filler body 150 to be located in point glue groove 134 and runner 136 and are filled in the first chip 110 and second Between chip 140.So far, it has been substantially completed the production of semiconductor package 10.The material of bottom filler body 150 is, for example, epoxy Resin (Epoxy).

In the present embodiment, when bottom filler body 150 is configured at glue groove 134 by dispenser 20, bottom filler body 150 can be first It is placed in a glue groove 134, in the chip bonding area 112 exposed further along 136 inlet opening 132 of runner.Flow into chip engagement The bottom filler body 150 in area 112 can contact gap small between the first chip 110 and the second chip 140, and by between gap Capillary force guidance, inserts the gap between the first chip 110 and the second chip 140, provides the first chip 110 and the second chip Fixed effect between 140.Bottom filler body 150 can coat convex block 142 in turn to provide buffering, dust-proof and moisture-proof protection effect Fruit promotes the reliability of semiconductor package 10.

In addition, in the present embodiment, as shown in Figure 5A, glue groove 134 is connected to adjacent two by two runners 136 The chip bonding area 112 of a first chip 110, however, the present invention is not limited thereto.In other words, the quantity of these runners 136 is corresponding In these chip bonding areas 112 quantity (such as: the quantity of runner 136 be equal to chip bonding area 112 quantity), and these flow The quantity in road 136 is greater than the quantity of these glue grooves 134.Whereby, two adjacent the first chips 110 can pass through a dispensing The filling processing procedure of the progress bottom filler body 150 of slot 134.

Fig. 6 is shown as partial cutaway schematic of the semiconductor package along hatching B-B ' of Fig. 5 A.

Fig. 7 is shown as partial cutaway schematic of the semiconductor package along hatching C-C ' of Fig. 5 A.Please refer to Fig. 5 A, Fig. 6 and Fig. 7, in the present embodiment, hatching B-B ' are parallel to hatching C-C ', extend each along second direction D2.Fig. 6 institute It is shown as pattern dielectric layer 130 and is formed by a glue groove 134 on Cutting Road 120.Fig. 7 show pattern dielectric layer 130 and exists Runner 136 is formed by first chip 110.In the present embodiment, on second direction D2, the maximum width of glue groove 134 is put Greater than the maximum width of runner 136.That is, the bore of 136 connectivity points glue groove 134 of runner is less than on second direction D2 The maximum width of point glue groove 134.However invention is not limited thereto, in other embodiments, on second direction D2, puts glue groove 134 maximum width can also be equal to the maximum width of runner 136.In other words, on second direction D2, glue groove 134 is put Width can be greater than or equal to the width of runner 136.

In this way, by the width of glue groove 134 be greater than runner 136 width for, when bottom filler body 150 be configured at width compared with When big point glue groove 134, the lesser runner 136 of width can guide bottom filler body 150 logical from point glue groove 134 by capillary phenomenon Runner 136 is crossed, then flows into chip bonding area 112.Therefore, flow velocity of the bottom filler body 150 in runner 136 can be promoted, and be increased Bottom filler body 150 inserts the efficiency between the first chip 110 and the second chip 140, and the time needed for shortening dispensing.It needs herein It is partially formed in pattern dielectric layer 130 it is noted that Fig. 5 A schematically shows bottom filler body 150, but bottom filler body 150 can not also be excessive in pattern dielectric layer 130.Compared to the dispensing processing procedure of existing semiconductor package, at this In embodiment, since bottom filler body 150 can be patterned the point glue groove 134 of dielectric layer 130 and the guidance of runner 136 connects to chip Area 112 is closed, therefore bottom filler body 150 can be reduced and arbitrarily flowed and excessive degree.

Referring again to Fig. 5 A, in the present embodiment, point glue groove 134 can extend along second direction D2.For example, As shown in Figure 5A, point glue groove 134 may be, for example, strip in the pattern in vertical view, but invention is not limited thereto.In other realities It applies in example, point glue groove 134 may be round or ellipse etc. in the pattern in vertical view.Whereby, the extension width of glue groove 134 is put The effect of the buffering of bottom filler body 150 can be provided.In this way, when bottom filler body 150 is configured at glue groove 134, bottom filler body 150 Dispensing slot 134 and runner 136 are further overflowed in diffusion that can be average to multiple directions outside reduction bottom filler body 150 Degree.

In conclusion semiconductor package 10 of the invention can be matched point glue groove 134 by pattern dielectric layer 130 It is placed on Cutting Road 120, then the guidance of bottom filler body 150 in glue groove 134 is flowed by chip bonding area 112 by runner 136, Therefore it is not required to reserve dispensing region on the first chip 110.In this way, the design on the surface of the first chip 110 can be simplified, and The size of first chip 110 can be contracted by, and the size of semiconductor package 10 is reduced.Further, since first It is not required to reserved dispensing region on chip 110, therefore the design of the first chip 110 on the surface can be made more to have nargin.In addition, by Correspond to the quantity of chip bonding area 112 in the quantity of above-mentioned runner 136, and the quantity of runner 136 is greater than the number of point glue groove 134 Amount, that is to say, that multiple first chips 110 can share the filling processing procedure that glue groove 134 carries out bottom filler body 150.Such as This, compared to the existing technology for reserving dispensing region on each first chip 110, semiconductor package 10 of the invention can be with The quantity that glue groove 134 is arranged is reduced to less than to the quantity of the first chip 110.Therefore, it is possible to reduce number and glue for dispensing glue Time needed for amount, shortening dispensing simultaneously promotes efficiency for dispensing glue, to promote the production efficiency of semiconductor package 10.In addition, The range of glue groove 134 is done to the effect for extending and can also providing bottom filler body 150 and buffering along the direction that Cutting Road 120 extends, Reduce the degree that dispensing slot 134 and runner 136 are overflowed outside bottom filler body 150.

It should be noted that, following embodiments continue to use the reference numerals and partial content of previous embodiment, wherein adopting herein Be denoted by the same reference numerals identical or approximate component, illustrates can refer to about the part that same technique content is omitted aforementioned Embodiment, it is no longer repeated in following embodiments.

Fig. 8 is shown as the partial enlargement upper schematic diagram in the first chipset area.Fig. 5 A and Fig. 8 are please referred to, the present embodiment First chipset area 105a is similar to the first chipset area 105 in Fig. 5 A, is in place of the two main difference: in the present embodiment In, these first chips 110 are respectively with four the first chips 110 of the matrix arrangement of 2x2 are one group and mark off multiple the One chipset area 105a.It should be noted that, Fig. 8 of the invention is for the sake of clear expression herein, it is schematically shown two Cutting Road 120 is located between four the first chips 110 of matrix arrangement, and remaining is omitted around these four first chips 110 a plurality of Cutting Road 120.

In the present embodiment, four the first chips 110 are separated in each first chipset area 105a and are intersected with each other two The intersection of Cutting Road 120 has a glue groove 134a, and these chip bonding areas on this four the first chips 110 112 connectivity points glue groove 134a.Specifically, four runner 136a are respectively communicated with a glue groove 134a and corresponding four openings 132 The chip bonding area 112 exposed.Whereby, when bottom filler body 150 is configured at a glue groove 134a, bottom filler body 150 can be with The chip bonding area 112 that is exposed of opening 132 of connection is flowed by runner 136a, and is filled in the first chip 110 and the Gap between two chips 140.In this way, the first chipset area 105a can obtain same technique effect with above-described embodiment.

In the present embodiment, point glue groove 134a can along two Cutting Roads 120 to intersect with each other in first direction D1 with And extend on second direction D2.For example, as shown in figure 8, point glue groove 134a in the pattern in vertical view may be, for example, cross, But invention is not limited thereto.In other embodiments, point glue groove 134a may be round, oval in the pattern in vertical view Or star etc..Whereby, the point glue groove 134a extension width on D1 and second direction D2 in a first direction, can provide bottom filler body The effect of 150 bufferings.In this way, bottom filler body 150 can be to multiple directions when bottom filler body 150 is configured at a glue groove 134a Average diffusion reduces the degree that dispensing slot 134a and runner 136a is overflowed outside bottom filler body 150.

In conclusion the manufacturing method of semiconductor package and semiconductor package of the invention, by wafer On pattern dielectric layer formed expose chip bonding area opening, point glue groove and connectivity points glue groove and chip bonding area stream Road, and a glue groove is configured on Cutting Road, it guides the bottom filler body for being configured at a glue groove by runner and flows into chip engagement Area.Therefore it is not required to reserve dispensing region on the first chip.In this way, the design on the surface of the first chip can be simplified, and the The size of one chip can be contracted by, and the size of semiconductor package is reduced.Further, since on the first chip not Dispensing region need to be reserved, therefore the design of the first chip on the surface can be made more to have nargin.In addition, multiple first chips can be with A shared glue groove carries out the filling processing procedure of bottom filler body.Therefore, it is possible to reduce the quantity of point glue groove setting can more be reduced Time needed for number for dispensing glue and glue amount, shortening dispensing simultaneously promotes efficiency for dispensing glue, to promote the life of semiconductor package Produce efficiency.Further, since the bore of runner connectivity points glue groove is less than the maximum width of point glue groove, therefore runner can guide bottom to fill out Colloid flows into chip bonding area by runner, increases the flow velocity of bottom filler body.In addition, bottom filler body is drawn from glue groove is put by runner It is directed at chip bonding area, it is possible to reduce bottom filler body arbitrarily flows and excessive degree.In addition, point glue groove can also provide bottom and fill out The cushion space of colloid average diffusion.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.