阅读说明：本技术 半导体装置封装件和制造半导体装置封装件的方法 (The method of semiconductor device package and manufacture semiconductor device package ) 是由 吕文隆 于 2018-07-19 设计创作，主要内容包括：一种半导体衬底包含介电层、第一导电层、第一阻挡层和导电柱。所述介电层具有第一表面和与所述第一表面相对的第二表面。所述第一导电层邻近于所述介电层的所述第一表面安置。所述第一阻挡层安置于所述第一导电层上。所述导电柱安置于所述第一阻挡层上。所述导电柱的宽度等于或小于所述第一阻挡层的宽度。(A kind of semiconductor substrate includes dielectric layer, the first conductive layer, the first barrier layer and conductive column.The dielectric layer has first surface and the second surface opposite with the first surface.First conductive layer is disposed adjacent to the first surface of the dielectric layer.First barrier layer is placed on first conductive layer.The conductive column is placed on first barrier layer.The width of the conductive column is equal to or less than the width on first barrier layer.)

1. a kind of semiconductor substrate, comprising:

Dielectric layer has first surface and the second surface opposite with the first surface；

First conductive layer, the first surface adjacent to the dielectric layer dispose；

First barrier layer is placed on first conductive layer；With

Conductive column is placed on first barrier layer,

Wherein the width of the conductive column is equal to or less than the width on first barrier layer.

2. semiconductor substrate according to claim 1, wherein

The conductive column has the first surface and second table opposite with the first surface contacted with first barrier layer Face；And

The first surface of the conductive column and the first surface of the dielectric layer are substantially coplanar.

3. semiconductor substrate according to claim 2 further comprises the second surface for being placed in the conductive column On conductive contact piece.

4. semiconductor substrate according to claim 1, wherein the first surface of the conductive column in the dielectric layer On outburst area include first barrier layer in the outburst area on the first surface of the dielectric layer.

5. semiconductor substrate according to claim 1, wherein first barrier layer has and to contact with the conductive column First surface, and the first surface on first barrier layer is exposed from the dielectric layer.

6. semiconductor substrate according to claim 5, wherein first conductive layer is placed in the dielectric layer, and institute The first surface of the first surface for stating the first barrier layer and the dielectric layer is substantially coplanar.

7. semiconductor substrate according to claim 1, wherein the conductive column includes:

Second conductive layer is contacted with first barrier layer；

Second barrier layer is placed on second conductive layer；With

Third conductive layer is placed on second barrier layer.

8. semiconductor substrate according to claim 7, wherein

Second conductive layer and the third conductive layer include: golden (Au), silver-colored (Ag), copper (Cu), platinum (Pt), palladium (Pd) or its Alloy；Or

Second barrier layer includes: nickel (Ni), titanium (Ti), tungsten (W) or its alloy.

9. semiconductor substrate according to claim 7, wherein the width of second conductive layer, second barrier layer The width of width and the third conductive layer is substantially the same.

10. semiconductor substrate according to claim 7, wherein

The thickness of second conductive layer is in the range of about 3 microns (μm) arrive about 20 μm；

The thickness on second barrier layer is in the range of about 1 μm to about 5 μm；And

The thickness of the third conductive layer is in the range of about 1 μm to about 3 μm.

11. semiconductor substrate according to claim 1, wherein first conductive layer is placed in the described of the dielectric layer On first surface.

12. semiconductor substrate according to claim 1, wherein first barrier layer includes: Ni, Ti, W or its alloy.

13. semiconductor substrate according to claim 1, wherein the thickness on first barrier layer is at about 1 μm to about 5 μm In range.

14. a kind of semiconductor device package, comprising:

Substrate, has first surface and the second surface opposite with the first surface, and the substrate includes

First conductive layer, the first surface adjacent to the substrate dispose；

First barrier layer is placed on first conductive layer；With

Conductive column is placed on first barrier layer,

Wherein the width of the conductive column is equal to or less than the width on first barrier layer；

Electronic building brick is placed on the second surface of the substrate and is electrically connected to first conductive layer.

15. semiconductor device package according to claim 14 further comprises the electronic building brick and the substrate The second surface between bottom filler.

16. semiconductor device package according to claim 15 further comprises be placed in the substrate described On two surfaces and the packaging body of the covering electronic building brick and the bottom filler.

17. semiconductor device package according to claim 14, wherein the conductive column is described the of the substrate Outburst area on one surface includes first barrier layer in the outburst area on the first surface of the substrate.

18. semiconductor device package according to claim 14, wherein first barrier layer has and the conduction The first surface of column contact, and the first surface of the first surface on first barrier layer and the substrate is generally It is coplanar.

19. semiconductor device package according to claim 14, wherein the conductive column includes:

Second conductive layer is contacted with first barrier layer；

Second barrier layer is placed on second conductive layer；With

Third conductive layer is placed on second barrier layer.

20. semiconductor device package according to claim 19, wherein the width of second conductive layer, described second The width of the width on barrier layer and the third conductive layer is substantially the same.

21. semiconductor device package according to claim 14, wherein first barrier layer includes: Ni, Ti, W or Its alloy.

22. a kind of method for manufacturing semiconductor device package, which comprises

(a) barrier layer is formed, the barrier layer has first surface and the second surface opposite with the first surface；

(b) the first conductive layer is formed on the first surface on the barrier layer；

(c) dielectric layer is formed to cover described the second of the barrier layer and first conductive layer and the exposure barrier layer Surface；With

(d) conductive column is formed on the second surface on the barrier layer.

23. according to the method for claim 22, wherein the barrier layer and first conductive layer pass through photoetching technique shape At.

24. according to the method for claim 22, wherein operation (d) further comprises:

The second conductive layer is formed on the surface substantially coplanar with the second surface on the barrier layer of the dielectric layer； With

A part of second conductive layer is etched, so that the width of second conductive layer is equal to or less than the barrier layer Width.

Technical field

The method that the disclosure relates generally to a kind of semiconductor device package and manufacture semiconductor device package, and The method for being related to the semiconductor device package comprising barrier structure and manufacture semiconductor device package.

Background technique

Semiconductor device package may include the soldered ball that electronic building brick is electrically connected to substrate.It is welded when being formed on the substrate When contact, it may occur that exudation (for example, during reflux course), this will cause not wish between two conductive gaskets The short circuit (that is, bridge joint) of prestige.In order to avoid bridging problem, anti-solder flux should be used.However, the use of anti-solder flux will increase semiconductor The manufacturing cost and thickness of device packaging part.In addition, due to, the thermal expansion coefficient (CTE) between anti-solder flux and substrate mismatches, Therefore warpage issues will occur, this can the interface further between anti-solder flux and substrate cause delamination.

Summary of the invention

In one or more embodiments, semiconductor substrate includes dielectric layer, the first conductive layer, the first barrier layer and conduction Column.Dielectric layer has first surface and the second surface opposite with first surface.First conductive layer adjacent to dielectric layer first Surface placement.First barrier layer is placed on the first conductive layer.Conductive column is placed on the first barrier layer.The width etc. of conductive column In or less than the first barrier layer width.

In one or more embodiments, semiconductor device package includes substrate and electronic building brick.Substrate has the first table Face and the second surface opposite with first surface.Substrate has the first conductive layer, the first barrier layer and conductive column.First conductive layer First surface adjacent to substrate disposes.First barrier layer is placed on the first conductive layer.Conductive column is placed in the first barrier layer On.The width of conductive column is equal to or less than the width on the first barrier layer.Electronic building brick is placed on the second surface of substrate and electricity It is connected to the first conductive layer.

In one or more embodiments, a kind of method for manufacturing semiconductor device package includes: (a) being formed and is stopped Layer, the barrier layer have first surface and the second surface opposite with first surface；(b) shape on the first surface on barrier layer At the first conductive layer；(c) dielectric layer is formed with covering barrier layer and the first conductive layer and the second surface on exposure barrier layer；With (d) conductive column is formed on the second surface on barrier layer.

Detailed description of the invention

When read in conjunction with the accompanying drawings, all aspects of this disclosure are best understood from described in detail below.It should be noted that various spies Sign may be not drawn on scale, and the size of various features can for discussion it is clear for the sake of and arbitrarily increase or reduce.

Figure 1A illustrates the viewgraph of cross-section of the semiconductor device package according to some embodiments of the present disclosure.

Figure 1B illustrates putting for a part of the semiconductor device package in Figure 1A according to some embodiments of the present disclosure Big view.

Fig. 2 illustrates the viewgraph of cross-section of the semiconductor device package according to some embodiments of the present disclosure.

Fig. 3 illustrates the viewgraph of cross-section of the semiconductor device package according to some embodiments of the present disclosure.

Fig. 4 illustrates the viewgraph of cross-section of the semiconductor device package according to some embodiments of the present disclosure.

Fig. 5 illustrates the viewgraph of cross-section of the semiconductor device package according to some embodiments of the present disclosure.

Fig. 6 illustrates the viewgraph of cross-section of the semiconductor device package according to some embodiments of the present disclosure.

Fig. 7 illustrates the viewgraph of cross-section of the electric device according to some embodiments of the present disclosure.

Fig. 8 A, Fig. 8 B, Fig. 8 C, Fig. 8 D, Fig. 8 E, Fig. 8 F and Fig. 8 F' illustrate the manufacture according to some embodiments of the present disclosure The method of semiconductor device package.

Fig. 9 A illustrates the semiconductor device package according to some embodiments of the present disclosure.

Fig. 9 B illustrates the semiconductor device package according to some embodiments of the present disclosure.

Same or similar element is indicated using common reference manuals through schema and detailed description.According to below in conjunction with attached The detailed description that figure is made will readily appreciate that the disclosure.

Specific embodiment

Figure 1A illustrates the viewgraph of cross-section of the semiconductor device package 1 according to some embodiments of the present disclosure.Semiconductor Device packaging part 1 includes substrate 10, conductive column 11, passivation layer 12, electronic building brick 13 and packaging body 14.

Substrate 10 can be such as printed circuit board, such as paper base copper foil laminates, composite copper foil laminates or polymer The fiberglass-based copper foil laminates of dipping.Substrate 10 may include interconnection structure, such as redistribution layer (RDL) or ground connection member Part.In some embodiments, substrate 10 is semiconductor substrate.In some embodiments, the surface 101 of substrate 10 is referred to as second Surface and the referred to as first surface of the surface of substrate 102.In some embodiments, substrate 10 arrives with a thickness of about 5 microns (μm) About 20 μm.

In some embodiments, as shown in fig. ib, illustrate the amplification view of a part of substrate 10 and conductive column 11 Figure, substrate 10 include conductive layer 10r, barrier layer 10b and dielectric layer 10d.Conductive layer 10r adjacent to the surface of substrate 10 102 (or The surface 102 of dielectric layer 10d) it disposes and is placed in dielectric layer 10d.Conductive layer 10r has back to the surface of conductive column 11 The 10r1 and surface 10r2 opposite with surface 10r1.In some embodiments, conductive layer 10r serves as the RDL of substrate 10 to provide Electrical connection.In some embodiments, conductive layer 10r is formed by the following terms or comprising the following terms: gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metal or alloy or two or more than two combination.In some embodiments, it leads Electric layer 10r with a thickness of about 1 μm to about 3 μm.

Barrier layer 10b is placed on the surface 10r2 of conductive layer 10r.In some embodiments, barrier layer 10b and conductive layer The surface 10r2 of 10r is contacted.In some embodiments, barrier layer 10b and the first metal layer 14a are conformal.For example, such as Figure 1B Shown in, conductive layer 10r and barrier layer 10b have common width D11.In some embodiments, the surface of barrier layer 10b The surface 102 of 10b2 and substrate 10 are substantially coplanar.In some embodiments, barrier layer 10b includes titanium (Ti), nickel (Ni), tungsten (W), other metal or alloy or two or more than two combination.In some embodiments, barrier layer 10b with a thickness of About 1 μm to about 5 μm.

Dielectric layer 10d covers a part of conductive layer 10r and a part of barrier layer 10b.In some embodiments, dielectric Layer 10d may include organic material, solder mask, polyimides (PI), epoxy resin, aginomoto accumulating film (ABF), one or more Mold compound, one or more preimpregnation composite fibre (for example, pre-soaking fibers), boron-phosphorosilicate glass (BPSG), silica, nitridation Silicon, silicon oxynitride, undoped silicate glass (USG), any combination thereof etc..The example of mold compound may include, but are not limited to Epoxy resin comprising filler dispersed therein.The example of pre-soaking fiber may include, but are not limited to by stack or be laminated one or Multiple preimpregnation materials or sheet material and the multilayered structure formed.In some embodiments, dielectric layer 10d may include inorganic material, example Such as silicon, ceramics.

Conductive column 11 is placed on the surface 102 of substrate 10.In some embodiments, conductive column 11 is placed in barrier layer On the surface 10b2 of 10b.In some embodiments, conductive column 11 is contacted with barrier layer 10b.For example, conductive column 11 has The surface 111 contacted with the surface 10b2 of barrier layer 10b.In some embodiments, the surface 111 of conductive column 11 and substrate 10 Surface 102 is substantially coplanar.In some embodiments, the width D 12 of conductive column 11 is less than or equal to barrier layer 10b and/or leads The width D 11 of electric layer 10r.For example, outburst area of the conductive column 11 on the surface of dielectric layer 10d 102, which is included in, stops Layer 10b is in the outburst area on the surface of dielectric layer 10d 102.

In some embodiments, conductive column 11 includes conductive layer 11a, barrier layer 11b and welding layer 11c.Conductive layer 11a peace It is placed on the surface 10b2 of barrier layer 10b.Barrier layer 11b is disposed adjacent to conductive layer 11a or is contacted with conductive layer 11a.Welding Layer 11c is disposed adjacent to barrier layer 11b or is contacted with barrier layer 11b.In some embodiments, conductive layer 11a, barrier layer 11b There is common width D12 with welding layer 11c.In some embodiments, conductive layer 11a is formed by the following terms or comprising following : Au, Ag, Cu, Pt, Pd, other metal or alloy or two or more than two combination.In some embodiments, stop Layer 11b formed by the following terms or comprising the following terms: Ni, Ti, W, other metal or alloy or two or it is more than two Combination.In some embodiments, welding layer 11c is formed by the following terms or comprising the following terms: Au, Ag, Cu, Pt, Pd, other Metal or alloy or two or more than two combination.In some embodiments, conductive layer 11a with a thickness of about 3 μm to about 20 μm, barrier layer 11b with a thickness of about 1 μm to about 5 μm, and welding layer 11c with a thickness of about 1 μm to about 3 μm.

Electric contact piece 16 (for example, soldered ball or soldering projection) is placed on the surface 112 of conductive column 11 (for example, welding layer On the surface 112 of 11c) it is electrically connected with being provided between semiconductor device package 1 and other circuits or circuit board.In some realities It applies in example, electric contact piece 16 is controlled collapse chip connection (C4) convex block, ball grid (BGA) or land grid array (LGA).In some embodiments, the diameter of electric contact piece 16 is about 25 μm to about 100 μm.In some embodiments, conductive column 11 can omit and electric contact piece 16 is directly placed on the surface 10b2 of barrier layer 10b.In some embodiments, 11 He of conductive column Electric contact piece 16 can be used for the combination of fan-in structure, fan-out structure or fan-in and fan-out structure.

As mentioned above, when welding contact is formed on the substrate, it may occur that exudation was (for example, flowing back During journey), this will cause undesirable short circuit (that is, bridge joint) between two conductive gaskets.In some existing approach, answer Bridge joint problem is avoided using anti-solder flux.However, the use of anti-solder flux will increase semiconductor device package manufacturing cost and Thickness.In addition, warpage and/or delamination problems will occur since the CTE between anti-solder flux and substrate is mismatched.According to Embodiment goes out as shown in Figure 1A and 1B, can by the way that barrier layer 10b to be placed in cover conductive layer 10r on conductive layer 10r Exudation problem is eliminated in the case where not using anti-solder flux, this will reduce the manufacturing cost and thickness of semiconductor device package 1 Degree.In addition, warpage and delamination problems can also be eliminated.

Referring back to Figure 1A, substrate 10 may include the recess or cavity to exposure conductive layer 10r.Conductive layer 12r placement In on the surface of substrate 10 101.In some embodiments, conductive layer 12r may extend into the recess or cavity of substrate 10 and electric Conductive layer 10r is connected to be electrically connected to provide between surface 102 of the surface of substrate 10 101 with substrate 10.In some implementations In example, the line-spacing (L/S) of conductive layer 12r is equal to or less than about 2 μm/2 μm.

Passivation layer 12 is placed on the surface 101 of substrate 10 to cover conductive layer 12r.In some embodiments, passivation layer 12 are also placed in the recess of substrate 10 or cavity.In some embodiments, passivation layer 12 includes gold under recess or cavity and ball Belonging to compound (UBM) 13b can be placed in recess or cavity to be electrically connected to conductive layer 12r.In some embodiments, passivation layer 10 Include silica, silicon nitride, gallium oxide, aluminium oxide, scandium oxide, zirconium oxide, lanthana, hafnium oxide, another oxide, another nitrogen Compound or two or more than two combination.In some embodiments, the specification depending on various embodiments, passivation layer 12 It can be replaced by solder mask liquid (for example, being in ink form) or film.In some embodiments, passivation layer 12 with a thickness of about 5 μ M to about 20 μm.

Electronic building brick 13 is placed on passivation layer 12 and by UBM 13b and conductive contact piece 13a (for example, dimpling block) electricity The conductive layer 12r being connected on substrate 10.Electronic building brick 13 may include chip or bare die, comprising semiconductor substrate, one or more It IC apparatus and/or is placed in and therein covers interconnection structure on one or more.IC apparatus may include such as crystal The active devices such as pipe and/or the passive device such as resistor, capacitor, inductor or two or more than two combination. In some embodiments, the number of electronic building brick 13 may depend on different designs and require and change.For example, semiconductor device Packaging part 1 may include the N number of electronic building brick for being located on passivation layer 12 and being electrically connected to conductive layer 12r, and wherein N is integer.

In some embodiments, the electric contact piece 13a of electronic building brick 13 can be covered or be encapsulated by bottom filler 13u.In In some embodiments, bottom filler 13u includes epoxy resin, mold compound (for example, epoxy molding compounds or other moulds Produced compounds), polyimides, phenolic compounds or material, the material comprising silicone dispersed therein or two or be more than two A combination.In some embodiments, the specification depending on different embodiments, bottom filler 13u can be capillary bottom of the tube Filler (CUF), molded bottom filler (MUF) or distribution gel.In some embodiments, bottom filler 13u can be saved Slightly.

Packaging body 14 is placed on passivation layer 12 and overlay electronic component 13 and bottom filler 13u.As shown in Figure 1A Out, the top surface 141 of packaging body 14 and the backside surface 131 of electronic building brick 13 are substantially coplanar.For example, electronic building brick 13 Backside surface 131 from packaging body 14 exposure.Alternatively, packaging body 14 can overlay electronic component 13 backside surface 131.Some In embodiment, packaging body 14 is including, for example, one or more organic materials (for example, mold compound, Bismaleimide Triazine (BT), PI, polybenzoxazoles (PBO), anti-solder flux, ABF, polypropylene (PP), epoxy-based material or two or it is more than two Combination), inorganic material (for example, silicon, glass, ceramics, quartz or two or more than two combination), membrane material or dry Membrane material or two or more than two combination.In some embodiments, packaging body 14 can be distribution gel.

Fig. 2 illustrates the viewgraph of cross-section of the semiconductor device package 2 according to some embodiments of the present disclosure.Semiconductor dress Packaging part 2 is set similar to the semiconductor device package 1 in Figure 1A, in addition to the conductive contact piece 26 of semiconductor device package 2 Cover the side wall of conductive column 21.Conductive column 21 is placed on the surface 10b2 of barrier layer 10b.In some embodiments, conductive column 21 contact with barrier layer 10b.Conductive column 21 is similar to the conductive column 11 of semiconductor device package 1, in addition to the resistance of conductive column 21 Barrier 21b covers conductive layer 21a and welding layer 21c covering barrier layer 21b.

Fig. 3 illustrates the viewgraph of cross-section of the semiconductor device package 3 according to some embodiments of the present disclosure.Semiconductor dress Packaging part 3 is set similar to the semiconductor device package 1 in Figure 1A, in addition to semiconductor device package 3 further includes placement In the backside surface 131 of film 31 and electronic building brick 13 on the top surface 141 of packaging body 14.Film 31 can be used for eliminating or mitigating half The warpage issues of conductor device packaging part 13 or the heat dissipation for reinforcing electronic building brick 13.In some embodiments, film 31 is by metal material Material is formed, the metal material such as Cu, Ni, Ti, W, Pt, other metal or alloy or two or more than two combination. In some embodiments, film 31 is formed by nonmetallic materials, the nonmetallic materials such as PI, ABF, epoxy resin, moldingization Close object or solder mask ink.

Fig. 4 illustrates the viewgraph of cross-section of the semiconductor device package 4 according to some embodiments of the present disclosure.Semiconductor dress Packaging part 4 is set similar to the semiconductor device package 1 in Figure 1A, in addition to semiconductor device package 4 further includes placement In the passivation layer 42 on passivation layer 12.Passivation layer 12 has the recess or cavity to exposure conductive layer 12r.Passivation layer 42 has Dispose thereon and be placed in the conductive layer 42r that conductive layer 12r is electrically connected in recess or cavity.Passivation layer 42 have to The recess or cavity of exposure conductive layer 42r.Electronic building brick 13 is connected to conductive layer 42 by electric contact piece 13a and UBM13b.In In some embodiments, passivation layer 42 and passivation layer 12 are formed from the same material.Alternatively, passivation layer 42 and passivation layer 12 are by different materials Material is formed.

Fig. 5 illustrates the viewgraph of cross-section of the semiconductor device package 5 according to some embodiments of the present disclosure.Semiconductor dress Packaging part 5 is set similar to the semiconductor device package 1 in Figure 1A, and the difference between them includes semiconductor device package 5 and does not include bottom filler and semiconductor device package 5 and further include the electronics being placed on the surface 102 of substrate 10 Component 53.Electronic building brick 53 is electrically connected to barrier layer 10b by conductive contact piece 53a (for example, dimpling block).Electronic building brick 53 can Comprising chip or bare die, comprising semiconductor substrate, one or more IC apparatus and/or it is placed in therein on one or more Cover interconnection structure.IC apparatus may include the active device such as transistor and/or such as resistor, capacitor, inductance The passive devices such as device or two or more than two combination.

Fig. 6 illustrates the viewgraph of cross-section of the semiconductor device package 6 according to some embodiments of the present disclosure.Semiconductor dress Packaging part 6 is set similar to the semiconductor device package 1 in Figure 1A, in addition in figure 1A, electronic building brick 13 passes through conductive contact Part 13a and UBM 13b are electrically connected to substrate 10, and in Fig. 6, electronic building brick 13 is electrically connected by joint wire 13w1 and 13w2 To substrate 10.Backside surface 131 is attached to substrate 10 by adhesive layer 13h (for example, gel).In some embodiments, it engages The active side 132 of electronic building brick 13 is electrically connected to the conductive gasket on the surface 101 of substrate 10 by conducting wire 13w2.In some implementations In example, the active side 132 of electronic building brick 13 is electrically connected to the conductive layer adjacent to the surface of substrate 10 102 by joint wire 13w1 10r。

Fig. 7 illustrates the viewgraph of cross-section of the electric device 7 according to some embodiments of the present disclosure.Electric device 7 includes half Conductor device packaging part 70, substrate 71 and printed circuit board (PCB) 72.Semiconductor device package 70 can be as Figure 1A, 2, 3, any of semiconductor device package 1,2,3,4,5 and 6 or any other semiconductor device shown in 4,5 and 6 Packaging part.Semiconductor device package 70 is electrically connected to substrate 71, and substrate 71 by electric contact piece 71a (for example, C4 convex block) PCB 72 is electrically connected to by electric contact piece 72a (for example, soldered ball).In some embodiments, substrate 71 may include and such as Figure 1A Shown in the similar structure of substrate 10.

Fig. 8 A, Fig. 8 B, Fig. 8 C, Fig. 8 D, 8E, 8F and 8F' be according to some embodiments of the present disclosure at the various stages The viewgraph of cross-section of the semiconductor structure of construction.At least some of these figures are had been simplified for, to better understand the disclosure Aspect.

With reference to Fig. 8 A, carrier 89 is provided and Ti layers of 89a by adhesive (or release film) 89h are attached to carrier 89.Ti layers 89a is for promoting subsequent process.In some embodiments, Ti layers of 89a can be omitted.Conductive layer 11a'(is for example, seed layer) pass through Physical vapour deposition (PVD) (PVD) or other suitable processes are formed on Ti layer 89.In some embodiments, conductive layer include Ti and Cu alloy (Ti/Cu) or other suitable materials.

Barrier layer 10b and conductive layer 10r are subsequently formed on conductive layer 11a'.In some embodiments, barrier layer 10b and Conductive layer 10r can be formed by photoetching process.For example, photoresist is formed on conductive layer 11a' for example, by coating；It connects Exposure process and developing process are carried out to photoresist to limit one or more openings to exposure conductive layer 11a'；Barrier layer 10b and conductive layer 10r is formed in opening for example, by plating and is formed on the expose portion of conductive layer 11a'；And photoresist It is removed from conductive layer 11a'.

With reference to Fig. 8 B, dielectric layer 10d (or passivation layer) is formed on conductive layer 11a' to cover conductive layer 10r and barrier layer 10b.Dielectric layer 10d may include one or more openings 10h to exposure conductive layer 10r.Seed layer 12s and conductive layer 12r shape At on dielectric layer 10d and be formed in opening 10h in be electrically connected to conductive layer 10r.In some embodiments, dielectric layer 10d It is formed by coating and the opening 10h of dielectric layer 10d can be formed by photoetching process.In some embodiments, seed layer 12s and Conductive layer 12r is formed by photoetching process.For example, seed layer is formed to be adequately coated the top surface of dielectric layer 10d And it is formed in the opening 10h of dielectric layer 10d；Photoresist is formed on seed layer for example, by coating；Photoresist is carried out and is developed Process with formed to exposure seed layer a part one or more opening；Conductive layer is formed in crystal seed for example, by plating On the expose portion of layer；And remove a part of photoresist and the seed layer covered by photoresist then to form conductive layer 12r.

With reference to Fig. 8 C, passivation layer 12 is formed on dielectric layer 10d to cover conductive layer 12r.In some embodiments, it is passivated Layer 12 is formed by coating or other suitable processes.One or more openings are formed for example, by photoetching technique to expose conductive layer A part of 12r.Conductive layer 13b (for example, UBM) is formed in opening and electric contact piece 13a is subsequently formed in conductive layer 13b On.In some embodiments, conductive layer 13b and electric contact piece 13a can be used to form conductive layer 12r or conductive layer by being similar to The photoetching process of the process of 10r is formed.

With reference to Fig. 8 D, electronic building brick 13 is electrically connected to electric contact piece 13a by engaging process.Bottom filler 13u is by shape At with the electric contact piece 13a of overlay electronic component 13.Packaging body 14 is formed by any suitable molding process with overlay electronic Component 13 and bottom filler 13u.Carrier other than 89h and Ti layers of 89a of adhesive is removed from conductive layer 11a' with sudden and violent Reveal conductive layer 11a'.

With reference to Fig. 8 E, barrier layer 11b and welding layer 11c are used to form conductive layer 10r or conductive layer for example, by being similar to The photoetching process of the process of 12r is formed on conductive layer 11a'.Solder 16' is formed on welding layer 11c.

With reference to Fig. 8 F, the upper surface of conductive layer 11a' does not dispose a part of barrier layer 11b or welding layer 11c to be removed with shape At conductive column 11 (including conductive layer 11a, barrier layer 11b and welding layer 11c).In some embodiments, the portion of conductive layer 11a' Dividing can remove for example, by etching or other suitable processes.In some embodiments, during etching process, conductive column 11 A part of side wall can also be removed to be formed and be recessed as shown in Fig. 8 F' 11r.Then, reflux course is carried out with shape At electric contact piece 16 (for example, soldered ball).

Fig. 9 A and Fig. 9 B illustrate the different types of semiconductor device package according to some embodiments of the present disclosure.

Go out as illustrated in figure 9 a, multiple chips or bare die 90 are placed on the carrier 91 of square shape.In some embodiments In, carrier 91 may include organic material (for example, mold compound, BT, PI, PBO, anti-solder flux, ABF, PP, epoxy-based material, or Two or more than two combination) or inorganic material (for example, silicon, glass, ceramics, quartz or two or it is more than two Combination).

Go out as shown in fig. 9b, multiple chips or bare die 90 are placed on the carrier 92 of circular shape.In some embodiments, Carrier 92 may include organic material (for example, mold compound, BT, PI, PBO, anti-solder flux, ABF, PP, epoxy-based material or its The combination of two or more) or inorganic material (for example, silicon, glass, ceramics, quartz or two or more than two group It closes).

As used herein, term " about ", " generally ", " a large amount of " and " about " are used to describing and considering small change Change.When being used in combination with event or situation, term can be referred to wherein event or situation clearly there is a situation where and wherein thing Part or situation be in close proximity to there is a situation where.For example, when in conjunction with numerical value in use, term can be referred to be less than or equal to it is described ± 10% variation range of numerical value, e.g., less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, it is small In or be equal to ± 2%, be less than or equal to ± 1%, be less than or equal to ± 0.5%, be less than or equal to ± 0.1% or be less than or wait In ± 0.05% variation range.For example, if difference between two values be less than or equal to the average value of value ± 10%, e.g., less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, be less than or equal to ± 2%, be less than Or be equal to ± 1%, be less than or equal to ± 0.5%, be less than or equal to ± 0.1% or be less than or equal to ± 0.05%, then can Think described two numerical value " generally " or " about " identical.For example, it " generally " can be referred to be less than relative to 0 ° in parallel Or it is equal to ± 10 ° of angle change range, e.g., less than or equal to ± 5 °, be less than or equal to ± 4 °, be less than or equal to ± 3 °, be small In or be equal to ± 2 °, be less than or equal to ± 1 °, be less than or equal to ± 0.5 °, be less than or equal to ± 0.1 ° or be less than or equal to ± 0.05 ° of angle change range.For example, it " generally " vertically can be referred to the angle for being less than or equal to ± 10 ° relative to 90 ° Spend variation range, e.g., less than or equal to ± 5 °, be less than or equal to ± 4 °, be less than or equal to ± 3 °, be less than or equal to ± 2 °, it is small In or be equal to ± 1 °, be less than or equal to ± 0.5 °, be less than or equal to ± 0.1 ° or be less than or equal to ± 0.05 ° of angle change Range.

If the displacement between two surfaces is not more than 5 μm, is not more than 2 μm, no more than 1 μm or no more than 0.5 μm, It is believed that described two surface co-planars or substantially coplanar.

As used herein, term " conductive (conductive) ", " conductive (electrically conductive) " " conductivity " refers to the ability of transmission electric current.Conductive material, which is indicated generally at, is presented those of few or zero confrontation to electric current flowing Material.One measurement of conductivity is every meter of Siemens (S/m).In general, conductive material is that conductivity is greater than about 10⁴S/m (example Such as at least 10⁵S/m or at least 10⁶S/m a kind of material).The conductivity of material can vary with temperature sometimes.Unless otherwise specified, Otherwise the conductivity of material is measured at room temperature.

Unless otherwise clearly specified in the context, otherwise as used herein, singular references " one (a/an) " and " institute State " it may include a plurality of indicants.In the description of some embodiments, the component of another component "upper" of setting " in " or " top " Situation and one or more interventions of the previous component directly on latter component (for example, with latter component material contact) can be covered Situation of the component between previous component and latter component.

Although describing by reference to the specific embodiment of the disclosure and illustrating the disclosure, these descriptions and instructions are simultaneously Do not limit the disclosure.Those skilled in the art can be clearly understood from, and not depart from as defined by the appended patent claims In the case where the true spirit and range of the disclosure, various changes can be carried out, and equivalent elements can be replaced in embodiment.Diagram It may be not necessarily drawn to scale.The variable etc. being attributed in manufacturing process, art recurring and physical device in the disclosure it Between there may be differences.The other embodiments of the not disclosure of certain illustrated may be present.The specification and schema should be regarded It is illustrative and not restrictive.Modification can be made, so that specific condition, material, material composition, method or process adapt to Target, spirit and scope in the disclosure.All such modifications are intended within the scope of the appended claims.Although having joined It examines and describes method disclosed herein by the specific operation that certain order carries out, it should be appreciated that the disclosure can not departed from These operations are combined, segment or resequenced in the case where teaching to form equivalent method.Therefore, unless specific finger herein Show, the order otherwise operated and the limitation that grouping is not the disclosure.