阅读说明：本技术 封装的半导体器件 (The semiconductor devices of encapsulation ) 是由 唐逸麒 R·M·穆卢干 M·R·库卡尼 于 2019-05-22 设计创作，主要内容包括：本申请公开封装的半导体器件。封装的半导体器件(300)包括塑封的互连衬底,塑封的互连衬底具有信号层(221)和底部金属层(223),信号层包括在具有通孔的介电层(222)上的第一和第二通道,底部金属层用于提供接地回波路径。信号层包括接触焊盘,第一和第二通道的迹线包括变窄的迹线区域(221s),且底部金属层包括含有接地切割区域(223a)的图案化层。DC阻隔电容器(C1、C2、C3、C4)串联在第一和第二通道的迹线内,用于提供AC耦合,DC阻隔电容器在一个接地切割中的上方具有一个极板。集成电路(IC)(210)包括经耦合以接收来自DC阻隔电容器的输出的第一和第二差分输入通道,其中其上的凸块阵列(218)倒装芯片安装到接触焊盘以提供第一和第二差分输出信号。(The application discloses the semiconductor devices of encapsulation.The semiconductor devices (300) of encapsulation includes the interconnection substrate of plastic packaging, the interconnection substrate of plastic packaging has signals layer (221) and bottom metal layers (223), signals layer includes the first and second channels on the dielectric layer (222) with through-hole, and bottom metal layers are for providing ground connection echo path.Signals layer includes contact pad, and the trace in the first and second channels includes the trace areas (221s) to narrow, and bottom metal layers include the patterned layer containing ground connection cutting region (223a).DC blocking condenser (C1, C2, C3, C4) is connected in the trace in the first and second channels, and for providing AC coupling, top of the DC blocking condenser in a ground connection cutting has a pole plate.Integrated circuit (IC) (210) includes the first and second Differential Input channels for being coupled to receive the output from DC blocking condenser, wherein bump array (218) flip-chip thereon is installed to contact pad to provide the first and second differential output signals.)

1. a kind of semiconductor devices of encapsulation comprising:

Interconnection substrate, that is, MIS of multilayer plastic packaging, with signals layer and bottom metal layers, the signals layer includes for having The first trace and the second trace of first passage on the dielectric layer of through-hole and in the dielectric layer with through-hole Second channel the first trace and the second trace, and the bottom metal layers below the dielectric layer are for providing ground connection Echo path, the signals layer include contact pad, wherein first trace of the first passage and the second channel With second trace include the trace areas to narrow and the bottom metal layers include containing multiple ground connection cutting regions Patterned layer；

The the first DC blocking capacitor i.e. DC being connected in first trace and second trace of the first passage Blocking condenser and the 2nd DC blocking condenser, for provide AC coupled i.e. AC coupling, the first DC blocking condenser and One in each leisure of 2nd DC blocking condenser ground connection cutting is upper with a pole plate；

The 3rd DC blocking condenser and the 4th being connected in first trace and second trace of the second channel DC blocking condenser, for providing AC coupling, the 3rd DC blocking condenser and each leisure of the 4th DC blocking condenser A top in the ground connection cutting has a pole plate, and

Integrated circuit, that is, IC comprising: the first Differential Input channel is coupled to receive from the first DC barrier capacitor The output of device and the 2nd DC blocking condenser；And at least the second Differential Input channel, it is coupled to receive described The output of three DC blocking condensers and the 4th DC blocking condenser, wherein bump array flip-chip thereon is installed to institute Contact pad is stated, to provide the first differential output signal and the second differential output signal.

2. the semiconductor devices of encapsulation according to claim 1, wherein the width with other traces on the signals layer It compares, the trace areas to narrow at least narrows 20%.

3. the semiconductor devices of encapsulation according to claim 1, wherein the width with other traces on the signals layer It compares, the trace areas to narrow at least narrows 40%.

4. the semiconductor devices of encapsulation according to claim 1, wherein the bump array includes copper post, the copper post There is solder projection on it.

5. the semiconductor devices of encapsulation according to claim 1, further includes printed circuit board i.e. PCB and be located at the bottom Solder pattern between portion's metal layer and the PCB, and the plastic packaging material of encapsulating is provided for the semiconductor devices of the encapsulation.

6. the semiconductor devices of encapsulation according to claim 1, wherein the IC includes communication device, the communicator Part includes the receiver containing decoder and the transmitter including encoder.

7. the semiconductor devices of encapsulation according to claim 1, wherein the first DC blocking condenser, described second The capacitor of DC blocking condenser, the 3rd DC blocking condenser and the 4th DC blocking condenser is 0.05 μ F to 2 μ F.

8. the semiconductor devices of encapsulation according to claim 1, wherein the trace areas to narrow is located adjacent to described First ground connection cutting top of the pole plate of DC blocking condenser, the pole plate of the DC blocking condenser is described first Ground connection cutting top.

9. the semiconductor devices of encapsulation according to claim 1, wherein the dielectric layer includes composite material, described multiple Condensation material includes epoxy resin.

10. a kind of method of the semiconductor devices of manufacture encapsulation comprising:

There is provided multilayer plastic packaging interconnection substrate, that is, MIS, with signals layer and bottom metal layers, the signals layer include for The first trace and the second trace of first passage on dielectric layer with through-hole and in the dielectric with through-hole The first trace and the second trace of second channel on layer, and the bottom metal layers below the dielectric layer are for providing It is grounded echo path, the signals layer includes contact pad, wherein described the first of the first passage and the second channel Trace and second trace include the trace areas to narrow and the bottom metal layers include containing multiple ground connection cutting areas The patterned layer in domain；

It is attached the first DC blocking capacitor in series in first trace and second trace of the first passage That is DC blocking condenser and the 2nd DC blocking condenser, for providing AC coupled i.e. AC coupling, the first DC obstructs capacitor A top in device and each leisure of the 2nd DC blocking condenser ground connection cutting has a pole plate, and described The 3rd DC blocking condenser and the 4th DC barrier are attached in first trace and second trace of second channel in series Capacitor connects described in the 3rd DC blocking condenser and each leisure of the 4th DC blocking condenser for providing AC coupling A top in ground cutting has a pole plate, and

Being attached integrated circuit, that is, IC includes: the first Differential Input channel, is coupled to receive from the first DC barrier electricity The output of container and the 2nd DC blocking condenser；And at least the second Differential Input channel, it is coupled to described in reception The output of 3rd DC blocking condenser and the 4th DC blocking condenser, wherein bump array flip-chip thereon is installed to The contact pad, to provide the first differential output signal and the second differential output signal.

11. described compared with the width of other traces on the signals layer according to the method described in claim 10, wherein The trace areas to narrow at least narrows 20%.

12. described compared with the width of other traces on the signals layer according to the method described in claim 10, wherein The trace areas to narrow at least narrows 40%.

13. according to the method described in claim 10, its further include:

The trace areas to narrow according to the design of the dielectric properties of the dielectric layer；

For the initial predefined track width in the trace areas to narrow；

It is simulated in advance into several track width candidates by using two dimensional field simulator,

It is verified using all-wave three-dimensional simulation device to determine performance, wherein the dielectric properties of the dielectric layer and being given an account of The thickness of electric layer is inputted together with the track width and desired characteristic impedance together as parameter.

14. the copper post has on it according to the method described in claim 10, wherein, the bump array includes copper post Solder projection.

15. according to the method described in claim 10, it further includes offer printed circuit board i.e. PCB, and in the bottom gold Belong to and solder pattern is provided between layer and the PCB, and the plastic packaging material of the semiconductor devices offer encapsulating of the encapsulation is provided.

16. the communication device includes containing according to the method described in claim 10, wherein, the IC includes communication device The receiver of decoder and transmitter including encoder.

17. according to the method described in claim 10, wherein the first DC blocking condenser, the 2nd DC obstruct capacitor The capacitor of device, the 3rd DC blocking condenser and the 4th DC blocking condenser is 0.05 μ F to 2 μ F.

18. according to the method described in claim 10, it further includes that the trace areas to narrow is located close to the DC First ground connection cutting top of the pole plate of blocking condenser, the pole plate of the DC blocking condenser connect described first Ground cutting top.

Technical field

This disclosure relates to the semiconductor devices of high speed encapsulation.

Background technique

Some high speed signal/data devices (such as retimer circuit, repeater and clock synthesizer) are usually to encapsulate High capacity and middle high pin count device in flip chip ball grid array (FC BGA) encapsulation, the FC BGA package are relatively High cost package.It is wire bonding BGA package with cost-benefit alternative solution.However, (> 5 gigabit/second of high speed (Gbps)) electric property of wire bonding BGA package is relatively poor, the return loss of insertion loss and difference such as with difference (return loss)。

Integrated circuit (IC) encapsulation can be based on the emerging technology of referred to as plastic packaging interconnection substrate (MIS).MIS is with special substrate Material starts, for selecting IC package.Then MIS itself is encapsulated factory and is generallyd use MIS simultaneously by various supplier developments and sale IC package, including addition molding are assembled around it.MIS is known as guiding frame by some people.

MIS is different from conventional substrate, because MIS technology includes the preformed seal structure with one or more metal layers. Every layer is usually provided at least one top and a bottom copper coating in advance, has dielectric layer, layers of copper tool between layers of copper There is through-hole to provide electrical connection in a package.

Summary of the invention

There is provided the content of present invention is for the brief selection of concept disclosed in place of matchmakers in simplified form, these concepts will It is further described in following detailed description (including provided attached drawing).The content of present invention is not intended to be limited to claimed Theme range.

Relatively inexpensive MIS QFN technology (its is provided plus the DC blocking condenser in encapsulation by exploitation physical structure With after tuning to provide the MIS with tradition FC BGA package similar performance), disclosed aspect is solved for high speed device FC BGA package high-cost problem (since it is desired that meet high electrical property, for example, 56Gbps or higher data speed Rate).Disclosed performance tuning includes making the respective traces on signals layer (for example, negative (N) signal traces in each channel and just (P) signal traces) narrow and the bottom metal layers with ground connection cutting (ground cuts) are provided, wherein the signal mark to narrow Line extends beyond ground connection cutting and there is a pole plate in each comfortable ground connection cutting top of DC blocking condenser.

Disclosed aspect includes the semiconductor devices of encapsulation comprising the plastic packaging with signals layer and bottom metal layers is mutual Even substrate, the signals layer include first passage on the dielectric layer with through-hole and second channel and the bottom metal layers Echo path is grounded for providing.Signals layer includes contact pad, and the trace in the first and second channels includes the trace zone to narrow Domain, and bottom metal layers include the patterned layer containing ground connection cutting region.DC blocking condenser is connected on first and second In the trace in channel, for providing AC coupling, wherein DC blocking condenser has a pole above one be grounded in cutting Plate.IC includes the first and second Differential Input channels for being coupled to receive the output from DC blocking condenser, wherein thereon Bump array flip-chip be installed to contact pad to provide the first and second differential output signals.

Detailed description of the invention

With reference to the drawings, the drawings are not necessarily drawn to scale, in which:

Figure 1A is the part without its plastic packaging of the semiconductor devices based on MIS QFN of example package, device tool There are two channels, and each channel has two traces, in total four traces, and there is every trace concatenated DC to obstruct capacitor Device.

Figure 1B is the schematic diagram of the part of the semiconductor devices based on MIS QFN of encapsulation shown in Figure 1A.

Fig. 2 is that have plastic packaging material according to the semiconductor devices based on MIS QFN of the example package of an exemplary aspect The sectional view of (mold compound) is directed to a Differential Input by being shown as the channel of the DC blocking condenser of C1, Show the signal path in signals layer.

Fig. 3 is that the feature of the part without its plastic packaging of the semiconductor devices based on MIS QFN of example package is described, One of DC blocking condenser is removed to show disclosed ground connection cutting and disclosed " elongated " trace and tune.

Fig. 4 A- Fig. 4 B by the insertion loss of the simulation between the semiconductor devices based on FC BGA known in Fig. 4 A and Insertion loss in Fig. 4 B compares, the insertion loss of Fig. 4 B be directed to lack disclosed performance tuning it is original based on The semiconductor devices of MIS QFN, and for the semiconductor devices based on MIS QFN for including disclosed performance tuning.It wants The specification of satisfaction is the insertion loss of < 0.5dB at 14GHz；At 14GHz, the insertion loss of < 15dB (being pushed into < 20dB), Wherein device operates at 14GHz (56Gbps).

Fig. 4 C- Fig. 4 D by the return loss of the simulation between the semiconductor devices based on FC BGA known in Fig. 4 C and Insertion loss in Fig. 4 D compares, the return loss of Fig. 4 D be directed to lack disclosed performance tuning it is original based on The semiconductor devices of MIS QFN, and for the semiconductor devices based on MIS QFN for including disclosed performance tuning.

Specific embodiment

Example embodiment is described with reference to the drawings, wherein identical appended drawing reference is for indicating similar or equivalent element.No The illustrated sequence of behavior or event should be considered as limitation, because certain behaviors or event may occur in a different order And/or occur simultaneously with other behaviors or event.Furthermore, it is possible to not need some illustrated movements or event to implement basis Disclosed method.

Figure 1A depicts a quarter (25%) of the semiconductor devices 100 based on MIS QFN of example package, is shown For binary channels device, there is first passage and second channel, including MIS 220, there is the first, second, third and fourth direct current (DC) blocking condenser C1, C2, C3 and C4, wherein there are two each channels (one is used for P trace, and one is used for N trace, or ' pin (legs) ') DC blocking condenser, for providing the DC blocking condenser for obstructing low frequency component for each input.IC Tube core 210 is attached to MIS 220 by bump array, and bump array has the convex block for being shown as 218.Bump array may include copper Column has the solder projection in the landing pad of IC tube core 210 thereon.

Although usually there is the plastic packaging material for being used for disclosed packaging, be not shown in Figure 1A plastic packaging material to avoid Fuzzy characteristics.Moreover, although it is not shown, there is also the input signal of the other end from IC tube core 210, by IC tube core 210 processing, then export from the first and second channels.Simplified pinciple such as Figure 1B is as shown in the figure, such as 210 ' institute of IC die sections The IC tube core shown has receiver (Rx) 211₀、211₁With transmitter (Tx) 213₀、213₁, by for repairing input signal Clock and data recovery (CDR) circuit 212₀、212₁It is coupled, the signal after then output is repaired.

The semiconductor devices 100 of encapsulation usually may include any device with high speed signal path AC coupled, high speed Signal path passes through MIS 220 and advances to IC tube core 210 and advance from IC tube core 210 across MIS 220.For example, high speed is believed Number adjuster is believed used in such as signal retimer or High Performance Computing Cluster (computing farm) application program Number repeater.The disclosed semiconductor devices based on MIS QFN can be tuned commonly used in any serializer/de-serializers (Serdes) or high-speed channel.

MIS 220 includes providing the signals layer 221 and bottom metal layers 223 of top surface, and signals layer 211 includes being located to have Contact pad and bottom metal layers 223 on the dielectric layer 222 of through-hole provide ground connection echo path, can also be used for adding Signal traces.Reaching the trace on the signals layer 221 of bottom metal layers by the through-hole wiring in dielectric layer 222 will be encapsulation The semiconductor devices based on MIS QFN physical bottom, client, which is usually welded, (is not shown patterned solder in Figure 1A Layer, but the patterning solder layer 219 in the Fig. 2 seen description below) arrive its printed circuit board (PCB) shown in PCB 240. Patterning solder layer may include the soldered ball for the bottom metal layers 223 for being attached to MIS encapsulation 220 or may include being printed onto Solder cream silk screen (solder paste screen) on PCB 240.Although it is not shown, but MIS substrate 220 may include more 3 layers shown in.

Signals layer 221 and bottom metal layers 223 generally include copper or copper alloy.Dielectric layer 222 generally includes plastic packaging material work For the dielectric material between layer 221 and 223.Known plastic packaging material is usually composite material in encapsulation comprising epoxy resin, phenol Class curing agent, silica, catalyst, pigment and release agent.

MIS 220 provides co-planar waveguide (CPW) microstrip structure.The thickness of MIS 220 can be about 80 μm, signals layer 221 Thickness with bottom metal layers 223 is about 20 μm, and the thickness of dielectric layer 222 is about 40 μm.DC blocking condenser usually has There is the capacitor of 0.05 μ F to 2 μ F.The capacitance range is higher than the usually possible capacitance range of capacitor on IC, therefore DC barrier electricity Container is usually the device separated with IC.In 0201 size (0.6x0.3mm), the typical capacitance of DC blocking condenser is 0.22 μF。

Figure 1B shows the simple equivalent circuit in Differential Input channel shown in Figure 1A.For each channel, there are differences Sub-signal, the N trace and P trace for being shown as each channel are shown as RX0P and RX0N for first passage, for second channel, It is shown as RX1P and RX1N.Bottom metal layers 223 provide echo path for each signal traces to provide impedance matching.Signal itself It is differential signal, i.e. N and P.Specifically gap/width of the trace in selection signal layer 221 is passed with the difference for maximizing signal It is defeated.

It is DC blocking condenser C1, C2, C3 and C4 at the input terminal (being shown as IC die sections 210 ') of IC.In signals layer Trace on 221, the through-hole in dielectric layer 222, convex block (Fig. 2 seen description below) and on C1, C2, C3 and C4 either side It is connected to the expression of the solid line as shown in of the interconnection in the path of IC die sections 210 '.In the outlet side of IC die sections 210 ' On, there are two DC blocking condensers in each channel, it is shown as C5, C6, C7 and C8, and package trace on signals layer 221, Through-hole and convex block (Fig. 2 seen description below) in dielectric layer 222 and from IC tube core to the path of DC blocking condenser in Also the solid line as shown in indicates for interconnection.

Fig. 2 is the cross-sectional view with plastic packaging material 260 of the semiconductor devices 200 based on MIS QFN of example package, For a Differential Input in the channel of the DC blocking condenser by being shown as C1, is shown with arrow and be shown as that " signal is defeated Enter " signal path.IC tube core 210 has bump array (one of convex block 218 is identified), and flip-chip is attached (FC Attached) to the contact pad on the signals layer of MIS 221.Outside the semiconductor devices 200 based on MIS QFN, in bottom There are patterned solder layer 219 (such as soldered ball) on metal layer 223, the solder layer 219 is from the plastic packaging on the bottom of MIS 220 260 exposure of material, the terminal pad (land) for being coupled to bottom metal layers 223 on PCB 240.

Shown arrow logo from PCB 240 to patterning solder layer 219, to bottom metal layers 223, into dielectric layer 222 Through-hole, on signals layer 221 node, to C1 a pole plate signal stream.After through C1, signal reaches the another of C1 One pole plate, then another node on arriving signal layer 221, reaches convex block 218 (for example, the Cu column with solder is convex Block), and finally reach IC tube core 210.

Fig. 3 is that the feature of the part without its plastic packaging of the semiconductor devices 300 based on MIS QFN of example package is retouched It draws, one of DC blocking condenser C1 is removed to show disclosed ground connection cutting 223a and be included in ground connection cutting 223a The disclosed elongated trace 221s of top, ground connection cutting and elongated trace both contribute to the tuning of MIS performance.Including shown Ground connection cutting 223a ground connection cutting region lack dielectric layer 222 so that ground connection cutting 223a above capacitor plate exist Below without bottom metal layers.Notice that the white space in Fig. 3 is plastic packaging material (for example, with reference to above filled with dielectric Plastic packaging material 260 in described Fig. 2).

50 μm of nominal line width shown in for example, can be used for signals layer 221, and elongated trace 221s can have such as institute 30 μm of the width shown, wherein particular example arrangement indicates that elongated trace 221s reduces with 40% track width.It is given Device performance requirements met by tuning, which provides elongated trace zone using the traces narrow down on signals layer 221 Domain and ground connection cutting 223a, the two insertion loss such as under given working frequency and are returned commonly used in meeting device specification Wave loss.Example specification specific for one, the specification are the insertion loss of < 0.5dB at 14GHz；At 14GHz, < The insertion loss of 15dB (being pushed into < 20dB), wherein device operates at 14GHz (56Gbps).

The percentage range (% range) of traces narrow down on signals layer 221 is 5% to 50%, such as 50 μm of traces of standard 25 μm of elongated trace 221s in width.As shown in Figure 3, the width of the trace in the first signals layer 221 usually can be 50μm.However, when (one of pad is on ground connection cutting region for the relatively close capacitor pad of 221 trace of the first signals layer Side) when, the significant reduction of track width is 30 μm such as the tuning of elongated trace.

It can be seen that a pole plate for being shown as the DC blocking condenser of C2 and C3 is located above ground connection cutting 223a.Fig. 3 Shown in metal pad on signals layer 221 in frame be used in a pole plate for being attached C1 above, just as C2 and C3 is attached phase The metal pad answered, the attachment include one in its pole plate above ground connection cutting 223a.

About the tuning of signals layer trace, trace can be finely tuned according to plastic packaging material material properties.The elongated mark of signals layer 221 The track width of line can be pre-defined initially by theoretical and/or experience, then can be simulated in advance by 2D simulators to several In a trace dimension candidate, it may then pass through to the all-wave 3D simulation in its end performance and verify.All these Plastic packaging material attribute (its dielectric constant and loss angle tangent) and desired characteristic impedance during step, in dielectric layer 222 Zo is entered as parameter, characteristic impedance Zo for it is single-ended be usually 50 ohm and be usually 100 ohm for difference.

About applicable theory, the empirical equation of the Zo for the microstrip line copied below shows how dielectric constant is one Kind plastic packaging material attribute, because the dielectric in dielectric layer 222 influences the characteristic impedance of 221 trace of signals layer, this is considered to resistance Anti- matching is critically important therefore also critically important to device performance.The equation of microstrip line shows the ruler of its characteristic impedance Zo and trace Relationship between very little and dielectric layer 222 dielectric constant ∈ e, wherein W is track width, and d is through-hole thickness, and through-hole is thick Degree is arranged by the thickness of dielectric layer 222, the thickness of the dielectric layer 222 determine between signals layer 221 and bottom metal layers 223 away from From.

For

As described above, Zo range is generally controlled to single-ended 50 ohm and 100 ohm of difference.Radio frequency (RF) electronics Known microstrip line has its most of field line usually in dielectric area in field, and dielectric layer 222 concentrates on here Between signals layer 221 and bottom metal layers 223.Disclosed ground connection cutting is placing one be located in capacitor pad just Lower section, so that each DC blocking condenser has the pad of cutting with ground.Identical ground connection cutting in bottom metal layers 223 Also implement below elongated trace.DC blocking condenser pad due to they and ground plane coupling and be usually unusual capacitor Property, therefore it is grounded the integral capacitor sex expression cut and reduce encapsulation.Below elongated trace on signals layer 221 there is also Ground connection cutting, to further increase the inductance of elongated trace.

Fig. 4 A- Fig. 4 B by the insertion loss of the simulation between the semiconductor devices based on FC BGA known in Fig. 4 A and Insertion loss in Fig. 4 B compares, the insertion loss of Fig. 4 B be directed to lack disclosed performance tuning it is original based on The semiconductor devices of MIS QFN, and for the semiconductor devices based on MIS QFN for including disclosed performance tuning.It should IC is data center's retimer, for extend it is long, damage, the range and robust of the high speed serialization link that crosstalk is impaired Property, while realizing 10 to 15 or the lower bit error rate (BER).The specification to be met is at 14GHz, and the insertion of < 0.5dB is damaged Consumption；At 14GHz, the insertion loss of < 15dB (being pushed into < 20dB), wherein device operates at 14GHz (56Gbps).

Fig. 4 C- Fig. 4 D by the return loss of the simulation between the semiconductor devices based on FC BGA known in Fig. 4 C and Insertion loss in Fig. 4 D compares, the return loss of Fig. 4 D be directed to lack disclosed performance tuning it is original based on The semiconductor devices of MIS QFN, and for the semiconductor devices based on MIS QFN for including disclosed performance tuning.

Data in Fig. 4 A- Fig. 4 D demonstrate: as described herein, by using significant cheap MIS QFN technology (it can provide the performance similar with traditional device based on FC BGA package after tuning) Lai Kaifa physical structure adds DC blocking condenser in encapsulation, traditional FC BGA package technology for high speed device high-cost problem (since it is desired that Meet high electrical property, the data rate of 56Gbps+) it is solved.The disclosed packaging based on MIS QFN provides tradition The performance of FC-BGA encapsulation technology, wherein packaging cost reduces about 40% to 60%, and since MIS technology process is than tradition Package substrate manufactures faster, therefore the production cycle shortened for 1 to 2 weeks.

The disclosed embodiments are desirably integrated into various assembling flow paths to form a variety of different packagings and correlation Product.The component may include single semiconductor element or multiple semiconductor elements, such as including multiple Stacket semiconductor tube cores PoP configuration.Various package substrates can be used.Semiconductor element may include one of the various elements and/or layer thereon, packet Include barrier layer, dielectric layer, device architecture, active component and passive element comprising source region, drain region, bit line, base stage, emitter, Collector, conductor wire, conductive through hole etc..In addition, semiconductor element can be formed by various techniques, including bipolar junction transistor, Insulated gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

The technical staff in field involved by the disclosure will be appreciated that in the range of claimed invention embodiment is permitted More other embodiments and modification are possible, and without departing from the scope of the present disclosure, can be to described reality Apply example further added, deleted, substitutions and modifications.