阅读说明：本技术 封装结构 (Encapsulating structure ) 是由 陶玉娟 于 2019-07-26 设计创作，主要内容包括：一种封装结构,包括：预封面板,所述预封面板包括塑封层,所述塑封层中具有若干半导体芯片,每个半导体芯片包括功能面和与功能面相对的非功能面,所述功能面上具有若干焊盘,所述塑封层暴露出功能面上的若干焊盘；位于半导体芯片与塑封层之间的第一屏蔽层和第二屏蔽层,所述第一屏蔽层包覆所述半导体芯片的非功能面和侧壁表面,所述第二屏蔽层位于第一屏蔽层和塑封层之间且完全覆盖所述半导体芯片的非功能面和侧壁上的第一屏蔽层表面。通过在第一屏蔽层上的第二屏蔽层,所述第二屏蔽层能覆盖所述第一屏蔽层中厚度不均匀以及边缘覆盖不好的地方,从而使得第一屏蔽层和第二屏蔽层两者构成的整体屏蔽层是完整的,提高了屏蔽的效果。(A kind of encapsulating structure, it include: preformed cover plate, the preformed cover plate includes plastic packaging layer, there are several semiconductor chips in the plastic packaging layer, each semiconductor chip includes functional surfaces and the non-functional surface opposite with functional surfaces, there are several pads, the plastic packaging layer exposes several pads on functional surfaces on the functional surfaces；First screen layer and secondary shielding layer between semiconductor chip and plastic packaging layer, the first screen layer coats the non-functional surface and sidewall surfaces of the semiconductor chip, and the secondary shielding layer is between first screen layer and plastic packaging layer and the first screen layer surface that is completely covered in the non-functional surface and side wall of the semiconductor chip.Pass through the secondary shielding layer in first screen layer, the secondary shielding layer can cover place in uneven thickness in the first screen layer and bad edges cover, so that the bulk shield that both first screen layer and secondary shielding layer are constituted is completely, to improve the effect of shielding.)

1. a kind of encapsulating structure characterized by comprising

Preformed cover plate, the preformed cover plate include plastic packaging layer, have several semiconductor chips, each semiconductor in the plastic packaging layer Chip includes functional surfaces and the non-functional surface opposite with functional surfaces, has several pads on the functional surfaces, the plastic packaging layer is sudden and violent Expose several pads on functional surfaces；

First screen layer and secondary shielding layer between semiconductor chip and plastic packaging layer, described in first screen layer cladding The non-functional surface and sidewall surfaces of semiconductor chip, the secondary shielding layer are between first screen layer and plastic packaging layer and complete Cover the first screen layer surface in the non-functional surface and side wall of the semiconductor chip；

The external contact structure being connect with pad on the back side of preformed cover plate.

2. encapsulating structure as described in claim 1, which is characterized in that the first screen layer is formed by sputtering technology, institute State first screen layer at least also cover semiconductor chip around part support plate surface, the secondary shielding layer by selectivity electricity Depositing process, gluing process or screen printing technique are formed.

3. encapsulating structure as claimed in claim 2, which is characterized in that the material of the first screen layer is copper, tungsten or aluminium, institute The material for stating secondary shielding layer is copper, solder or conductive silver glue.

4. encapsulating structure as described in claim 1, which is characterized in that the first screen layer is magnetic field shielding layer, and described Secondary shielding layer is electric field shielding layer；Or the first screen layer is electric field shielding layer, and the secondary shielding layer is magnetic field Shielded layer.

5. encapsulating structure as claimed in claim 4, which is characterized in that the material of the electric field shielding layer is copper, tungsten, aluminium；Institute The material for stating magnetic field shielding layer is the alloy of CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe.

6. encapsulating structure as described in claim 1, which is characterized in that also have bottom on the functional surfaces of the semiconductor chip Shielded layer, the entire functional surfaces of the bottom shield layer covering semiconductor chip, the edge of the bottom shield layer and half The surrounding side wall of conductor chip flushes, and several pads run through bottom shield layer, passes through separation layer between pad and bottom shield layer Isolation；The first screen layer is connect with the edge of bottom shield layer.

7. encapsulating structure as described in claim 1, which is characterized in that the external contact structure includes being located at preformed cover backboard The wiring layer again being connect on face with pad and the external contacts being connect on wiring layer again with wiring layer again.

8. encapsulating structure as claimed in claim 7, which is characterized in that have insulating layer, institute on the back side of the preformed cover plate Stating has the opening for exposing bond pad surface in insulating layer, the wiring layer again is located in the opening and partial insulative layer table On face, the external contacts are located at being routed in layer surface outside opening again.

9. encapsulating structure as claimed in claim 8, which is characterized in that further include: be located at insulating layer in by first screen layer with The part conductive contact structure that wiring layer is electrically connected again.

10. it is a kind of encapsulating structure as claimed in claims 1-9 is split after the independent encapsulating structure that is formed, feature It is, comprising: plastic packaging layer has semiconductor chip in the plastic packaging layer, and the semiconductor chip includes functional surfaces and and function The opposite non-functional surface in face, has several pads on the functional surfaces, and the plastic packaging layer exposes several pads on functional surfaces； First screen layer and secondary shielding layer between semiconductor chip and plastic packaging layer, the first screen layer cladding is described partly to be led The non-functional surface and sidewall surfaces of body chip, the secondary shielding layer is between first screen layer and plastic packaging layer and is completely covered First screen layer surface in the non-functional surface and side wall of the semiconductor chip；

The external contact structure being connect with pad on the functional surfaces of semiconductor chip.

Technical field

The present invention relates to field of semiconductor fabrication more particularly to a kind of encapsulating structures with electromagnetic shielding.

Background technique

The rapid development of electronic product of new generation, push integrated antenna package also to high density, high-frequency, micromation, Highly integrated direction is developed, and high frequency chip often generates stronger electromagnetic wave, causes not expecting to inside and outside and chip is encapsulated Interference or noise；In addition electronic component density is higher and higher, the distance of transmission line is more and more closer, so that coming from integrated circuit The inside and outside electromagnetic interference problem of encapsulation also gets worse, while can reduce the quality of integrated circuit, service life etc..

In electronic equipment and electronic product, electromagnetic interference (Electromagnetic Interference) energy passes through Conductibility coupling and radiativity coupling are to be transmitted.It, need to be using filtering to conductibility coupling to meet EMC Requirements Technology is inhibited using electromagnetic interface filter part；Radiativity coupling is then needed to be inhibited using shield technology.In current electricity Magnetic frequency spectrum is increasingly intensively, electromagnetic power density sharply increases, low and high level device or equipment are largely used in mixed way in unit volume Etc. factors and in the case where causing equipment and system electromagnetic environment worsening, importance just seems more prominent.

A magnetic field shielding is arranged in a kind of existing electromagnetic shielding solution mainly on semiconductor package Layer, for shielding the electromagnetic interference of chip chamber, but the effect of existing electromagnetic shielding still have it is to be hoisted.

Summary of the invention

The technical problem to be solved by the present invention is to how improve the effectiveness of existing encapsulating structure.

The present invention provides a kind of encapsulating structures, comprising:

Preformed cover plate, the preformed cover plate include plastic packaging layer, have several semiconductor chips, Mei Geban in the plastic packaging layer Conductor chip includes functional surfaces and the non-functional surface opposite with functional surfaces, has several pads, the plastic packaging on the functional surfaces Layer exposes several pads on functional surfaces；

First screen layer and secondary shielding layer between semiconductor chip and plastic packaging layer, the first screen layer cladding The non-functional surface and sidewall surfaces of the semiconductor chip, the secondary shielding layer between first screen layer and plastic packaging layer and The first screen layer surface in the non-functional surface and side wall of the semiconductor chip is completely covered；

The external contact structure being connect with pad on the back side of preformed cover plate.

Optionally, the first screen layer is formed by sputtering technology, and the first screen layer at least also covers semiconductor Part support plate surface around chip, the secondary shielding layer pass through selective electroplating technique, gluing process or screen printing work Skill is formed.

Optionally, the material of the first screen layer is copper, tungsten or aluminium, and the material of the secondary shielding layer is copper, solder Or conductive silver glue.

Optionally, the first screen layer is magnetic field shielding layer, and the secondary shielding layer is electric field shielding layer；Or institute Stating first screen layer is electric field shielding layer, and the secondary shielding layer is magnetic field shielding layer.

Optionally, the material of the electric field shielding layer is copper, tungsten, aluminium；The material of the magnetic field shielding layer is CoFeB conjunction Gold, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe alloy.

Optionally, also there is bottom shield layer, the bottom shield layer covering half on the functional surfaces of the semiconductor chip The entire functional surfaces of conductor chip, the edge of the bottom shield layer is flushed with the surrounding side wall of semiconductor chip, several Pad runs through bottom shield layer, is isolated between pad and bottom shield layer by separation layer；The first screen layer and bottom screen Cover the edge connection of layer.

Optionally, the external contact structure include the wiring layer again being connect with pad in the preformed cover back and The external contacts being connect on wiring layer again with wiring layer again.

Optionally, there is insulating layer on the back side of the preformed cover plate, have in the insulating layer and expose bond pad surface Opening, the wiring layer again is located in the opening and in SI semi-insulation layer surface, and the external contacts are located at opening Outer is routed in layer surface again.

Optionally, further includes: by first screen layer and the part conductive contact that wiring layer is electrically connected again in insulating layer Structure.

The present invention also provides it is a kind of the aforementioned encapsulating structure is split after the independent encapsulating structure that is formed, It is characterised by comprising: plastic packaging layer, there is semiconductor chip in the plastic packaging layer, the semiconductor chip include functional surfaces and The non-functional surface opposite with functional surfaces has several pads on the functional surfaces, if the plastic packaging layer exposes on functional surfaces Dry pad；First screen layer and secondary shielding layer between semiconductor chip and plastic packaging layer, the first screen layer cladding The non-functional surface and sidewall surfaces of the semiconductor chip, the secondary shielding layer between first screen layer and plastic packaging layer and The first screen layer surface in the non-functional surface and side wall of the semiconductor chip is completely covered；

The external contact structure being connect with pad on the functional surfaces of semiconductor chip.

Compared with prior art, technical solution of the present invention has the advantage that

Encapsulating structure of the invention, including the first screen layer and secondary shielding between semiconductor chip and plastic packaging layer Layer, the first screen layer coat the non-functional surface and sidewall surfaces of the semiconductor chip, and the secondary shielding layer is located at the Between one shielded layer and plastic packaging layer and the first screen layer table that is completely covered in the non-functional surface and side wall of the semiconductor chip Face, the secondary shielding layer can cover place in uneven thickness in the first screen layer and bad edges cover, thus So that the bulk shield that both first screen layer and secondary shielding layer are constituted is completely, to improve the effect of shielding.

Further, the secondary shielding layer is only located at the of the non-functional surface and sidewall surfaces for coating the semiconductor chip One shielding layer surface on, and the surface of the secondary shielding layer be in ellipsoid, the secondary shielding layer by selective electroplating technique, Gluing process or screen printing technique are formed, and the secondary shielding layer formed is enabled preferably to cover the first screen layer, are prevented Only occur covering bad place in secondary shielding layer, is further ensured that both first screen layer and secondary shielding layer are constituted whole The integrality of body shielded layer, and it is subsequent without additional exposure mask and etching technics removal semiconductor chip.

Further, the first screen layer is magnetic field shielding layer, then the secondary shielding layer formed is electric field shielding layer；Or The first screen layer is electric field shielding layer, then the secondary shielding layer formed is magnetic field shielding layer, by forming structure above-mentioned First screen layer and secondary shielding layer so that first screen layer and secondary shielding layer are directed to electric field respectively or magnetic field is shielded It covers, to improve the shield effectiveness of shielded layer, and the secondary shielding layer can cover in the first screen layer thickness not Uniform and bad edges cover place, so that the bulk shield that both first screen layer and secondary shielding layer are constituted It is completely, to further improve the effect of shielding.

Further, also there is bottom shield layer, the bottom shield layer covering half on the functional surfaces of the semiconductor chip The entire functional surfaces of conductor chip, the edge of the bottom shield layer is flushed with the surrounding side wall of semiconductor chip, several Pad runs through bottom shield layer, is isolated between pad and bottom shield layer by separation layer；When forming the first screen layer, The first screen layer is connect with the edge of bottom shield layer.I.e. in the present embodiment not only after forming first screen layer, It also will form secondary shielding layer in first screen layer, thus the secondary shielding layer can cover thickness in the first screen layer The place that degree is uneven and edges cover is bad, so that the whole screen that both first screen layer and secondary shielding layer are constituted Covering layer is completely, to improve the effect of shielding, and due to also having bottom shield on the functional surfaces of the semiconductor chip Layer, when forming the first screen layer, the first screen layer is connect with the edge of bottom shield layer, so that envelope Semiconductor chip in the assembling structure cladding complete or comprehensive by bottom shielded layer and first screen layer, thus electric and magnetic fields It cannot be entered in encapsulating structure by the bottom of encapsulating structure and bring electromagnetic interference to semiconductor chip, to realize to semiconductor Chip carries out comprehensive electromagnetic shielding, further improves the effect of electromagnetic shielding.

Detailed description of the invention

Fig. 1-Figure 13 is the structural schematic diagram of the forming process of first embodiment of the invention encapsulating structure；

Figure 14-Figure 20 is the structural schematic diagram of the forming process of second embodiment of the invention encapsulating structure.

Specific embodiment

As described in the background art, the effect of existing electromagnetic shielding still has to be hoisted.

The study found that existing magnetic field shielding layer is formed generally by sputtering technology, due to semiconductor package thickness Degree is general thicker, and semiconductor package is generally in rectangle so that semiconductor package there are multiple apex angles and side wall compared with To be precipitous, when forming the magnetic field shielding layer of cladding semiconductor package by sputtering technology, the magnetic field shielding layer of formation Thickness, which is easy uneven, semiconductor package edge, can have unlapped situation, so that the shielding of magnetic field shielding layer Effect is difficult to ensure.

For this purpose, the present invention provides a kind of encapsulating structure and forming method thereof, if the forming method is by dry semiconductor After the functional surfaces of chip are bonded on support plate, the first screen of the non-functional surface and sidewall surfaces that coat the semiconductor chip is formed Cover layer；Secondary shielding layer is formed in the first screen layer.By forming secondary shielding layer in first screen layer, described Two shielded layers can cover place in uneven thickness in the first screen layer and bad edges cover, so that the first screen The bulk shield for covering both layer and secondary shielding layer composition is completely, to improve the effect of shielding.

In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general ratio Example makees partial enlargement, and the schematic diagram is example, should not be limited the scope of the invention herein.In addition, in reality It should include the three-dimensional space of length, width and depth in the production of border.

Fig. 1-Figure 13 is the structural schematic diagram of the forming process of first embodiment of the invention encapsulating structure.

It is Fig. 1 along the schematic diagram of the section structure in the direction cutting line AB with reference to Fig. 1-Fig. 3, Fig. 2, several semiconductor chips is provided 101, each semiconductor chip 101 includes functional surfaces and the non-functional surface opposite with functional surfaces, is had on the functional surfaces several Pad 102.

Integrated circuit (not shown), the semiconductor chip are formed in the functional surfaces of the semiconductor chip 101 There are several pads 102, the pad 102 is electrically connected with the integrated circuit in semiconductor chip 101, institute on 101 functional surfaces State port of the pad 102 as integrated circuit and external electrical connections in semiconductor chip 101.

The functional surfaces of the semiconductor chip 101 are to be used to form the one side of integrated circuit, the non-functional surface be with The opposite one side of functional surfaces, surrounded surface is the side wall of semiconductor chip 101 between functional surfaces and non-functional surface.

The semiconductor chip 101 is formed by semiconductor integration making technology, is specifically please referred to Fig. 1 and Fig. 2, is provided Wafer 100, the chip area and the Cutting Road region between chip area that the wafer 100 includes several ranks arrangement； Several semiconductor chips 101 are correspondingly formed in several chip areas of the wafer 100, in the function of the semiconductor chip 101 Several pads 102 can be formed on face；With reference to Fig. 3, after forming several pads, divides the wafer 100 along Cutting Road, formed several Discrete semiconductor chip 101.

In one embodiment, the material of the wafer 100 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), silicon carbide (SiC)；It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be others III-V compounds of group such as material, such as GaAs.

In one embodiment, the integrated circuit in the semiconductor chip 101 may include several semiconductor devices (such as Transistor, memory, diode and/or triode etc.) and by interconnection structure (including the metal connecting line of semiconductor devices connection And metal plug).

In the present embodiment, the semiconductor chip 101 is the semiconductor chip being electromagnetically shielded.

With reference to Fig. 4, support plate 201 is provided；The functional surfaces of several semiconductor chips 101 are bonded on support plate 201.

Offer support platform of the support plate 201 as subsequent technique, the support plate 201 can carry for glass support plate, silicon The support plate of plate or metal support plate, the support plate 201 or other suitable materials.

The semiconductor chip 101 is bonded in the surface of support plate 201 by an adhesive layer, the semiconductor chip 101 The adhesive surface of functional surfaces (or pad 102) towards support plate 201.

There are many available materials of adhesive layer, and in one embodiment, adhesive layer uses UV glue.UV glue is a kind of energy To the aitiogenic glueing material of the ultraviolet light of special wavelength.UV glue can be divided into according to variation sticky after ultraviolet light Two kinds, one is UV solidification glue, i.e. photoinitiator in material or photosensitizer produces after absorbing ultraviolet light under ultraviolet irradiation Liveliness proof free radical or cation cause monomer polymerization, are crosslinked and connect branch chemical reaction, make ultraviolet cured adhesive within the several seconds Solid-state is converted by liquid, so that the body surface being in contact with it be bonded；Another UV glue without ultraviolet light when irradiating Viscosity is very high, and the crosslinking chemical bond after ultraviolet light in material is interrupted viscosity is caused to decline to a great extent or disappear.This In adhesive layer used by UV glue be the latter.It can be formed by film coating process, print adhesive process or plastic roll technique described viscous Close layer.

In other embodiments, the adhesion-layer materials can also for epoxide-resin glue, polyimides glue, polyethylene glue, Benzocyclobutene glue or polybenzoxazoles glue.

Several semiconductor chips 101 are uniformly bonded on support plate 201 in ranks arrangement.

In other embodiments, referring to FIG. 5, before semiconductor chip 101 is bonded on support plate 201, described Insulating layer is formed on support plate 201, and (including the first insulating layer 121 and second insulating layer 122, the first insulating layer 121 are located at second absolutely The top of edge layer 122) and wiring layer 123 again in insulating layer, the insulating layer (the first insulating layer) expose part cloth again The surface of line layer 123；The functional surfaces of several semiconductor chips 101 are bonded with the wiring layer again 123 on support plate 201, In In one embodiment, the pad 102 can be bonded by solder layer and wiring layer 123 again.

With reference to Fig. 6, the first screen layer 103 of the non-functional surface and sidewall surfaces that coat the semiconductor chip 101 is formed.

In the present embodiment, the first screen layer 103 can not only coat the semiconductor chip 101 non-functional surface and Sidewall surfaces, the first screen layer 103 also cover 201 surface of support plate between semiconductor chip 101.In other embodiments In, the first screen layer 103 can only coat the non-functional surface and sidewall surfaces of the semiconductor chip 101.

In one embodiment, the first screen layer 103 is formed by sputtering technology, the material of the first screen layer 103 Material can be copper, tungsten or aluminium, due to the tool of semiconductor chip 101 there are four apex angle (rectangular) and 101 thickness of semiconductor chip compared with Thick 101 side wall of semiconductor chip is more precipitous (side wall and 201 surface of support plate are in 90 degree of angles), so that being formed by sputtering technology First screen layer 103 there is a problem of that in uneven thickness and edges cover is bad.

Described to form the shielded layer that first screen layer 103 is electric and magnetic fields in the present embodiment, first screen layer 103 is used In the shielding of electric and magnetic fields, the secondary shielding layer being subsequently formed also is the shielded layer of electric and magnetic fields, and secondary shielding layer is used for The shielding of electric and magnetic fields.

The study found that existing shielded layer should shield electric field armoured magnetic field again, and the single layer screen of existing certain material Covering layer or multi-layer phase only can have preferable shield effectiveness to electric field with the shielded layer of material or analog material, to the screen in magnetic field It covers that effect is relatively weak, affects the shield effectiveness of shielded layer.Thus in other embodiments, the first screen layer 103 is Magnetic field shielding layer, first screen layer is used for armoured magnetic field, and the secondary shielding layer being subsequently formed is electric field shielding layer, secondary shielding Layer is for shielding electric field；Or the first screen layer is electric field shielding layer, and first screen layer is for shielding electric field, and described the Two shielded layers are magnetic field shielding layer, and secondary shielding layer is used for armoured magnetic field, by formed structure above-mentioned first screen layer and Secondary shielding layer, so that first screen layer and secondary shielding layer are directed to electric field respectively or magnetic field is shielded, to improve screen Cover the shield effectiveness of layer.When the first screen layer 103 is electric field shielding layer, the first screen layer 103 (electric field shielding layer) Material be copper, tungsten, aluminium；When the first screen layer 103 is magnetic field shielding layer, the 103 (magnetic field shielding of first screen layer Layer) material be CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe alloy.Form described first Shielded layer 103 can use sputtering, physical vapour deposition (PVD), atomic layer deposition or chemical vapor deposition or other suitable works Skill.

With reference to Fig. 7, secondary shielding layer 104 is formed in the first screen layer 103.

By forming secondary shielding layer 104 in first screen layer 103, the secondary shielding layer 104 can cover described the Place in uneven thickness and bad edges cover in one shielded layer 103, so that first screen layer 103 and secondary shielding The bulk shield that both layers 104 are constituted is completely, to improve the effect of shielding.

In the present embodiment, the secondary shielding layer 104 is only located at the non-functional surface and side wall for coating the semiconductor chip On 103 surface of first screen layer on surface, and the surface of the secondary shielding layer 104 is in ellipsoid, the secondary shielding layer 104 It is formed by selective electroplating technique, gluing process or screen printing technique, enables the secondary shielding layer 104 formed better The first screen layer is covered, prevents from occurring covering bad place in secondary shielding layer 104, is further ensured that first screen layer The integrality for the bulk shield that both 103 and secondary shielding layer 104 are constituted, and it is subsequent without additional exposure mask and etching work Skill removes semiconductor chip.

The material of the secondary shielding layer 104 is copper, solder or conductive silver glue.In one embodiment, the secondary shielding 104 forming process of layer are as follows: first form mask layer (not shown) on the support plate 201, there is exposure in the mask layer The opening of the non-functional surface of semiconductor chip 101 and the first screen layer 103 in sidewall surfaces out；With the first screen layer 103 as conductive layer when being electroplated, and plating forms secondary shielding layer 104 in said opening, or in the opening directly It brushes and forms secondary shielding layer 104 into solder；Remove the mask layer.

In another embodiment, the material of the secondary shielding layer 104 is solder or conductive silver glue, can pass through dispensing work Skill or screen printing technique form the secondary shielding layer 104.Specifically, when carrying out gluing process, by solder or conductive silver glue On 103 surface of first screen layer that point is coated on 101 side wall of semiconductor chip and non-functional surface.It is first when carrying out screen printing The part first screen layer 103 on 101 surrounding support plate 201 of semiconductor chip is first removed, so that remaining first screen layer 103 is wrapped Cover the non-functional surface and sidewall surfaces and bottom filled layer side surface of the semiconductor chip, and remaining first screen layer 103 also extend over 201 surface of part support plate around semiconductor chip 101；Then will have meshed web plate as support plate On 201, in the corresponding mesh being located in web plate of each semiconductor chip 101；It is brushed in mesh into solder, solder covering 103 surface of first screen layer on 101 side wall of semiconductor chip and non-functional surface；Remove the web plate；Solder is returned Stream forms secondary shielding layer 104 in first screen layer 103.

In one embodiment, the solder is tin, Xi Yin, tin-lead, tin silver copper, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, tin One or more of metals such as gold, tin copper, tin zinc indium or tin silver antimony.

In other embodiments, the first screen layer 103 is magnetic field shielding layer, then the secondary shielding layer 104 formed is Electric field shielding layer；Or the first screen layer 103 is electric field shielding layer, then the secondary shielding layer 104 formed is magnetic field shielding Layer, by forming the first screen layer and secondary shielding layer of structure above-mentioned, so that first screen layer and secondary shielding layer difference It is shielded for electric field or magnetic field, to improve the shield effectiveness of shielded layer.When the secondary shielding layer 104 is electric field screen Layer is covered, the material of the secondary shielding layer 104 (electric field shielding layer) is copper, tungsten, aluminium；When the secondary shielding layer 104 is magnetic field Shielded layer, the material of the secondary shielding layer 104 (magnetic field shielding layer) be CoFeB alloy, CoFeTa, NiFe, Co, CoFe, The alloy of CoPt or Ni, Co and Fe.Sputtering, physical vapour deposition (PVD), atomic layer can be used by forming the secondary shielding layer 104 Deposition or chemical vapor deposition or other suitable techniques.

In one embodiment, after forming the secondary shielding layer 104, described adjacent half can be removed by etching technics The first screen layer on support plate between conductor chip 101.

With reference to Fig. 8, plastic packaging is formed on the support plate 201 in the secondary shielding layer 104 and between semiconductor chip 101 Layer 105.

The plastic packaging layer 105 is for sealing and fixing the semiconductor chip 101, to be subsequently formed preformed cover plate.

The material of the plastic packaging layer 105 can be for epoxy resin, polyimide resin, benzocyclobutane olefine resin, polyphenyl simultaneously Oxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyene One of hydrocarbon, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol Or it is several.

Forming the plastic packaging layer 105 can be using Shooting Technique (injection molding) or turn modeling technique (transfer molding) or other suitable techniques.

With reference to Fig. 9, the support plate 201 (with reference to Fig. 8) is removed, forms preformed cover plate 10,10 back side of the preformed cover plate dew The functional surfaces (and pad) of semiconductor chip 101 out.

By removal adhesive layers such as chemical attack, mechanical stripping, CMP, mechanical lapping, heat bakings, so that 201 quilt of support plate Removing.

The back side of the preformed cover version 10 is the surface contacted with support plate 201 (referring to Fig. 8).

With reference to Figure 10 and Figure 11, the external contact structure connecting with pad 102 is formed at the back side of the preformed cover plate 10.

In the present embodiment, the external contact structure includes being located on 10 back side of preformed cover plate to connect again with pad 102 Wiring layer 123 and the external contacts 124 being connect on wiring layer 123 again with wiring layer 123 again.Each semiconductor core Pad 102 on piece 101 is connected with corresponding external contact structure.

In one embodiment, the forming process of the wiring layer again 123 and external contacts 124 includes: in the pre- envelope Insulating layer (the first insulating layer) 121 is formed on the back side of panel 10, is formed and is exposed in the insulating layer (the first insulating layer) 121 The opening on 102 surface of pad, 121 materials of the insulating layer (the first insulating layer) can with silicon nitride, Pyrex, phosphorosilicate glass or Boron-phosphorosilicate glass；In said opening and partial insulative layer (the first insulating layer) 121 surfaces form wiring layer 123 again；It is opening It is routed formation external contacts 124 in layer surface again outside mouthful.In one embodiment, the external contacts 124 be soldered ball or Person includes metal column and the soldered ball on metal column, the forming process of the external contacts 124 are as follows: in the insulating layer Insulating layer (second insulating layer) 122, insulating layer (second insulation are formed on (the first insulating layer) 121 and again wiring layer 123 Layer) 122 there is the second opening for exposing part on insulating layer (the first insulating layer) 121 surfaces 123 surface of wiring layer again；In External contacts 124 are formed in second opening.

In one embodiment, further include insulating layer (the first insulating layer) 121 formed by first screen layer 103 and part again The conductive contact structure (not shown) that wiring layer 123 is electrically connected, so that shielded layer can pass through partially wiring layer 123 again The electrostatic interference in electric discharge or the barrier external world.

With reference to Figure 12 and Figure 13, after the formation external contact structure, the preformed cover plate 10 is cut, several separation are formed Encapsulating structure 11.

Each encapsulating structure 11 includes plastic packaging layer 105, has semiconductor chip 101 in the plastic packaging layer 105, described Semiconductor chip 101 includes functional surfaces and the non-functional surface opposite with functional surfaces, has several pads 102 on the functional surfaces, The plastic packaging layer 105 exposes several pads on functional surfaces；First between semiconductor chip 101 and plastic packaging layer 105 Shielded layer 103 and secondary shielding layer 104, the first screen layer 103 coat non-functional surface and the side of the semiconductor chip 101 Wall surface, the secondary shielding layer 104 is between first screen layer 103 and plastic packaging layer 105 and the semiconductor is completely covered 103 surface of first screen layer in the non-functional surface and side wall of chip 101；

The external contact structure being connect with pad 101 on the functional surfaces of semiconductor chip.

The external contact structure include the wiring layer again 123 that is connect with pad 102 on 10 back side of preformed cover plate with And the external contacts 124 being connect on wiring layer 123 again with wiring layer 123 again.

The present invention realizes there is first screen layer 103 and secondary shielding layer 104 by aforesaid semiconductor integration making technology Encapsulating structure 11 batch making, improve the efficiency of production.

Figure 14-Figure 20 is the structural schematic diagram of the forming process of second embodiment of the invention encapsulating structure.Second embodiment Difference with first embodiment is: also having bottom shield layer, the bottom shield on the functional surfaces of the semiconductor chip The entire functional surfaces of layer covering semiconductor chip, the edge of the bottom shield layer and the surrounding side wall of semiconductor chip are neat Flat, several pads run through bottom shield layer, are isolated between pad and bottom shield layer by separation layer；Forming first screen When covering layer, the first screen layer is connect with the edge of bottom shield layer.Not only the first screen is being formed i.e. in the present embodiment After covering layer, secondary shielding layer also will form in first screen layer, thus the secondary shielding layer can cover first screen Place in uneven thickness in layer and bad edges cover is covered, so that both first screen layer and secondary shielding layer are constituted Bulk shield be it is complete, improve the effect of shielding, and due to also having on the functional surfaces of the semiconductor chip Bottom shield layer, when forming the first screen layer, the first screen layer is connect with the edge of bottom shield layer, from And the cladding for making the semiconductor chip in encapsulating structure complete or comprehensive by bottom shielded layer and first screen layer, thus electricity Field and magnetic field cannot be entered in encapsulating structure by the bottom of encapsulating structure brings electromagnetic interference to semiconductor chip, to realize Comprehensive electromagnetic shielding is carried out to semiconductor chip, further improves the effect of electromagnetic shielding.

The forming process of the semiconductor chip with bottom shielded layer are as follows: Figure 14 is referred to, wafer 100 is provided, it is described Several semiconductor chips 101 are formed on wafer 100, the semiconductor chip 101 is including top layer dielectric layer 108 and is located at top layer Top layer interconnection structure 109 in dielectric layer 108, the semiconductor chip further include being located at wafer (or semiconductor substrate) surface shape At several semiconductor devices (such as transistor etc.), between 100 surface of top layer dielectric layer 108 and wafer it is several layer by layer Between dielectric layer, there is corresponding interconnection structure, interconnection structure can be mutual with upper and lower level in interlayer dielectric layer in every layer of interlayer dielectric layer It is electrically connected even or with semiconductor devices, the top layer interconnection structure 109 in the top layer dielectric layer 108 can be with the layer of adjacent layer Between interconnection structure electrical connection in dielectric layer；Separation layer is formed in the top layer dielectric layer 108.

Separation layer described in the present embodiment be double stacked structure, including the first separation layer 110 and be located at the first separation layer The material of the second separation layer 111 on 110, the first separation layer 110 and the second separation layer 111 is not identical, 110 He of the first separation layer The material of second separation layer 111 can be one of silica, silicon nitride, silicon oxynitride, be accurately controlled shape convenient for subsequent At second opening depth, prevent formation second be open when over etching separation layer so that second opening expose top layer Jie The part of the surface of Portions of top layer interconnection structure 109 in matter layer 108, it is subsequent in the second opening formed bottom shielded layer when cause to push up Short circuit between layer interconnection structure 109.In other embodiments, the separation layer can be single layer structure.

With reference to Figure 15, the separation layer is etched, if forming several first openings 112 in the separation layer and surrounding described Second opening 113 of dry first opening 112, and remaining separation layer 111 be only located at the first opening 112 and the second opening 112 it Between, first opening 112 and the second opening 111 are separated.

It is several first opening 112 be it is discrete, it is described first opening 112 run through the separation layer, each first opening 112 can expose 109 part of the surface of top layer interconnection structure accordingly, and subsequent filling metal is formed in first opening 112 Pad.

It is described second opening 113 surround it is described first opening 112, second opening 113 and first opening 112 between by every Absciss layer 111 separates, and the depth of second opening 113 is less than the thickness of separation layer, first opening 112 and around first The exterior domain of the separation layer 111 of opening 112 all corresponds to the region of the second opening 113, and third opening 113 is connection, after When continuing the formation bottom shielded layer in third opening 113, the bottom shielded layer can be covered on the functional surfaces of semiconductor chip 101 All regions other than pad (being formed in the first opening 112) and around the separation layer of pad, when in semiconductor When the non-functional surface of chip 101 and the surface of side wall form first screen layer, the four of the first screen layer and bottom shield layer Circumferential edges connection, so that the semiconductor chip in encapsulating structure is complete or comprehensive by bottom shielded layer and first screen layer Cladding, thus electric and magnetic fields cannot be entered in encapsulating structure by the bottom of encapsulating structure and bring electromagnetism to semiconductor chip Interference carries out comprehensive electromagnetic shielding to semiconductor chip to realize, further improves the effect of electromagnetic shielding.

In the present embodiment, uses the first etching technics to etch second separation layer 111 and made with first separation layer 110 For stop-layer, the second opening is formed in second separation layer 111；Then, the second etching technics, etching described second are carried out Separation layer 111 and the first separation layer 110 form the first opening, In in second separation layer 111 and the first separation layer 110 Before carrying out the first etching technics or the second etching technics, it can be formed on the surface of second separation layer 110 corresponding Mask layer.It should be noted that second etching technics can also be carried out prior to the first etching technics.

In other embodiments, when the separation layer is single layer structure, twice etching technique can also be carried out and be respectively formed The first opening and the second opening, by control etching technics time, thus control formation second opening depth (second opens The depth of mouth is less than the thickness of separation layer).

With reference to Figure 16, filling metal material forms several pads 102 in several first openings, opens described second Filling metal material forms bottom shield layer 114 in mouthful；With reference to Figure 17, after forming pad 102 and bottom shielded layer 114, cutting The wafer forms several discrete semiconductor chips 101 with bottom shielded layer 114.

In one embodiment, several pads 102 and bottom shield layer 114 are formed by same technique, comprising steps of Metal material layer is formed in the first opening and the second opening and on the surface of separation layer, the metal material layer passes through Physical vapour deposition (PVD), sputtering or electroplating technology are formed, the material of the metal material layer can for aluminium, nickel, tin, tungsten, platinum, One or more of copper, titanium, chromium, tantalum, gold, silver；Planarization removal is higher than the metal material layer of the insulation surface, in institute Formation pad 102 in the first opening is stated, forms bottom shield layer 114 in second opening.

With reference to Figure 18, Figure 18 is 101 overlooking structure diagram of semiconductor chip in Figure 17, in conjunction with reference Figure 17 and Figure 18, There is bottom shield layer 114, the bottom shield layer 114 covers semiconductor chip on the functional surfaces of the semiconductor chip 101 101 entire functional surfaces, the edge of the bottom shield layer 114 is flushed with the surrounding side wall of semiconductor chip 101, several Pad 102 runs through bottom shield layer 114, is isolated between pad 102 and bottom shield layer 114 by separation layer 111.

Process and the existing semiconductor chip fabrication technique that bottom shield layer 114 is previously formed in the application are integrated, bottom The manufacturing process of shielded layer 114 synchronous with the manufacturing process of pad 102 can carry out, and simplify manufacture craft, reduce technique Difficulty improves efficiency.

With reference to Figure 19, the semiconductor chip 101 with bottom shield layer 114 is bonded on support plate 201, the pad 102 and bottom shield layer 114 contacted with support plate 201；Form the non-functional surface and sidewall surfaces for coating the semiconductor chip 101 First screen layer 103；Secondary shielding layer 104 is formed in the first screen layer 103；In the secondary shielding layer 104 And plastic packaging layer 105 is formed on the support plate 201 between semiconductor chip 101.

With reference to Figure 20, the support plate 201 (with reference to Figure 19) is removed, forms preformed cover plate, the preformed cover back is exposed The functional surfaces of semiconductor chip；External contact structure (the external contact connecting with pad is formed at the back side of the preformed cover plate Structure includes being located at the wiring layer again 123 connecting in preformed cover back with pad 102 and on wiring layer 123 again and again The external contacts 124 that wiring layer 123 connects).

It should be noted that in second embodiment with structure same or similar in first embodiment other limit or retouch It states, is not repeating in a second embodiment, specifically please refer to the restriction or description of corresponding portion in first embodiment.

A kind of encapsulating structure is additionally provided in one embodiment of the invention, please refers to Figure 11 or Figure 20, comprising:

Preformed cover plate (10), the preformed cover plate include plastic packaging layer 105, if having dry semiconductor in the plastic packaging layer 105 Chip 101, each semiconductor chip 101 include functional surfaces and the non-functional surface opposite with functional surfaces, are had on the functional surfaces Several pads 102, the plastic packaging layer 105 expose several pads on functional surfaces；

First screen layer 103 and secondary shielding layer 104 between semiconductor chip 101 and plastic packaging layer 102, described One shielded layer 103 coats the non-functional surface and sidewall surfaces of the semiconductor chip 101, and the secondary shielding layer 104 is located at the Between one shielded layer 103 and plastic packaging layer 105 and be completely covered in the non-functional surface and side wall of the semiconductor chip 101 first 103 surface of shielded layer；

The external contact structure being connect with pad on the back side of preformed cover plate.

In one embodiment, the first screen layer 103 is formed by sputtering technology, and the secondary shielding layer 104 passes through Selective electroplating technique, gluing process or screen printing technique are formed.The material of the first screen layer 103 be copper, tungsten or aluminium, The material of the secondary shielding layer 104 is copper, solder or conductive silver glue.

In another embodiment, the first screen layer 103 is magnetic field shielding layer, and the secondary shielding layer 104 is electricity Field shielded layer；Or the first screen layer 103 is electric field shielding layer, and the secondary shielding layer 104 is magnetic field shielding layer.Institute The material for stating electric field shielding layer is copper, tungsten, aluminium；The material of the magnetic field shielding layer be CoFeB alloy, CoFeTa, NiFe, Co, The alloy of CoFe, CoPt or Ni, Co and Fe.

In one embodiment, Figure 20 is please referred to, also there is bottom shield layer on the functional surfaces of the semiconductor chip 101 114, the bottom shield layer 114 covers the entire functional surfaces of semiconductor chip 101, the surrounding of the bottom shield layer 114 Edge is flushed with the surrounding side wall of semiconductor chip 101, and several pads 102 run through bottom shield layer 114, pad 102 and bottom screen It covers and is isolated between layer 114 by separation layer 111；The first screen layer 103 is connect with the edge of bottom shield layer 114.

In one embodiment, the external contact structure includes being located in preformed cover back to connect again with pad 102 Wiring layer 123 and the external contacts 124 being connect on wiring layer 123 again with wiring layer 123 again.

There is insulating layer (the first insulating layer) 121 on the back side of the preformed cover plate, there is exposure in the insulating layer 121 The opening on 102 surface of pad out, the wiring layer again 123 is located in the opening and on 121 surface of partial insulative layer, described External contacts 124 are located on 123 surface of wiring layer again outside opening.

Cover the insulating layer (the first insulating layer) 122 of the insulating layer (the first insulating layer) 121, the external contacts 124 parts are located in insulating layer (the first insulating layer) 122.

In one embodiment, further includes: by first screen layer 103 and part, wiring layer 123 is electric again in insulating layer 121 The conductive contact structure (not shown) of connection.

The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as Protection scope of the present invention.