阅读说明：本技术 芯片集成结构 (chip integrated structure ) 是由 冯雪 刘兰兰 陈颖 叶柳顺 张柏诚 蒋晔 付浩然 李波 于 2018-05-28 设计创作，主要内容包括：本发明公开了一种芯片集成结构,涉及半导体制造工艺领域,所述结构包括：衬底,粘接在衬底上的芯片、位于芯片的侧面和芯片周围的衬底上的缓冲层、以及芯片引线,芯片引线自芯片沿固化后的缓冲层表面延伸至衬底,且芯片引线与位于缓冲层下的芯片侧面和缓冲层下的衬底表面绝缘。采用上述芯片集成结构可抑制芯片与衬底之间的连接导线断裂、脱粘失效等问题的发生,降低应力集中现象带来的影响。(The invention discloses a chip integrated structure, relating to the field of semiconductor manufacturing process, wherein the structure comprises: the chip lead extends to the substrate from the surface of the solidified buffer layer of the chip, and the chip lead is insulated from the side surface of the chip positioned under the buffer layer and the surface of the substrate positioned under the buffer layer. By adopting the chip integrated structure, the problems of fracture, debonding failure and the like of a connecting wire between the chip and the substrate can be inhibited, and the influence caused by the stress concentration phenomenon is reduced.)

1. a chip integrated structure, comprising: the chip comprises a substrate, a chip adhered on the substrate, a buffer layer positioned on the side surface of the chip and the substrate around the chip, and chip leads; the chip lead extends to the substrate from the surface of the buffer layer after the chip is solidified, and is insulated from the side surface of the chip under the buffer layer and the surface of the substrate under the buffer layer.

2. The chip integrated structure according to claim 1, further comprising a chip external circuit formed on the substrate, the chip leads being connected with the chip external circuit.

3. The chip integrated structure of claim 2, wherein the chip leads are integrally formed with the chip external circuit.

4. The chip integrated structure according to claim 1, further comprising an adhesive glue between the chip and the substrate, wherein the adhesive glue adheres the chip to the substrate, and the buffer layer covers a side portion of the adhesive glue.

5. the chip integrated structure according to claim 4, wherein the adhesive glue is a heat-curable glue.

6. the chip integrated structure according to claim 4, wherein the adhesive glue is an epoxy glue, a polyester glue, a silicone glue, or a conductive glue.

7. The chip integrated structure of claim 4, wherein the buffer layer has a slope extending from a side of the chip to the substrate.

8. The chip integrated structure according to any one of claims 1 to 7, wherein the buffer layer is an insulating glue.

9. the chip integrated structure according to claim 8, wherein the insulating glue is at least one of an acrylic glue, an unsaturated polyester glue and a polyurethane glue, or a mixture of at least two of the above glues.

10. The chip integrated structure according to claim 8, wherein the insulating glue is an ultraviolet light curing glue.

Technical Field

The invention relates to the field of semiconductor manufacturing processes, in particular to a chip integrated structure.

Background

Chip integration refers to the integration of chip leads and their off-chip circuitry onto the substrate of a device. In the conventional process, a packaged chip is used for chip integration. The packaged chip has leads which lead from contact pads in the chip (Die) for providing electrical contact to circuit elements within the chip. When the packaged chip is integrated into a device, the chip is wire-bonded to a substrate, and a circuit external to the chip is prepared on the substrate of the device to realize electrical connection of the chip.

The inventor finds that the prior art has at least the following defects in the process of implementing the invention:

Because the size and the material property of the chip are different from those of the substrate, in the process of using the device, the phenomenon of stress concentration is generated at the joint of the chip and the substrate due to the sudden change of the geometric dimension and the material property, particularly, the stress concentration phenomenon is more likely to occur in the use process of the flexible electronic device, and the stress concentration phenomenon easily causes the problems of fracture, debonding failure and the like of a connecting wire between the chip and the substrate.

Disclosure of Invention

Accordingly, there is a need for a chip integration method and a chip integration structure that can reduce the influence of stress concentration.

According to a first aspect of embodiments of the present invention, there is provided a chip integration method, including:

Providing a substrate, and forming adhesive glue at a chip mounting position of the substrate;

Providing a chip, and adhering the chip to the substrate through the adhesive glue;

Coating insulating glue on the side surface of the chip and the substrate around the chip;

Curing the insulating glue;

And manufacturing a chip lead, wherein the chip lead extends from the chip to the substrate along the surface of the cured insulating glue.

In an alternative embodiment, the insulating glue is formed by printing through a 3D printing technology.

In an optional embodiment, the insulating glue is an ultraviolet curing glue, and the insulating glue is cured by an ultraviolet curing method.

In an optional implementation manner, the substrate on the side surface of the chip and around the chip is coated with an insulating glue, specifically:

Printing an insulating glue on the side surface of the chip and the substrate around the chip by adopting a 3D printing technology, so that the insulating glue forms an inclined surface extending from the side surface of the chip to the substrate; the included angle between the inclined plane and the substrate is 0-45 degrees.

In an alternative embodiment, the chip leads are printed using 3D printing techniques.

in an alternative embodiment, the step of fabricating the chip leads includes:

printing conductive paste serving as a raw material to form a wire to be cured, wherein the wire to be cured extends from the chip to the substrate along the surface of the cured insulating glue;

And curing the wire to be cured to obtain the chip lead.

In an alternative embodiment, the conductive paste is a thermally curable paste; the curing temperature of the conductive paste is 80-100 ℃, and the wire to be cured is cured in a thermosetting mode.

in an optional embodiment, the method further comprises:

After the insulating glue is cured, forming a chip external circuit on the substrate;

And extending the chip lead from the chip to the substrate along the cured surface of the insulating glue and connecting the chip lead with a chip external circuit.

In an alternative embodiment, the chip external circuit is formed by printing using 3D printing technology.

In an alternative embodiment, the chip external circuit is printed integrally with the chip leads.

In an optional implementation, the chip integration method further includes:

Printing the conductive paste serving as a raw material on the substrate to form a line to be cured;

And curing the line to be cured to obtain the chip external circuit.

In an alternative embodiment, the adhesive glue is formed by printing using a 3D printing technique.

in an alternative embodiment, the adhesive glue is a heat curable glue; the curing temperature of the adhesive is 80-100 ℃, and the adhesive is cured in a thermosetting mode.

According to a second aspect of the embodiments of the present invention, there is provided a chip integrated structure, including:

the chip comprises a substrate, a chip adhered on the substrate, insulating glue positioned on the side surface of the chip and the substrate around the chip, and chip leads; the chip lead extends from the chip to the substrate along the cured surface of the insulating glue.

In an alternative embodiment, the chip integrated structure further includes a chip external circuit formed on the substrate, and the chip leads are connected to the chip external circuit.

In an alternative embodiment, the chip leads are integrally formed with the chip external circuit.

In an optional embodiment, the chip integrated structure further includes an adhesive glue located between the chip and the substrate, the adhesive glue adhering the chip to the substrate, and the insulating glue coating the side of the adhesive glue.

In an alternative embodiment, the insulating paste has a slope extending from the side of the chip to the substrate; the included angle between the inclined plane and the substrate is 0-45 degrees.

In an alternative embodiment, the insulating glue is at least one of an acrylic glue, an unsaturated polyester glue and a polyurethane glue or a mixture of at least two of the above.

compared with the prior art, the invention has the following outstanding beneficial effects:

the invention provides a chip integration method and a chip integration structure, wherein a chip is bonded on a substrate through bonding glue, so that the bonding capability between the chip and the substrate can be improved; the bonding capability of the chip and the substrate is enhanced by curing the insulating adhesive on the side surface of the chip and the substrate around the chip, the problems of fracture, debonding failure and the like of a connecting lead between the chip and the substrate are inhibited, and because a chip lead extends from the chip to the substrate along the surface of the cured insulating adhesive, the stress on the substrate is weakened by the buffering of the insulating adhesive when reaching the connecting lead, so that the influence of the stress concentration phenomenon on the connecting lead is reduced.

Drawings

fig. 1 is a flowchart of a chip integration method according to an embodiment of the present invention;

FIG. 2 is a schematic view of a substrate according to a second embodiment of the present invention;

fig. 3 is a schematic diagram of a first step of a chip integration method according to a second embodiment of the present invention;

fig. 4 is a schematic diagram of a second step of a chip integration method according to a second embodiment of the present invention;

fig. 5 is another schematic diagram of a second step of the chip integration method according to the second embodiment of the present invention;

fig. 6 is a schematic diagram of a fourth step of a chip integration method according to a second embodiment of the present invention;

FIG. 7 is a partial enlarged view of A in FIG. 6;

Fig. 8 is another schematic diagram of step four of a chip integration method according to a second embodiment of the present invention;

Fig. 9 is a schematic diagram of step six of a chip integration method according to a second embodiment of the present invention;

Fig. 10 is another schematic diagram of step six of a chip integration method according to a second embodiment of the present invention;

fig. 11 is a schematic diagram of a seventh step of a chip integration method according to a second embodiment of the present invention;

fig. 12 is another schematic diagram of a seventh step of a chip integration method according to a second embodiment of the present invention;

Fig. 13 is a schematic diagram of a chip integrated structure according to a third embodiment of the present invention;

Fig. 14 is another schematic diagram of a chip integrated structure according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings.