阅读说明：本技术 射频装置 (Radio frequency device ) 是由 陈汇丰 杨光 欧阳锦坚 袁林山 黃清俊 谈文毅 于 2021-04-12 设计创作，主要内容包括：本发明公开一种射频装置,其包括半导体基底、电感器结构、屏蔽结构以及掩模图案。半导体基底包括第一区与第二区。电感器结构设置于半导体基底的第一区上。屏蔽结构设置于半导体基底的第一区上且在垂直方向上位于电感器结构与半导体基底之间。掩模图案设置于半导体基底上,掩模图案的第一部分设置于屏蔽结构上且直接接触屏蔽结构,且屏蔽结构的上表面完全被掩模图案的第一部分覆盖。(A radio frequency device includes a semiconductor substrate, an inductor structure, a shielding structure, and a mask pattern. The semiconductor substrate comprises a first region and a second region. The inductor structure is disposed on the first region of the semiconductor substrate. The shielding structure is disposed on the first region of the semiconductor substrate and is located between the inductor structure and the semiconductor substrate in a vertical direction. The mask pattern is disposed on the semiconductor substrate, a first portion of the mask pattern is disposed on and directly contacts the shielding structure, and an upper surface of the shielding structure is completely covered by the first portion of the mask pattern.)

1. A radio frequency device, comprising:

a semiconductor substrate including a first region and a second region;

an inductor structure disposed on the first region of the semiconductor substrate;

a shielding structure disposed on the first region of the semiconductor substrate and between the inductor structure and the semiconductor substrate in a vertical direction; and

a mask pattern disposed on the semiconductor substrate, wherein a first portion of the mask pattern is disposed on and directly contacts the shielding structure, and an upper surface of the shielding structure is completely covered by the first portion of the mask pattern.

2. The apparatus of claim 1, wherein the shielding structure is an electrically floating (electrically floating) conductive structure.

3. The radio frequency device of claim 1, wherein the mask pattern comprises a first insulating layer and a second insulating layer disposed conformally on the first insulating layer.

4. The radio frequency device of claim 3, wherein a material composition of the second insulating layer is different from a material composition of the first insulating layer.

5. The radio frequency device of claim 3, wherein the first insulating layer is thinner than the second insulating layer.

6. The radio frequency device of claim 1, further comprising:

a gate structure disposed on the second region of the semiconductor substrate; and

a first spacer structure disposed on a sidewall of the gate structure, wherein a second portion of the mask pattern is conformally disposed on the gate structure and the first spacer structure.

7. The radio frequency device of claim 6, wherein a material composition of the gate structure is the same as a material composition of the shield structure.

8. The radio frequency device of claim 6 wherein the shield structure comprises a first portion of a patterned conductive layer and the gate structure comprises a second portion of the patterned conductive layer.

9. The radio frequency device of claim 8, wherein the patterned conductive layer is a patterned conductive polysilicon layer.

10. The radio frequency device of claim 6, further comprising:

a second spacer structure disposed on a sidewall of the shielding structure, wherein the first portion of the mask pattern is conformally disposed on the shielding structure and the second spacer structure.

11. The radio frequency device of claim 10, wherein a material composition of the first spacer structure is the same as a material composition of the second spacer structure.

12. The radio frequency device of claim 6, further comprising:

and a dielectric layer disposed on the semiconductor substrate, wherein a first portion of the dielectric layer is disposed on the first region of the semiconductor substrate and covers the first portion of the mask pattern, and a second portion of the dielectric layer is disposed on the second region of the semiconductor substrate and covers the gate structure and the second portion of the mask pattern.

13. The radio frequency device of claim 12, wherein the dielectric layer is thicker than the mask pattern.

14. The radio frequency device of claim 12, further comprising:

a silicide layer disposed between the gate structure and the second portion of the dielectric layer, wherein the silicide layer directly contacts the gate structure and the second portion of the dielectric layer.

15. The radio frequency device of claim 12, further comprising:

a dummy metal structure disposed between the first portion of the dielectric layer and the inductor structure in the vertical direction.

16. The radio frequency device of claim 15, wherein the dummy metal structure is an electrically floating metal structure.

17. The radio frequency device of claim 15, further comprising:

an interconnect structure disposed on the second portion of the dielectric layer, wherein the dummy metal structure includes a first portion of a patterned metal layer and the interconnect structure includes a second portion of the patterned metal layer.

18. The radio frequency device of claim 17, wherein the dummy metal structure is electrically separated from the interconnect structure.

19. The radio frequency device of claim 17 wherein the inductor structure comprises a first portion of a top metal conductive layer and a second portion of the top metal conductive layer is disposed on and electrically connected to the interconnect structure.

20. The rf device of claim 19 wherein the inductor structure is electrically separated from the second portion of the top metal conductive layer.

Technical Field

The present invention relates to a radio frequency device, and more particularly, to a radio frequency device having an inductor structure.

Background

Microprocessor systems composed of Integrated Circuits (ICs) have been widely used in various aspects of life, such as household appliances, mobile communication devices, personal computers, and the like, and have been traced by the ICs. With the increasing sophistication of technology and various imagination of electronic products by human society, integrated circuits are also developed in a direction of more elements, more precision and smaller size.

In response to the advent of the communication era, conventional semiconductor devices are often designed with rf circuit structures to perform wireless communication functions. In an rf device, a Q-factor (Q-factor) of an inductor (inductor) directly affects energy efficiency (energy efficiency) of the device, so how to improve the Q-factor of the rf device through design adjustment of structure and/or manufacturing process is a direction of continuous research by those skilled in the relevant art.

Disclosure of Invention

The invention provides a radio frequency device, which utilizes a mask pattern to cover a shielding structure positioned below an inductor structure, thereby reducing energy loss and achieving the effect of improving the quality factor of the inductor structure.

An embodiment of the invention provides a radio frequency device, which includes a semiconductor substrate, an inductor structure, a shielding structure and a mask pattern. The semiconductor substrate includes a first region and a second region. The inductor structure is disposed on the first region of the semiconductor substrate. The shielding structure is disposed on the first region of the semiconductor substrate and is located between the inductor structure and the semiconductor substrate in a vertical direction. The mask pattern is disposed on the semiconductor substrate, a first portion of the mask pattern is disposed on and directly contacts the shielding structure, and an upper surface of the shielding structure is completely covered by the first portion of the mask pattern.

Drawings

FIG. 1 is a schematic diagram of a radio frequency device according to an embodiment of the present invention;

fig. 2 is a schematic top view of a shielding structure of an rf device according to an embodiment of the invention;

fig. 3 is a schematic top view of a shielding structure and an inductor structure of an rf device according to an embodiment of the invention;

fig. 4 to 7 are schematic diagrams illustrating a method for manufacturing a radio frequency device according to an embodiment of the invention, wherein

FIG. 5 is a schematic view of the situation following FIG. 4;

FIG. 6 is a schematic view of the situation following FIG. 5;

fig. 7 is a schematic view of the situation after fig. 6.

Description of the main elements

10 semiconductor substrate

12 isolation structure

22 dielectric layer

22A first part

22B second part

24 patterned conductive layer

24A first part

24B second part

32 first spacer

32A first part

32B second part

34 second spacer

34A first part

34B second part

40 mask pattern

40A first part

40B second part

42 first insulating layer

44 second insulating layer

50 metal layer

52A silicide layer

52B silicide layer

54 dielectric layer

54A first part

54B second part

56 contact structure

62 virtual metal structure

64 interconnect structure

70 inductor structure

70S section

100 radio frequency device

BS bottom surface

GS grid structure

ILD interlayer dielectric layer

M1 patterned metal layer

M11 first part

Second part of M12

M2 patterned metal layer

M21 first part

Second part of M22

M3 patterned metal layer

M31 first part

Second part of M32

M4 patterned metal layer

M41 first part

Second part of M42

M5 patterned metal layer

M51 first part

Second part of M52

R1 first region

R2 second region

SP1 spacer structure

SP2 spacer structure

SS shielding structure

TM top metal conductive layer

First part of TM1

Second part of TM2

TS upper surface

TS1 Upper surface

TS2 Upper surface

TS3 Upper surface

V1 connecting plug

V2 connecting plug

V3 connecting plug

V4 connecting plug

V5 connecting plug

In the Z vertical direction

Detailed Description

The following detailed description of the invention has disclosed sufficient detail to enable those skilled in the art to practice the invention. The embodiments set forth below should be considered as illustrative and not restrictive. It will be apparent to persons skilled in the relevant art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the invention.

Before further description of the various embodiments, specific terminology used throughout the following description is set forth.

The meaning of the terms "on …", "above …" and "above …" should be read in the broadest manner such that "on …" means not only "directly on" something but also includes the meaning of being on something with other intervening features or layers in between, and "above …" or "above …" means not only "above" or "over" something, but may also include the meaning of being "above" or "over" something with no other intervening features or layers in between (i.e., directly on something).

Ordinal numbers such as "first," "second," and the like, used in the specification and the claims to modify a claim element are not by itself intended to imply any previous ordinal number with respect to the claim element, nor the order in which a claim element is ordered to another claim element or a method of manufacture, and are used solely to distinguish one claim element having a certain name from another claim element having a same name, unless otherwise specifically stated.

The term "forming" or "disposing" is used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any viable layer formation technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a radio frequency device 100 according to an embodiment of the invention. As shown in fig. 1, the radio frequency device 100 includes a semiconductor substrate 10, an inductor (inductor) structure 70, a shielding structure SS and a mask pattern 40. The semiconductor substrate 10 includes a first region R1 and a second region R2. The inductor structure 70 is disposed on the first region of the semiconductor substrate 10. The shielding structure SS is disposed on the first region R1 of the semiconductor substrate 10 and located between the inductor structure 70 and the semiconductor substrate 10 in a vertical direction Z. The mask pattern 40 is disposed on the semiconductor substrate 10, a first portion 40A of the mask pattern 40 is disposed on and directly contacts the shielding structure SS, and an upper surface TS1 of the shielding structure SS is completely covered by the first portion 40A of the mask pattern 40.

In some embodiments, the shielding structure SS under the inductor structure 70 may be formed of a conductive material to block electric field lines from passing through the semiconductor substrate 10 and reduce the coupling capacitance between the inductor structure 70 and the semiconductor substrate 10. In the present invention, the mask pattern 40 can be used to cover the design of the shielding structure SS, so as to reduce energy loss (energy loss) and improve the coupling resistance between the inductor structure 70 and the structure below the inductor structure 70, thereby achieving the effect of improving the quality factor (Q-factor) of the inductor structure 70.

In some embodiments, the vertical direction Z may be regarded as a thickness direction of the semiconductor substrate 10, the semiconductor substrate 10 may have an upper surface TS and a bottom surface BS opposite to each other in the vertical direction Z, and the inductor structure 70, the shielding structure SS and the mask pattern 40 may be disposed on one side of the upper surface TS, but not limited thereto. The horizontal direction orthogonal to the vertical direction Z may be substantially parallel to the upper surface TS or/and the bottom surface BS of the semiconductor substrate 10. Further, the distance in the vertical direction Z between the position or/and the component relatively higher in the vertical direction Z and the bottom surface BS of the semiconductor substrate 10 described herein is greater than the distance in the vertical direction Z between the position or/and the component relatively lower in the vertical direction Z and the bottom surface BS of the semiconductor substrate 10. A lower portion or a bottom portion of each component may be closer to the bottom surface BS of the semiconductor substrate 10 in the vertical direction Z than an upper portion or a top portion of the same component, another component above a certain component may be regarded as being relatively farther away from the bottom surface BS of the semiconductor substrate 10 in the vertical direction Z, and another component below a certain component may be regarded as being relatively closer to the bottom surface BS of the semiconductor substrate 10 in the vertical direction Z.

Further, in some embodiments, the rf device 100 may further include an isolation structure 12, at least one gate structure GS, a first spacer structure (e.g., the spacer structure SP2 shown in fig. 1) and a second spacer structure (e.g., the spacer structure SP1 shown in fig. 1). The isolation structure 12 may be at least partially disposed in the semiconductor substrate 10 to define a plurality of mutually separated regions in the semiconductor substrate 10, for example, but not limited to, a plurality of active (active) regions may be defined in the second region R2 of the semiconductor substrate 10. The gate structure GS may be disposed on the second region R2 of the semiconductor substrate 10, the spacer structure SP1 may be disposed on the sidewall of the shielding structure SS, and the spacer structure SP2 may be disposed on the sidewall of the gate structure GS. In some embodiments, the material composition of the spacer structure SP1 may be the same as the material composition of the spacer structure SP2, but is not limited thereto. For example, a first spacer 32 and a second spacer 34 may be disposed on the first region R1 and the second region R2 of the semiconductor substrate 10, and the second spacer 34 may be disposed on the first spacer 32, the spacer structure SP1 may include a first portion 32A of the first spacer 32 and a first portion 34A of the second spacer 34, and the spacer structure SP2 may include a second portion 32B of the first spacer 32 and a second portion 34B of the second spacer 34. The first and second spacers 32 and 34 may each comprise a single layer or multiple layers of insulating material, such as silicon oxide, silicon nitride, or other suitable insulating materials.

In some embodiments, a first portion 40A of the mask pattern 40 may be conformally disposed on the shielding structure SS and the spacer structure SP1, and a second portion 40B of the mask pattern 40 may be conformally disposed on the gate structure GS, the spacer structure SP2 and the second region R2 of the semiconductor substrate 10. It should be noted that, in some embodiments, a plurality of gate structures GS may be disposed on the second region R2 of the semiconductor substrate 10, and the two gate structures GS illustrated in fig. 1 may be two gate structures GS separated from each other or a cross-sectional view of the same gate structure GS at different portions. Accordingly, the gate structure GS may be only partially covered by the second portion 40B of the mask pattern 40 in the vertical direction Z and not completely covered by the second portion 40B of the mask pattern 40.

The mask pattern 40 may include a single layer or multiple layers of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating material. In some embodiments, the mask pattern 40 may include a first insulating layer 42 and a second insulating layer 44, the second insulating layer 44 may be conformally disposed on the first insulating layer 42, and the material composition of the second insulating layer 44 may be different from that of the first insulating layer 42. For example, the first insulating layer 42 may be a silicon oxide layer, and the second insulating layer 44 may be a silicon nitride layer, but not limited thereto. In addition, in some embodiments, the first insulating layer 42 can be regarded as a liner layer, and the second insulating layer 44 can be regarded as a main mask material, so the first insulating layer 42 can be thinner than the second insulating layer 44, i.e., the thickness of the first insulating layer 42 in the vertical direction Z can be smaller than the thickness of the second insulating layer 44 in the vertical direction Z, but not limited thereto. In some embodiments, the first portion 40A of the mask pattern 40 may be composed of the first and second insulating layers 42 and 44 disposed on the first region R1 of the semiconductor substrate 10, and the second portion 40B of the mask pattern 40 may be composed of the first and second insulating layers 42 and 44 disposed on the second region R2 of the semiconductor substrate 10, so that the material composition of the first portion 40A of the mask pattern 40 may be the same as that of the second portion 40B of the mask pattern 40.

In some embodiments, the material composition of the gate structure GS may be the same as that of the shield structure SS. For example, a patterned conductive layer 24 may be disposed on the first region R1 and the second region R2 of the semiconductor substrate 10, the shielding structure SS may include a first portion 24A of the patterned conductive layer 24, and the gate structure GS may include a second portion 24B of the patterned conductive layer 24. The patterned conductive layer 24 may include a conductive material containing silicon, such as a doped polysilicon material or other suitable conductive materials, and the patterned conductive layer 24 may be a patterned conductive polysilicon layer, but is not limited thereto. In some embodiments, the rf device 100 may further include a dielectric layer 22 disposed on the first region R1 and the second region R2 of the semiconductor substrate 10, wherein a first portion 22A of the dielectric layer 22 may be disposed between the shielding structure SS and the semiconductor substrate 10 in the vertical direction Z, and a second portion 22B of the dielectric layer 22 may be disposed between the gate structure GS and the semiconductor substrate 10 in the vertical direction Z. The dielectric layer 22 may comprise an oxide layer, such as a silicon oxide layer or other suitable dielectric material, while the second portion 22B of the dielectric layer 22 may be considered a gate dielectric layer.

In some embodiments, the shielding structure SS may be an electrically floating (electrically floating) conductive structure, for example, and may be completely covered by an insulating material (such as the first portion 40A of the mask pattern 40, the spacer structure SP1, and the first portion 22A of the dielectric layer 22), but not limited thereto. In other words, the first portion 24A and the second portion 24B of the patterned conductive layer 24 can be physically and electrically separated from each other. In addition, in some embodiments, the mask pattern 40 may be regarded as a blocking layer for blocking the formation of the salicide layer, so that the gate structure GS not covered by the mask pattern 40 on the second region R2 of the semiconductor substrate 10 and the salicide layer may be formed on the semiconductor substrate 10. For example, the rf device 100 may further include a silicide layer 52A and a silicide layer 52B, the silicide layer 52A may be disposed on the second region R2 of the semiconductor substrate 10 and directly contact the semiconductor substrate 10, and the silicide layer 52B may be disposed on the gate structure GS and directly contact the gate structure GS. Silicide layers 52A and 52B may comprise cobalt-metal silicide (cobalt-silicide), nickel-metal silicide (nickel-silicide), or other suitable metal silicide.

In some embodiments, the silicide layer 52B may include a material converted from a portion of the gate structure GS, but the upper surface TS3 of the silicide layer 52B may still be higher in the vertical direction Z than the upper surface TS2 of the gate structure GS in other regions, and the upper surface TS1 of the shielding structure SS and the upper surface TS2 of the gate structure GS may be located in the same plane orthogonal to the vertical direction Z, but not limited thereto. Therefore, compared to the situation where the silicide layer is directly formed on the shielding structure SS, the use of the first portion 40A of the mask pattern 40 to completely cover the shielding structure SS to avoid forming the silicide layer on the shielding structure SS can increase the overall resistance of the semiconductor substrate 10 and the shielding structure and relatively increase the distance between the inductor structure 70 and the shielding structure (especially when the first portion 24A of the patterned conductive layer 24 and the silicide layer formed thereon can be collectively referred to as the shielding structure), thereby reducing the energy loss (energy loss) caused by the substrate. In other words, in some embodiments, the shielding structure SS may be formed of only a polysilicon material without the silicide (e.g., metal silicide) described above. In addition, the quality factor of the inductor structure 70 is proportional to the ratio of the stored energy to the energy loss per oscillation cycle (i.e., inversely proportional to the energy loss per oscillation cycle), wherein the energy loss includes the energy loss caused by metal and the energy loss caused by substrate, the energy loss caused by metal may include, for example, DC loss and skin effect (skin effect) loss, and the energy loss caused by substrate may include substrate current caused by electric field and eddy current (eddy current) loss. Therefore, the first portion 40A of the mask pattern 40 completely covers the shielding structure SS in the vertical direction Z to prevent the formation of a silicide layer on the shielding structure SS, which may reduce the energy loss caused by the substrate, thereby improving the quality factor of the inductor structure 70 and the device performance of the rf device 100.

In some embodiments, the rf device 100 may further include a dielectric layer 54 disposed on the first region R1 and the second region R2 of the semiconductor substrate 10, a first portion 54A of the dielectric layer 54 may be disposed on the first region R1 of the semiconductor substrate 10 and cover the first portion 40A of the mask pattern 40, and a second portion 54B of the dielectric layer 54 may be disposed on the second region R2 of the semiconductor substrate 10 and cover the gate structure GS, the silicide layer 52A, the silicide layer 52B, the spacer structure SP2 and the second portion 40B of the mask pattern 40. The silicide layer 52B may be disposed between the gate structure GS and the second portion 54B of the dielectric layer 54, and the silicide layer 52B may directly contact the gate structure GS and the second portion 54B of the dielectric layer 54. In addition, in some embodiments, the rf device 100 may further include one or more contact structures 56 penetrating the dielectric layer 54 on the second region R2 in the vertical direction Z for making electrical connection with the silicide layer 52A or the silicide layer 52B. In some embodiments, the dielectric layer 54 may have a planarization effect and need a relatively thick thickness, so the dielectric layer 54 may be thicker than the mask pattern 40, i.e., the thickness of the dielectric layer 54 in the vertical direction Z may be greater than the thickness of the mask pattern 40 in the vertical direction Z, but not limited thereto.

In some embodiments, the radio frequency device 100 may further include a dummy metal structure 62, an interconnect structure 64, and an inter-layer dielectric ILD. An ILD may be disposed on the dielectric layer 54 and over the first and second regions R1 and R2 of the semiconductor substrate 10. Dummy metal structure 62 may be disposed between first portion 54A of dielectric layer 54 and inductor structure 70 in vertical direction Z, interconnect structure 64 may be disposed on second portion 54B of dielectric layer 54, and dummy metal structure 62, interconnect structure 64, and inductor structure 70 may be at least partially disposed in inter-layer dielectric ILD. In some embodiments, the dummy metal structure 62 may be an electrically floating metal structure, and the interconnect structure 64 may be electrically connected to active devices (e.g., transistors corresponding to the gate structures GS) or/and passive (passive) devices on the semiconductor substrate 10.

For example, the rf device 100 may include a plurality of metal layers (e.g., the patterned metal layer M1, the patterned metal layer M2, the patterned metal layer M3, the patterned metal layer M4, the patterned metal layer M5, and the top metal conductive layer TM shown in fig. 1) disposed on the dielectric layer 54 and stacked in the vertical direction Z. The dummy metal structure 62 may include a first portion M11 of the patterned metal layer M1, a first portion M21 of the patterned metal layer M2, a first portion M31 of the patterned metal layer M3, a first portion M41 of the patterned metal layer M4, or/and a first portion M51 of the patterned metal layer M5, and the interconnect structure 64 may include a second portion M12 of the patterned metal layer M1, a second portion M22 of the patterned metal layer M2, a second portion M32 of the patterned metal layer M3, a second portion M42 of the patterned metal layer M4, and a second portion M52 of the patterned metal layer M5. In addition, inductor structure 70 may include a first portion TM1 of top metal conductive layer TM, and a second portion TM2 of top metal conductive layer TM may be disposed on interconnect structure 64 and electrically connected to interconnect structure 64.

In some embodiments, the rf device 100 may include a plurality of connection plugs (e.g., the connection plug V1, the connection plug V2, the connection plug V3, the connection plug V4, and the connection plug V5 shown in fig. 1) electrically connected to the metal layers (e.g., the second portion M12 of the patterned metal layer M1, the second portion M22 of the patterned metal layer M2, the second portion M32 of the patterned metal layer M3, the second portion M42 of the patterned metal layer M4, the second portion M52 of the patterned metal layer M5, and the second portion TM2 of the top metal conductive layer TM) alternately stacked in the vertical direction Z. In addition, the dummy metal structures 62 may be electrically floating metal structures and electrically separated from the interconnect structure 64, so that the first and second portions of each patterned metal layer may be physically and electrically separated from each other. In addition, in some embodiments, the inductor structure 70 may be electrically separated from the second portion TM2 of the top metal conductive layer TM, and the inductor structure 70 may be electrically connected to corresponding devices through other portions of the patterned metal layer, such as devices formed on the second region R2 of the semiconductor substrate 10 or devices formed on regions of the semiconductor substrate 10 other than the first region R1 and the second region R2.

In some embodiments, the substrate 10 may include a semiconductor substrate such as a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials. Isolation structures 12 may comprise a single layer or multiple layers of insulating material such as silicon oxide, silicon nitride, or other suitable insulating materials. The dielectric layer 22 may comprise an oxide layer such as a silicon oxide layer or other suitable dielectric material. The dielectric layer 54 may comprise a single layer or multiple layers of an insulating material such as silicon oxide, silicon nitride, or other suitable dielectric material. The ILD may comprise a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide nitride, Fluorinated Silicate Glass (FSG), low dielectric constant (low-k) dielectric materials, or other suitable dielectric materials. The low-k dielectric material may include a dielectric material with a relatively low dielectric constant (e.g., but not limited to, a dielectric constant less than 2.9), such as benzocyclobutene (BCB), hsq (hydrogen silsesquioxane), msq (methyl silsesquioxane), silicon oxy-carbon hydride (SiOC-H), and/or a porous dielectric material. The contact structure 56, the patterned metal layers, the connecting plugs and the top metal conductive layer TM may respectively include a low resistance material and a barrier layer, the low resistance material may include a material with relatively low resistivity, such as copper, aluminum, tungsten, etc., and the barrier layer may include tin, tan or other suitable barrier materials, but not limited thereto.

Please refer to fig. 2, fig. 3 and fig. 1. Fig. 2 is a top view of a shielding structure SS of a radio frequency device according to an embodiment of the invention, and fig. 3 is a top view of the shielding structure SS and an inductor structure 70 of the radio frequency device according to an embodiment of the invention. As shown in fig. 1 to 3, in some embodiments, the first portion 24A of the patterned conductive layer 24 may be a pattern with mirror symmetry characteristics, so as to uniformly control the shielding effect of the shielding structure SS, but not limited thereto. In addition, the inductor structure 70 may have a plurality of sections 70S that are not directly connected, and each section 70S may be electrically connected to each other or to different elements respectively through other portions of the patterned metal layer. It should be noted that the pattern design of the shielding structure SS and the inductor structure 70 of the present invention is not limited to the situation shown in fig. 2 and 3, and the shielding structure SS and/or the inductor structure 70 having other pattern features may be used according to the design requirement. Furthermore, in some embodiments, the first region R1 may be considered as an inductor region in the rf device 100, the second region R2 may be considered as another circuit region in the rf device 100, and no active devices such as transistors may be disposed in the first region R1 and on the first region R1, thereby reducing negative effects on the operation of the inductor structure 70.

Please refer to fig. 4 to 7 and fig. 1. Fig. 4 to 7 are schematic diagrams illustrating a method for manufacturing a radio frequency device according to an embodiment of the present invention, wherein fig. 5 is a schematic diagram illustrating a situation after fig. 4, fig. 6 is a schematic diagram illustrating a situation after fig. 5, fig. 7 is a schematic diagram illustrating a situation after fig. 6, and fig. 1 can be regarded as a schematic diagram illustrating a situation after fig. 7. The method for fabricating the rf switch device 101 of the present embodiment may include, but is not limited to, forming the isolation structure 12, the dielectric layer 22, the patterned conductive layer 24, the first spacer 32 and the second spacer 34 on the semiconductor substrate 10, and forming the shielding structure SS and the gate structure GS respectively from the first portion 24A and the second portion 24B of the patterned conductive layer 24, as shown in fig. 4, so that the shielding structure SS and the gate structure GS may be formed together by the same fabrication process, thereby achieving the effect of simplifying the fabrication process, and the upper surface TS1 of the shielding structure SS and the upper surface TS2 of the gate structure GS may be substantially located in the same plane orthogonal to the vertical direction Z. Then, as shown in fig. 4 to 5, the mask pattern 40 may be formed, and at least a portion of the gate structure GS and at least a portion of the second region R2 of the semiconductor substrate 10 may not be covered by the mask pattern 40.

Then, as shown in fig. 6, a metal layer 50 may be globally formed, and the metal layer 50 may directly contact the second region R2 of the semiconductor substrate 10 and the gate structure GS that are not covered by the mask pattern 40. Thereafter, as shown in fig. 6 to 7, a heat treatment may be performed to react the metal layer 50 with the gate structure GS and the semiconductor substrate 10 to form the silicide layer 52A and the silicide layer 52B, and the metal layer 50 may be removed after the silicide layer 52A and the silicide layer 52B are formed. In some embodiments, metal layer 50 may comprise cobalt, nickel, or other suitable metal material, and silicide layers 52A and 52B may comprise cobalt-metal silicide, nickel-metal silicide, or other corresponding silicides of the metal materials of metal layer 50. Thereafter, as shown in fig. 7 and 1, the dielectric layer 54, the contact structure 56, the inter-layer dielectric ILD, the dummy metal structure 62, the interconnect structure 64, the inductor structure 70, and/or other required components may be formed, thereby forming the rf device 100 shown in fig. 1.

In summary, in the rf device of the present invention, the shielding structure under the inductor structure can be covered by the mask pattern, so as to reduce the energy loss and achieve the effect of improving the quality factor of the inductor structure.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.