阅读说明：本技术 电感器件布线架构、集成电路及通信设备 (Inductance device wiring architecture, integrated circuit and communication equipment ) 是由 叶辉 于 2019-03-29 设计创作，主要内容包括：本申请实施例公开一种电感器件布线架构,包括电感器件及位于电感器件下方的多个虚拟金属。其中,多个虚拟金属排布在多层金属层中,多层金属层中每层金属层对应多个虚拟金属的部分虚拟金属,在远离电感器件的方向上,多层金属层中的至少两层金属层对应的虚拟金属的排布面积递增。上述电感器件布线架构能够减少对电感器件性能的不良影响,并提高产品良率。本申请实施例还公开一种集成电路和一种通信设备。(The embodiment of the application discloses inductance device wiring framework, including inductance device and a plurality of dummy metal that are located inductance device below. The plurality of virtual metals are distributed in the plurality of metal layers, each metal layer in the plurality of metal layers corresponds to part of the virtual metals of the plurality of virtual metals, and the distribution areas of the virtual metals corresponding to at least two metal layers in the plurality of metal layers are increased in the direction away from the inductor. The wiring structure of the inductance device can reduce the adverse effect on the performance of the inductance device and improve the product yield. The embodiment of the application also discloses an integrated circuit and communication equipment.)

An inductive device routing architecture, comprising:

the inductor comprises an inductor and a plurality of dummy metals positioned below the inductor;

the plurality of dummy metals are arranged in the plurality of metal layers, each metal layer in the plurality of metal layers corresponds to part of the dummy metals, and the arrangement area of the dummy metals corresponding to at least two metal layers in the plurality of metal layers increases progressively in the direction away from the inductor.

The inductive device wiring architecture of claim 1, wherein the plurality of dummy metals are arranged in a staircase pattern.

The inductive device wiring architecture of claim 1 or 2, wherein, in the plurality of metal layers, an arrangement area of dummy metals corresponding to at least three metal layers disposed adjacent to each other increases in a direction away from the inductive device.

The inductive device wiring architecture of any of claims 1 to 3, wherein an arrangement area of a dummy metal corresponding to an i-th metal layer under the inductive device is equal to an arrangement area of a dummy metal corresponding to an i-1-th metal layer, the i-th metal layer is located on a side of the i-1-th metal layer away from the inductive device, and i is an integer and greater than or equal to 2.

The wiring structure of claim 4, wherein the plurality of dummy metals corresponding to the ith metal layer are arranged at equal intervals, and an arrangement interval between two adjacent dummy metals is the ith interval; the plurality of virtual metals corresponding to the (i-1) th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the (i-1) th interval; the i-1 th spacing is less than the ith spacing.

The layout architecture of the inductor device according to any one of claims 1 to 5, wherein an arrangement area of a dummy metal corresponding to a jth metal layer below the inductor device is smaller than an arrangement area of a dummy metal corresponding to a jth metal layer located on a side of the jth metal layer away from the inductor device, where j is an integer and greater than or equal to 2.

The layout structure of the inductor device according to claim 6, wherein the plurality of dummy metals corresponding to the jth metal layer are arranged at equal intervals, and an arrangement interval between two adjacent dummy metals is the jth interval; the plurality of virtual metals corresponding to the j-1 th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the j-1 th interval; the j-1 th spacing is less than the j-th spacing.

The inductive device wiring architecture of any one of claims 1 to 7, wherein under the inductive device, the number of dummy metals corresponding to each metal layer is plural, and the dummy metals corresponding to each metal layer are arranged to cross the dummy metals corresponding to adjacent metal layers.

The inductive device wiring architecture of any one of claims 1 to 5 and 7, wherein under the inductive device, the number of the dummy metals of each metal layer is plural, and the dummy metal corresponding to each metal layer is aligned with the dummy metal corresponding to an adjacent metal layer.

The inductive device wiring architecture of any one of claims 1 to 7, wherein under the inductive device, the number of the dummy metals corresponding to each metal layer is plural, and the dummy metals corresponding to one or more metal layers are arranged to cross the dummy metals corresponding to the adjacent metal layers, and the dummy metals corresponding to one or more metal layers are arranged to align with the dummy metals corresponding to the adjacent metal layers.

The inductive device wiring architecture of any of claims 1 to 10, wherein the inductive device is an inductor with two ports or a transformer with four ports.

The inductive device wiring architecture of any of claims 1 to 11, wherein the inductive devices are arranged in a same metal layer; or the inductance device comprises an upper inductance and a lower inductance, and the upper inductance and the lower inductance are arranged in two adjacent metal layers.

An integrated circuit comprising the inductive device wiring architecture of any of claims 1 to 12.

A communication device comprising the integrated circuit of claim 13.