阅读说明：本技术 氮化镓hemt芯片整合封装结构及其制造方法 (Gallium nitride HEMT chip integrated packaging structure and manufacturing method thereof ) 是由 谢文华 任炜强 于 2021-08-09 设计创作，主要内容包括：涉及氮化镓HEMT芯片整合封装结构及其制造方法,结构依照封装工序依序包括位于封装底面的散热载片、氮化镓HEMT芯片、第一封装胶层、扇出线路层、MOSFET芯片、第二封装胶层及金属岛层。扇出线路层的第一源极内岛形成于偏离氮化镓HEMT芯片的区块中,漏极线路的一端扇出延伸以远离氮化镓HEMT芯片,柵极线路位于第一源极内岛与漏极线路之间;MOSFET芯片设置于第一源极内岛上,使MOSFET芯片的漏极有间隔连接至氮化镓HEMT芯片的源极;金属岛层的第二源极内岛导通互连MOSFET芯片的第二源极垫与柵极线路,使MOSFET芯片的源极短路径连接氮化镓HEMT芯片的柵极,MOSFET芯片位于不同于氮化镓HEMT芯片的封装胶层中,结构具有减少寄生电感与提高MOSFET芯片反应灵敏的效果。(The structure sequentially comprises a heat dissipation slide glass positioned on the bottom surface of the package, a gallium nitride HEMT chip, a first package adhesive layer, a fan-out line layer, an MOSFET chip, a second package adhesive layer and a metal island layer according to the packaging procedure. The first source electrode inner island of the fan-out circuit layer is formed in a block deviating from the gallium nitride HEMT chip, one end of the drain electrode circuit extends in a fan-out mode to be far away from the gallium nitride HEMT chip, the gate electrode circuit is located between the first source electrode inner island and the drain electrode circuit, the MOSFET chip is arranged on the first source electrode inner island, the drain electrode of the MOSFET chip is connected to the source electrode of the gallium nitride HEMT chip at intervals, the second source electrode inner island of the metal island layer is in conduction and interconnection with a second source electrode pad and a gate electrode circuit of the MOSFET chip, the source electrode short-circuit path of the MOSFET chip is connected with the gate electrode of the gallium nitride HEMT chip, the MOSFET chip is located in a packaging adhesive layer different from the gallium nitride HEMT chip, and the structure has the effects of reducing parasitic inductance and improving reaction sensitivity of the MOSFET chip.)

1. A gallium nitride HEMT chip integration packaging structure is characterized in that, includes:

a heat sink slide located on the bottom surface of the package;

the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source electrode pad, a first grid electrode pad and a first drain electrode pad;

the first packaging adhesive layer is formed on the heat dissipation carrier to seal the gallium nitride HEMT chip, the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and the first packaging adhesive layer is provided with a first through hole to expose the first source pad, the first gate pad and the first drain pad;

a fan-out wiring layer formed on the first encapsulation glue layer, the fan-out wiring layer including: a first source inner island communicated with the first source pad through a through hole, a gate line communicated with the first gate pad through the through hole, and a drain line communicated with the first drain pad through the through hole, wherein the first source inner island is formed in a block deviated from the gallium nitride HEMT chip, one end of the drain line is fanned out and extended to be far away from the gallium nitride HEMT chip, and the gate line is positioned between the first source inner island and the drain line;

the MOSFET chip is arranged on the first source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;

a second packaging adhesive layer formed on the first packaging adhesive layer and the fan-out circuit layer, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and the second packaging adhesive layer is provided with a second through hole to expose the second source pad and the second gate pad;

a metal island layer formed on the second encapsulation glue layer, the metal island layer comprising: the through hole is communicated with and interconnects the second source electrode pad and the second source electrode inner island of the gate electrode circuit, and the through hole is communicated with the gate electrode inner island of the second gate electrode pad;

the radiating carrier is divided into a source outer island, a gate outer island and a drain outer island, wherein the source outer island is arranged at the periphery of the radiating main island and is communicated with the second source inner island, the gate outer island is communicated with the gate inner island, and the drain outer island is communicated with the fan-out end of the drain circuit;

with the opening or closing of the MOSFET chip in the positive and negative voltage working range of the gate outer island, the potential of the first source pad of the gallium nitride HEMT chip can be synchronously adjusted down or up so as to synchronously open or close the gallium nitride HEMT chip.

2. The integrated package structure of gallium nitride HEMT chip of claim 1, wherein the off-state voltage of the first drain pad of the gallium nitride HEMT chip is between 100-600V through the outer drain island, the first gate pad of the gallium nitride HEMT chip is shorted with the second source pad of the MOSFET chip through the inner second source island, the off-state and on-state voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0V, and the voltage of the first source pad of the gallium nitride HEMT chip is passively raised when the MOSFET chip is turned off at the source and drain, and the voltage of the first gate pad of the gallium nitride HEMT chip is not more than ≦ 0V to turn on the gallium nitride HEMT chip.

3. The integrated package structure of gallium nitride HEMT chip of claim 1, wherein the off-state operating voltage of the outer gate island is ≦ 0V, the on-state operating voltage of the outer gate island is 3-20V, and a Schottky diode is reversely disposed in the MOSFET chip.

4. The integrated package structure of GaN HEMT chip of any of claims 1-3, wherein the first source inner island is relatively offset from the GaN HEMT chip and has a size larger than the first source pad, and the first source inner island has a size larger than and a contour corresponding to the backside of the MOSFET chip, so that the drain layer is substantially bonded to the first source inner island.

5. The integrated package structure of gallium nitride HEMT chip according to claim 4, wherein the second source inner island is offset and has a size larger than the first source inner island, and the through hole of the first package glue layer electrically connected to the second source inner island corresponds to the through hole of the second package glue layer in a through manner to shorten the conduction path to less than 100um, and the package internal resistance of the integrated package structure of gallium nitride HEMT chip is less than 0.2 milliohm.

6. A gallium nitride HEMT chip integration packaging structure comprises: the heat dissipation carrier capable of establishing an external heat dissipation path, a gallium nitride HEMT chip arranged on the heat dissipation carrier, an MOSFET chip sealed in a FOPLP packaging adhesive layer and a FOPLP circuit structure, wherein the FOPLP circuit structure comprises a grid electrode inner island, a first source electrode inner island and a second source electrode inner island, the first source electrode inner island is positioned in the FOPLP packaging adhesive layer, the source electrode of the gallium nitride HEMT chip and the drain electrode of the MOSFET chip are connected in an interlayer mode, the second source electrode inner island and the grid electrode inner island are positioned on one surface of the FOPLP packaging adhesive layer, and the grid electrode of the gallium nitride HEMT chip and the source electrode of the MOSFET chip are short-circuited in a long and short through hole mode, and the heat dissipation carrier is split to comprise: the source outer island is conducted to the second source inner island, the gate outer island is conducted to the gate inner island, and the drain outer island is conducted to the fan-out end of the drain circuit of the FOPLP circuit structure.

7. The integrated package structure of GaN HEMT chip of claim 6, wherein the heat sink chip further comprises a heat sink main island, the back surface of the GaN HEMT chip is thermally coupled to the heat sink main island, the gate inner island is located on the same surface of the FOPLP package adhesive layer as the second source inner island, and the drain outer island is originally connected to the gate of the MOSFET chip.

8. A manufacturing method of a gallium nitride HEMT chip integrated packaging structure is characterized by comprising the following steps:

providing a heat dissipation slide;

arranging a gallium nitride HEMT chip on the heat dissipation carrier, so that the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;

forming a first packaging adhesive layer on the heat dissipation chip in a flat plate molding manner to seal the gallium nitride HEMT chip, wherein the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and a first through hole is formed in the first packaging adhesive layer to expose the first source pad, the first gate pad and the first drain pad;

forming a fan-out wiring layer on the first encapsulation glue layer, the fan-out wiring layer comprising: a first source inner island communicated with the first source pad through a through hole, a gate line communicated with the first gate pad through the through hole, and a drain line communicated with the first drain pad through the through hole, wherein the first source inner island is formed in a block deviated from the gallium nitride HEMT chip, one end of the drain line is fanned out and extended to be far away from the gallium nitride HEMT chip, and the gate line is positioned between the first source inner island and the drain line;

arranging an MOSFET chip on the first source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;

forming a second packaging adhesive layer on the first packaging adhesive layer and the fan-out circuit layer in a flat plate molding manner, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and a second through hole is formed in the second packaging adhesive layer so as to expose the second source pad and the second gate pad;

forming a metal island layer on the second encapsulation glue layer, wherein the metal island layer comprises: the through hole is communicated with and interconnects the second source electrode pad and the second source electrode inner island of the gate electrode circuit, and the through hole is communicated with the gate electrode inner island of the second gate electrode pad;

the heat dissipation carrier is divided into a source outer island, a gate outer island and a drain outer island, wherein the source outer island is arranged at the periphery of the heat dissipation main island and is communicated with the second source inner island, the gate outer island is communicated with the gate inner island, and the drain outer island is communicated with the fan-out end of the drain circuit.

9. The method for manufacturing the integrated package structure of the gallium nitride HEMT chip according to claim 8, wherein:

in the step of arranging the gallium nitride HEMT chip, the first gate pad is configured between the first source pad and the first drain pad;

or/and in the step of forming the first packaging adhesive layer in a flat plate molding manner, the first packaging adhesive layer also covers the peripheral side edges of the heat dissipation slide glass;

or/and in the step of forming the fan-out line layer, the first source inner island is relatively deviated from the gallium nitride HEMT chip and has a larger size than the first source pad, and the size of the first source inner island is larger than the size of the first source inner island and the outline of the first source inner island corresponds to the back surface of the MOSFET chip;

or/and, in the step of disposing the MOSFET chip on the first source inner island, the drain layer is fully and substantially bonded to the first source inner island;

or/and, in the step of forming the metal island layer, the second source electrode inner island is relatively deviated and has a size larger than that of the first source electrode inner island, and the through hole of the first packaging adhesive layer electrically connected with the second source electrode inner island corresponds to the through hole of the second packaging adhesive layer in a straight-through manner, so as to shorten a conduction path to be less than 100um, and further enable the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure to be controlled to be less than 0.2 milliohm;

or/and the manufacturing method further comprises a step of packaging and separating to obtain a separated gallium nitride HEMT chip integrated packaging structure, wherein the off working voltage of the first drain pad of the gallium nitride HEMT chip is between 100 and 600V through the outer drain island, the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip are in short circuit through the inner second source island, the off and on working voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0V, when the source and drain of the MOSFET chip are closed, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised through the outer gate island, the voltage of the first gate pad of the gallium nitride HEMT chip is not more than 0V, preferably, the off working voltage of the outer gate island is less than 0V, the opening working voltage of the gate outer island is 3-20V, and a Schottky diode is arranged in the MOSFET chip in a reverse direction.

10. An electronic device, comprising: the integrated package structure comprises a printed circuit board and the integrated package structure of the GaN HEMT chip, wherein the integrated package structure is jointed on the printed circuit board, the outer source island, the outer gate island and the outer drain island which are positioned on the same surface in the package bottom surface of the integrated package structure of the GaN HEMT chip are respectively welded to corresponding pins of the printed circuit board, the back surface of the MOSFET chip is not directly thermally coupled with the GaN HEMT chip under the barrier of a package glue layer, and a horizontal electric connection path between the drain electrode of the MOSFET chip and the source electrode of the GaN HEMT chip does not exceed the projection area of the MOSFET chip on the package bottom surface.

Technical Field

The invention relates to the technical field of packaging of gallium nitride HEMT chips, in particular to an integrated packaging structure of a gallium nitride HEMT chip and a manufacturing method thereof.

Background

The base material of the working layer of a gallium nitride HEMT (high electron mobility transistor) chip is gallium nitride (GaN), and the base material of the working layer of a MOSFET chip is silicon (Si). Due to the material characteristics, a PN junction cannot be arranged in the gallium nitride HEMT chip, the conduction between the source electrode and the drain electrode is conducted through the middle electronic layer, and the gallium nitride HEMT chip can be turned off only by applying a sufficient negative voltage on the gate electrode. Therefore, the gan HEMT chip has the advantage of fast switching speed compared to a MOSFET (metal oxide semiconductor field effect transistor) chip, but based on the structural characteristics, the switching on operation of the gate needs to be within the working range of negative voltage, when the gate is grounded or the voltage is 0V, the gan HEMT chip is turned on, and a sufficiently large negative voltage needs to be given, so that the source and the drain of the gan HEMT chip are turned off, and thus, the risk of power consumption and leakage current exists. Therefore, the power device of the gan HEMT mainly solves the problem of how to switch on the switch in the working range of positive voltage (including voltage 0V) to realize that the gate is grounded or the gan HEMT chip is turned off under the voltage 0V, and various prior arts are available at present.

The invention patent publication No. CN103872119A discloses a high electron mobility transistor and a method of manufacturing the same, the HEMT includes: the device comprises a substrate, a first gallium nitride layer, a P-type gallium nitride layer, a second gallium nitride layer, a barrier layer, a grid, a source and a drain. The first gallium nitride layer is formed on the substrate, viewed from a cross section, the first gallium nitride layer has a step profile, and the P-type gallium nitride layer is formed on the upper step surface of the step profile and is provided with an enhanced side wall; the second gallium nitride layer is formed on the P-type gallium nitride layer, and the barrier layer is formed on the second gallium nitride layer, so that a two-dimensional electron cloud (2-delctron gas,2DEG) is formed between the barrier layer and the second gallium nitride layer. The grid is formed outside the enhanced side wall and used for receiving grid voltage so as to conduct or not conduct the HEMT. That is to say, the technical scheme for realizing the gate switch conduction in the positive voltage working range is to perform the step-shaped process change in the chip structure, that is, the internal chip structure of the existing gallium nitride HEMT chip needs to be changed, and the reliability and other characteristics of the chip need to be verified again.

The invention patent publication No. CN112768427A discloses a packaging structure and a packaging method of a gallium nitride HEMT, and a gallium nitride HEMT chip has high switch-on speed but high heat generation in use. In order to improve the heat dissipation performance of the packaging structure, the to-be-packaged gallium nitride HEMT chip is fixed and electrically connected in the heat dissipation area, the grid electrode of the to-be-packaged gallium nitride HEMT chip is positioned between the source electrode and the drain electrode, the parasitic inductance of the driving loop is reduced, and the source electrode and the second conductive bonding pad are electrically connected through the fourth electric connection component to form the Kelvin source electrode. In the prior art, a gan HEMT chip is usually a single chip package structure, and a pin-less lead frame is used to increase heat dissipation performance, but the technical problem of gate switch conduction in a positive voltage working range cannot be solved.

The invention discloses a high-current cascade enhanced GaN full-bridge power module packaging structure and a packaging method, wherein the structure comprises a packaging shell, a metal lead frame and pins, and the packaging shell also comprises: the HEMT device comprises a first cascade enhancement type GaN HEMT device, a second cascade enhancement type GaN HEMT device, a third cascade enhancement type GaN HEMT device, a fourth cascade enhancement type GaN HEMT device and a full-bridge gate driving circuit. Any cascade enhancement mode GaN HEMT device in the module provided by the prior patent realizes large current by connecting a plurality of GaN HEMT devices in parallel; in addition, a voltage regulation circuit is required to be added to ensure that the internal high-voltage depletion type GaN device works in a safe region state. In the prior patent, a plurality of GaN HEMTs are connected in parallel to achieve the purpose of large current; it is not specifically disclosed how the additional voltage regulator circuit is integrated into the package structure, and it can be seen from the figure that the conventional way of connecting the chips side by side and the wire bonding is still adopted. Among the relevant prior art, the setting of a large amount of routing binding lines must produce great parasitic inductance in packaging structure, is unfavorable for improving gallium nitride HEMT power device's operating frequency, and the lead wire mode of binding lines has the encapsulation internal resistance simultaneously, also can cause the electrical loss to need great encapsulation size just can seal two above chips down, be unfavorable for packaging structure's miniaturization. In order to reduce the inductance, an additional DBC insulating sheet is required inside another type of similar package structure, and the insulating sheet is a poor thermal conductor, which is not favorable for heat dissipation of the package structure.

In addition, patent publication No. CN110504242A discloses a GaN epitaxial structure having a PN junction, in which a PN junction is formed between an N-type GaN semiconductor layer and a P-type GaN semiconductor layer, the P-type GaN semiconductor layer is formed on a nucleation layer, and the N-type GaN semiconductor layer is formed on the P-type GaN semiconductor layer and forms a PN junction with the P-type GaN semiconductor layer. The P-type GaN semiconductor layer is made of P-type GaN or P-type AlGaN, and the N-type GaN semiconductor layer is made of N-type GaN or N-type AlGaN. The related art of the patent does not disclose a specific dopant, and if aluminum (Al) is used as a dopant, the GaN semiconductor layer is necessarily P-type. The PN junction composed of the P-type GaN and the P-type GaN can form a quantum well effect, namely the PN junction of the most basic structure of the LED, and belongs to the field of semiconductor light emitting, so that the PN junction is not arranged inside a gallium nitride HEMT chip in the existing visible product.

Disclosure of Invention

The invention mainly aims to provide a gallium nitride HEMT chip integrated packaging structure, which has the effect of switching on and off a gate electrode of the packaging structure in a positive voltage working range so as to close the gallium nitride HEMT chip under grounding or 0V, does not need to change the internal chip structure of the existing gallium nitride HEMT chip, and solves the problem of power consumption and leakage current caused by the fact that the gate electrode in the existing gallium nitride HEMT chip packaging structure can be switched off in a negative voltage working range. In a practical application, the package structure can be turned off by 0V of the surface gate and turned on by 5V of the gallium nitride HEMT chip.

The second objective of the present invention is to provide a method for manufacturing an integrated package structure of a gallium nitride HEMT chip, which effectively integrates the gallium nitride HEMT chip and the MOSFET chip in a structure conforming to the preferential heat dissipation of the gallium nitride HEMT chip, thereby reducing the difficulty of integrating a heterogeneous chip in semiconductor package manufacturing and improving the production smoothness of the package process flow.

The third objective of the present invention is to provide an electronic device, which can rapidly derive the internal heat of the gallium nitride HEMT chip, thereby reducing the influence of the heat generated by the gallium nitride HEMT chip on the electrical performance of the MOSFET chip.

The main purpose of the invention is realized by the following technical scheme:

a gallium nitride HEMT chip integration packaging structure is provided, which comprises: a heat sink slide located on the bottom surface of the package;

the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;

the first packaging adhesive layer is formed on the heat dissipation carrier to seal the gallium nitride HEMT chip, the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and the first packaging adhesive layer is provided with a first through hole to expose the first source pad, the first gate pad and the first drain pad;

a fan-out wiring layer formed on the first encapsulation glue layer, the fan-out wiring layer including: a first source inner island communicated with the first source pad through a through hole, a gate line communicated with the first gate pad through the through hole, and a drain line communicated with the first drain pad through the through hole, wherein the first source inner island is formed in a block deviated from the gallium nitride HEMT chip, one end of the drain line is fanned out and extended to be far away from the gallium nitride HEMT chip, and the gate line is positioned between the first source inner island and the drain line;

the MOSFET chip is arranged on the first source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;

a second packaging adhesive layer formed on the first packaging adhesive layer and the fan-out circuit layer, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and the second packaging adhesive layer is provided with a second through hole to expose the second source pad and the second gate pad;

a metal island layer formed on the second encapsulation glue layer, the metal island layer comprising: the through hole is communicated with and interconnects the second source electrode pad and the second source electrode inner island of the gate electrode circuit, and the through hole is communicated with the gate electrode inner island of the second gate electrode pad;

the radiating carrier is divided into a source outer island, a gate outer island and a drain outer island, wherein the source outer island is arranged at the periphery of the radiating main island and is communicated with the second source inner island, the gate outer island is communicated with the gate inner island, and the drain outer island is communicated with the fan-out end of the drain circuit;

with the opening or closing of the MOSFET chip in the positive and negative voltage working range (the negative voltage working range includes 0V), the potential of the first source pad of the gallium nitride HEMT chip can be synchronously adjusted down or up so as to synchronously open or close the gallium nitride HEMT chip.

By adopting the technical scheme, the second source electrode pad of the MOSFET chip is short-circuited to the first gate electrode pad of the gallium nitride HEMT chip by utilizing the second source electrode inner island to be used as the source electrode connection of the whole packaging structure, the second gate electrode pad of the MOSFET chip can be used as the gate electrode connection of the whole packaging structure, the gate electrode can be turned off to the opening working voltage and can be increased to the negative voltage switching-off including 0V and the positive voltage opening not including 0V, and the gate electrode voltage on the packaging surface is grounded or 0V potential and still keeps in a power-saving constant-off state. The gallium nitride HEMT chip and the MOSFET chip are efficiently integrated under a FOPLP (Fan-Out Panel Level Package) packaging framework, the MOSFET chip is arranged on the first source electrode inner island on the first packaging adhesive layer, so that the drain layer on the back surface of the MOSFET chip is electrically connected with the first source electrode pad of the gallium nitride HEMT chip, the MOSFET chip is relatively deviated from the gallium nitride HEMT chip, the gallium nitride HEMT chip is arranged on the heat dissipation carrier, the gallium nitride HEMT chip has higher external heat conductivity than the MOSFET chip, the gallium nitride HEMT chip and the MOSFET chip are not directly thermally coupled, and a faster external heat dissipation conduction path which is better than the MOSFET chip is provided for high-temperature energy of the gallium nitride HEMT chip.

The invention may in a preferred example be further configured to: the off working voltage of the first drain electrode pad of the gallium nitride HEMT chip is between 100 and 600V through the outer drain electrode island, the first grid electrode pad of the gallium nitride HEMT chip is in short circuit with the second source electrode pad of the MOSFET chip through the inner second source electrode island, the off and on working voltages of the first grid electrode pad of the gallium nitride HEMT chip are both smaller than 0V, and when the source and drain of the MOSFET chip are closed under negative voltage (including 0V), the voltage of the first source electrode pad of the gallium nitride HEMT chip is passively raised through the outer grid electrode island, and the voltage of the first grid electrode pad of the gallium nitride HEMT chip is still not enough to turn on the gallium nitride HEMT chip when the voltage of the source and the drain of the MOSFET chip is closed under the negative voltage (including 0V).

By adopting the preferable technical characteristics, the second gate electrode pad of the MOSFET chip is connected as the gate electrode of the whole packaging structure by utilizing the gate electrode outer island, the second source electrode pad of the MOSFET chip is short-circuited to the first gate electrode pad of the gallium nitride HEMT chip by utilizing the second source electrode inner island in a matching way, and the second gate electrode pad is also connected as the source electrode of the whole packaging structure, so that the gate electrode working voltage of the gallium nitride HEMT chip integrated packaging structure is changed, the interference of parasitic inductance is avoided, and the gallium nitride HEMT chip integrated packaging structure can be turned off at the ground or 0 potential. The source drain gate electrode arrangement from the gallium nitride HEMT chip to the bottom surface of the package is changed, the turn-off working voltage of the first drain electrode pad of the gallium nitride HEMT chip can be operated at a high voltage of 100-600V, namely the turn-off and turn-on working voltages of the first gate electrode pad of the gallium nitride HEMT chip are both less than 0V, and the gallium nitride HEMT chip belongs to a high-power semiconductor device. When the MOSFET chip is closed at a source and a drain, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, the voltage of the first gate pad of the gallium nitride HEMT chip is not larger than or equal to 0V, so that the gallium nitride HEMT chip is switched on and off synchronously by the MOSFET chip.

The invention may in a preferred example be further configured to: the turn-off working voltage of the gate outer island is less than or equal to 0V, the turn-on working voltage of the gate outer island is 3-20V, and a Schottky diode is arranged in the MOSFET chip in a reverse direction.

By adopting the preferable technical characteristics, the turn-off working voltage of the gate outer island is less than or equal to 0V, the source-drain connection of the MOSFET chip is still turned off under the ground or 0V, the gallium nitride HEMT chip is also synchronously turned off, when the power switch is switched and used, the voltage of the second source inner island is stabilized at a negative voltage, the voltage change of the drain outer island does not influence the voltage relatively far away from the gate outer island, and the turn-on working voltage of the gate outer island can be in a relatively stable value with small fluctuation between 3 and 20V. And a Schottky diode is reversely arranged in the MOSFET chip and is used for eliminating the parasitic capacitance of the MOSFET chip which takes silicon as a base material.

The invention may in a preferred example be further configured to: the first source inner island is relatively deviated from the gallium nitride HEMT chip and has a larger size than the first source pad, and the size of the first source inner island is larger than and has a contour corresponding to the back surface of the MOSFET chip, so that the drain layer is substantially combined with the first source inner island.

By adopting the preferable technical characteristics, the integrated packaging structure utilizes the first source electrode inner island on the first packaging adhesive layer to be relatively deviated from the gallium nitride HEMT chip and the size of the first source electrode inner island is larger than that of the first source electrode pad, so that the MOSFET chip does not need to be directly placed on the first source electrode pad of the gallium nitride HEMT chip, the size of the MOSFET chip can be larger than that of the first source electrode pad of the gallium nitride HEMT chip, the size of the MOSFET chip is not limited, and the on-resistance of a wire bonding lead in the packaging does not rise, so that the current performance of the MOSFET chip can be maintained.

The invention may in a preferred example be further configured to: the second source electrode inner island is relatively deviated and larger than the first source electrode inner island in size, the through hole of the first packaging adhesive layer and the through hole of the second packaging adhesive layer which are electrically connected with the second source electrode inner island correspond to each other in a straight-through mode so as to shorten a conduction path to be less than 100um, and the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure is less than 0.2 milliohm.

By adopting the preferable technical characteristics, the second source inner island is relatively deviated and has a size larger than that of the first source inner island, the through hole of the first packaging adhesive layer electrically connected with the second source inner island on the first gate electrode pad of the gallium nitride HEMT chip is in through correspondence with the through hole of the second packaging adhesive layer so as to shorten the conduction path to be less than 100um, the packaging inner resistance of the integrated packaging structure of the gallium nitride HEMT chip can also reach below 0.2 milliohm, therefore, the transmission path of the first gate electrode pad and the first source electrode pad on the gallium nitride HEMT chip is short, the configuration relationship of the chip and the packaging structure between the gate electrode and the source electrode is interchanged, and the state that the source electrode of the chip is relatively far away from the drain electrode is changed into the state that the gate electrode of the packaging structure is relatively far away from the drain electrode.

The main purpose of the invention can also be realized by another technical scheme as follows:

a gallium nitride HEMT chip integration packaging structure is provided, which comprises: the heat dissipation chip comprises a heat dissipation slide glass capable of establishing an external heat dissipation path, a gallium nitride HEMT chip arranged on the heat dissipation slide glass, an MOSFET chip sealed in a FOPLP (Fan-Out planar Level Packaging) Packaging adhesive layer and a FOPLP line structure, wherein the FOPLP line structure comprises a first source electrode inner island and a second source electrode inner island, the first source electrode inner island is positioned in the FOPLP Packaging adhesive layer and is connected with a source electrode of the gallium nitride HEMT chip and a drain electrode of the MOSFET chip in an interlayer mode, the second source electrode inner island is positioned on one surface of the FOPLP Packaging adhesive layer and is short-circuited with a grid electrode of the gallium nitride HEMT chip and a source electrode of the MOSFET slide glass chip in a long and short through hole mode, and the heat dissipation cutting comprises: the source outer island is conducted to the second source inner island, the gate outer island is conducted to the gate inner island, and the drain outer island is conducted to the fan-out end of the drain circuit of the FOPLP circuit structure.

By adopting the technical scheme, the source electrode of the gallium nitride HEMT chip and the drain electrode of the MOSFET chip are connected in a sandwich mode by utilizing the first source electrode inner island in the FOPLP packaging adhesive layer, and the gate electrode of the gallium nitride HEMT chip and the source electrode of the MOSFET chip are in short circuit by utilizing the second source electrode inner island on the packaging top surface in a mode of penetrating through the FOPLP packaging adhesive layer by the long and short through holes, so that the integrated packaging of the heterogeneous chip with the circuit structure with the gate electrode taking the gallium nitride HEMT chip as a closing effect under the condition of grounding or 0V voltage is realized, the parasitic inductance is greatly reduced, and the heat dissipation of the gallium nitride HEMT chip is improved.

The invention may in a preferred example be further configured to: the heat dissipation slide glass also comprises a heat dissipation main island, the back surface of the gallium nitride HEMT chip is thermally coupled and connected to the heat dissipation main island, the gate inner island is positioned on the same surface of the FOPLP packaging adhesive layer as the second source inner island, the gate inner island is originally connected with the gate of the MOSFET chip, and the drain outer island is originally connected with the drain of the gallium nitride HEMT chip.

By adopting the preferable technical characteristics, the drain electrode of the gallium nitride HEMT chip is originally connected with the drain electrode of the gallium nitride HEMT chip by the outer drain electrode island, the gate electrode of the MOSFET chip is originally connected with the inner gate electrode of the FOPLP packaging adhesive layer by the inner gate electrode island, other active devices are not connected between the outer drain electrode island and the drain electrode of the gallium nitride HEMT chip, other active devices are not connected between the inner gate electrode island and the gate electrode of the MOSFET chip, the external lead-in path of the chip inside the package is shortened, the complicated and long routing length is not needed, and the gate electrode function of the MOSFET chip is used as the gate electrode function of the whole gallium nitride HEMT chip integrated packaging structure.

The main purpose of the invention is realized by the following technical scheme:

a method for manufacturing a gallium nitride HEMT chip integrated package structure is provided, which is used for manufacturing the gallium nitride HEMT chip integrated package structure which can be combined by any technical scheme, and the manufacturing method comprises the following steps:

providing a heat dissipation slide;

arranging a gallium nitride HEMT chip on the heat dissipation carrier, so that the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;

forming a first packaging adhesive layer on the heat dissipation chip in a flat plate molding manner so as to seal the gallium nitride HEMT chip, wherein the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and the first packaging adhesive layer is provided with a first through hole so as to expose the first source pad, the first gate pad and the first drain pad;

forming a fan-out wiring layer on the first encapsulation glue layer, the fan-out wiring layer comprising: a first source inner island communicated with the first source pad through a through hole, a gate line communicated with the first gate pad through the through hole, and a drain line communicated with the first drain pad through the through hole, wherein the first source inner island is formed in a block deviated from the gallium nitride HEMT chip, one end of the drain line is fanned out and extended to be far away from the gallium nitride HEMT chip, and the gate line is positioned between the first source inner island and the drain line;

arranging an MOSFET chip on the first source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;

forming a second packaging adhesive layer on the first packaging adhesive layer and the fan-out circuit layer in a flat plate molding manner, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and a second through hole is formed in the second packaging adhesive layer so as to expose the second source pad and the second gate pad;

forming a metal island layer on the second encapsulation glue layer, wherein the metal island layer comprises: the through hole is communicated with and interconnects the second source electrode pad and the second source electrode inner island of the gate electrode circuit, and the through hole is communicated with the gate electrode inner island of the second gate electrode pad;

the heat dissipation carrier is divided into a source outer island, a gate outer island and a drain outer island, wherein the source outer island is arranged at the periphery of the heat dissipation main island and is communicated with the second source inner island, the gate outer island is communicated with the gate inner island, and the drain outer island is communicated with the fan-out end of the drain circuit.

By adopting the technical scheme, FOPLP layer by layer packaging is utilized, a main heat dissipation path of the gallium nitride HEMT chip is firstly established, the first layer of packaging is carried out, then an electric path for interconnecting the MOSFET chip and the second layer of packaging are established, the fan-out circuit layer is arranged on the first packaging adhesive layer, the fan-out circuit layer comprises a first source electrode inner island which is communicated with the first source electrode pad through a through hole, the first source electrode inner island is formed in a block deviating from the gallium nitride HEMT chip, and when the MOSFET chip is arranged, the back drain electrode layer of the MOSFET chip can be electrically connected with the first source electrode pad of the gallium nitride HEMT chip. The metal island layer comprises a second source inner island which is communicated and interconnected with the second source pad and the gate electrode circuit through a through hole, the voltage difference of a source electrode and a drain electrode of the gallium nitride HEMT chip is changed through the operation of a second gate electrode switch of the MOSFET chip, and then the source electrode and the drain electrode of the gallium nitride HEMT chip are synchronously opened and synchronously closed, the gallium nitride HEMT chip and the MOSFET chip do not need to be connected through an external circuit, and the heat dissipation type heterogeneous chip has the effect of microminiaturization packaging and integration.

The invention may in a preferred example be further configured to:

in the step of arranging the gallium nitride HEMT chip, the first gate pad is configured between the first source pad and the first drain pad;

or/and in the step of forming the first packaging adhesive layer in a flat plate molding manner, the first packaging adhesive layer also covers the peripheral side edges of the heat dissipation slide glass;

or/and in the step of forming the fan-out line layer, the first source inner island is relatively deviated from the gallium nitride HEMT chip and has a larger size than the first source pad, and the size of the first source inner island is larger than the size of the first source inner island and the outline of the first source inner island corresponds to the back surface of the MOSFET chip;

or/and, in the step of disposing the MOSFET chip on the first source inner island, the drain layer is fully and substantially bonded to the first source inner island;

or/and, in the step of forming the metal island layer, the second source electrode inner island is relatively deviated and has a size larger than that of the first source electrode inner island, and the through hole of the first packaging adhesive layer electrically connected with the second source electrode inner island corresponds to the through hole of the second packaging adhesive layer in a straight-through manner, so as to shorten a conduction path to be less than 100um, and further enable the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure to be controlled to be less than 0.2 milliohm;

or/and the manufacturing method further comprises a step of packaging and separating to obtain a separated gallium nitride HEMT chip integrated packaging structure, wherein the off working voltage of the first drain pad of the gallium nitride HEMT chip is between 100 and 600V through the outer drain island, the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip are in short circuit through the inner second source island, the off and on working voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0V, when the source and drain of the MOSFET chip are closed, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised through the outer gate island, the voltage of the first gate pad of the gallium nitride HEMT chip is not more than 0V, preferably, the off working voltage of the outer gate island is less than 0V, the opening working voltage of the gate outer island is 3-20V, and a Schottky diode is arranged in the MOSFET chip in a reverse direction.

The technical result corresponding to the characteristics of the device described above can be achieved by using the above-mentioned preferred technical features, with the corresponding structural features or possible combinations of structural features described above.

The main purpose of the invention is realized by the following technical scheme:

an electronic device is proposed, comprising: the integrated packaging structure comprises a printed circuit board and a gallium nitride HEMT chip which is jointed on the printed circuit board and can be combined with the printed circuit board according to any technical scheme, wherein in the packaging bottom surface of the integrated packaging structure of the gallium nitride HEMT chip, a source outer island, a gate outer island and a drain outer island which are positioned on the same surface are respectively welded to corresponding pins of the printed circuit board, the back surface of the MOSFET chip is not directly thermally coupled with the gallium nitride HEMT chip under the blockage of a packaging adhesive layer, and a horizontal electric connection path between the drain electrode of the MOSFET chip and the source electrode of the gallium nitride HEMT chip does not exceed the projection area of the MOSFET chip on the packaging bottom surface.

By adopting the technical scheme, the electronic device can more quickly transfer the heat of the gallium nitride HEMT chip, and the heat dissipation slide is only directly thermally coupled with the gallium nitride HEMT chip, so that the MOSFET chip receives less heat from the gallium nitride HEMT chip.

In summary, the technical solution of the present invention includes at least one of the following technical effects that contribute to the prior art:

1. the first source electrode pad of the gallium nitride HEMT chip is connected with the drain electrode layer of the MOSFET chip through a first source electrode inner island on a first through hole of a first packaging adhesive layer, a second source electrode pad of the MOSFET chip is led out to a second source electrode inner island on the packaging surface through a second through hole of a second packaging adhesive layer, the connection length of each layer of through holes can be smaller than or equal to 50um (the first molding height of the first packaging adhesive layer is less than or equal to 50um, and the second molding height of the second packaging adhesive layer is less than or equal to 50um), and the traditional routing connection length is 1000-2000 um, compared with a routing mode, the interconnection length of the chips in the packaging is greatly reduced, and the parasitic inductance is one order of magnitude smaller than that of the traditional packaging;

2. because the second source electrode pad of the MOSFET chip is connected with the second source electrode inner island on the top surface of the package through the second through hole of the second package adhesive layer, the metal island layer comprising the second source electrode inner island can increase the heat dissipation of the top surface of the package, and a heat dissipation slide is welded with an external Printed Circuit Board (PCB), so that the paths of electric conduction and heat conduction are very short, and when the external connection length of the second source electrode pad of the MOSFET chip passing through the second source electrode inner island is below 100 mu m, the electric conduction and heat conduction effects of the gallium nitride HEMT chip integrated package structure can be optimized;

3. the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure can be reduced to below 0.2 milliohm, and the packaging internal resistance of the existing GaN HEMT packaging structure is above 1 milliohm;

4. the size area of the MOSFET chip is not limited by the area size of the first source electrode pad of the gallium nitride HEMT chip any more, and the MOSFET chip can be larger than the first source electrode pad of the gallium nitride HEMT chip, and the MOSFET chip with better conduction performance can be integrated in a packaging structure, so that the internal resistance of a device of the gallium nitride HEMT chip integrated packaging structure is further reduced;

5. the back of the gallium nitride HEMT chip of the invention example forms the thermal coupling with the heat-dissipating slide through the adhesive bonding, the heat resistance of the outer casing of the encapsulated junction is smaller, the heat that the gallium nitride HEMT chip produces is conducted the heat to the external printed circuit board at the bottom surface of the encapsulation directly through the heat-dissipating main island of the heat-dissipating slide, can also carry on the heat dissipation at the top surface of the encapsulation through the second source inner island, the double-sided heat dispersion is better;

6. the heat dissipation slide can be removed or kept in a product, if higher heat dissipation requirements exist, a heat radiator can be arranged on the top surface of the package, so that the top surface of the package is provided with heat conduction metal, a leveled third package adhesive layer is utilized to provide a horizontal installation reference, and the installation of the external radiator is more convenient;

7. before the third packaging adhesive layer is covered or in a product without the need of forming the third packaging adhesive layer, the second power Source inner island and the Gate inner island can be exposed out of the package top surface, and in some occasions of on-line testing after the device flitch is used, a test probe can be used for directly contacting a Source (Source) and a Gate (Gate) of the package top surface to carry out testing without additional wiring.

Drawings

FIG. 1 is a cross-sectional view of a gallium nitride HEMT chip integrated package structure according to some preferred embodiments of the present invention;

fig. 2 is a top view (a) and a bottom view (B) of a gallium nitride HEMT chip integrated package structure in a see-through surface glue layer according to some preferred embodiments of the present invention;

FIG. 3 is a circuit diagram of an integrated package structure of a GaN HEMT chip according to some embodiments of the present invention;

fig. 4 is a schematic view of a gallium nitride HEMT chip integrated package method of the present invention, with the gallium nitride HEMT chip disposed on a heat sink slide;

fig. 5 is a schematic view illustrating a first packaging adhesive layer formed on a heat sink chip by a flat mold sealing method in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;

fig. 6 is a schematic view illustrating a first through hole is formed in a first packaging adhesive layer in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

fig. 7 is a schematic view showing a first deposited metal layer forming a fan-out wiring layer formed on a first packaging adhesive layer in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;

FIG. 8 is a schematic diagram illustrating the fan-out wiring layer formed in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

fig. 9 is a schematic cross-sectional view of a MOSFET chip disposed on a first source inner island in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;

fig. 10 is a schematic view illustrating a second packaging adhesive layer formed on a first packaging adhesive layer by a flat mold method in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;

fig. 11 is a schematic view illustrating a second through hole is formed in a second packaging adhesive layer in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

fig. 12 is a schematic view showing a second deposited metal layer forming a metal island layer formed on a second packaging adhesive layer in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

fig. 13 is a schematic view illustrating a second deposited metal layer is etched to form a metal island layer in the method for integrally packaging a gallium nitride HEMT chip according to some preferred embodiments of the present invention;

fig. 14 is a cross-sectional view of a gallium nitride HEMT chip integrated package structure in accordance with still other embodiments of the present invention.

The reference numeral 10 denotes a heat dissipation carrier, 10A denotes a heat dissipation main island, 11 denotes a source outer island, 12 denotes a gate outer island, 13 denotes a drain outer island, 20 denotes a gallium nitride HEMT chip, 21 denotes a first source pad, 22 denotes a first gate pad, 23 denotes a first drain pad, 30 denotes a first encapsulant layer, 31 denotes a first via hole, 40 denotes a fan-out line layer, 40A denotes a first deposited metal layer, 41 denotes a first source inner island, 42 denotes a gate line, 43 denotes a drain line, 50 denotes a MOSFET chip, 51 denotes a second source pad, 52 denotes a second gate pad, 53 denotes a drain layer, 54 denotes a Schottky diode, 60 denotes a second encapsulant layer, 61 denotes a second via hole, 62 denotes a third via hole, 70 denotes a metal island layer, 70A denotes a second deposited metal layer, 71 denotes a second source inner island, 72 denotes a gate inner island, 80 denotes a third encapsulant layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of embodiments for understanding the inventive concept of the present invention, and do not represent all embodiments, nor do they explain only embodiments. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention under the understanding of the inventive concept of the present invention are within the protection scope of the present invention.

It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture, and if the specific posture is changed, the directional indications are changed accordingly. In order to facilitate understanding of the technical solution of the present invention, the gallium nitride HEMT chip integrated package structure of the present invention and the method for manufacturing the same are described and explained in further detail below, but the present invention is not limited to the scope of protection.

The term "heat dissipation carrier" as used herein refers to a heat dissipation exposed area of a heat dissipation object corresponding to the surface of a package, which is 60% or more, specifically 80% or more (as shown in fig. 1), and usually does not exceed 100% of the area of the bottom surface of the package.

The term "offset" as used herein means that the top and bottom surfaces of the package projected toward the bottom surface of the package are not aligned with each other at a central point. The term "fan-out" as used herein refers to the extension of an object to fan-out in a direction away from the center of the gallium nitride HEMT chip. The "island" described in the specification is a metal pad layer having an electrical function of the "pad" but having a larger area than the pad, and the shape of the island may be more irregular than the pad, and the island is usually not provided on the surface of the chip. The term "native connection" as used herein refers to an electrical connection path between two electrically connected components in a package without adding any active device, and specifically, the electrical connection path is simply formed by a circuit formed in a wafer level package, and does not include a wire bonding connection nor other devices disposed therebetween.

The accompanying drawings illustrate various embodiments having a common component, and the various embodiments having differences or differences will be described with particularity. Therefore, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features or any combination of a plurality of the technical features described below can be characterized in the same embodiment or whether a plurality of technical features mutually exclusive can be respectively characterized in different variant embodiments.

Fig. 1 is a cross-sectional view of a gallium nitride HEMT chip integrated package structure according to some preferred embodiments of the present invention, fig. 2 is a top view (a) and a bottom view (B) of a package of a transparent surface package adhesive layer of the gallium nitride HEMT chip integrated package structure, fig. 3 is a circuit diagram of the gallium nitride HEMT chip integrated package structure, and fig. 4 to 13 are schematic component section views of the gallium nitride HEMT chip integrated package structure in a packaging process. In the figure, "S" is a Source (Source), "G" is a Gate (Gate), "D" is a Drain (Drain), and in the example, the Source is a carrier start point and the Drain is a carrier end point.

Referring to fig. 1, fig. 2 and fig. 3, in some preferred embodiments of the present invention, an integrated package structure of a gan HEMT chip is provided, including: the chip package comprises a heat dissipation chip 10, a gallium nitride HEMT chip 20, a first package glue layer 30, a fan-out line layer 40, a MOSFET chip 50, a second package glue layer 60 and a metal island layer 70, wherein the heat dissipation chip 10, the gallium nitride HEMT chip 20, the first package glue layer, the fan-out line layer, the MOSFET chip 50, the second package glue layer 60 and the metal island layer are located on the bottom surface of the package. One of the important effects of the invention is that the on-state working voltage for driving the gallium nitride HEMT chip 20 is increased to a positive voltage not containing 0V, the grounding or reference potential of 0V is off (one specific application is 0V off and 5V on), the parasitic inductance is greatly reduced in the packaging structure, and the technical effect of realizing the source and drain off of the gallium nitride HEMT chip 20 without applying a negative voltage is stably achieved.

Referring to fig. 1, a gallium nitride HEMT chip 20 is disposed on a heat sink chip 10 such that the back surface of the gallium nitride HEMT chip 20 is thermally coupled to the heat sink chip 10, and the front surface of the gallium nitride HEMT chip 20 is provided with a first source pad 21, a first gate pad 22 and a first drain pad 23. The semiconductor substrate of the gallium nitride HEMT chip 20 is gallium nitride, and in this example the first gate pad 22 can be located between the first source pad 21 and the first drain pad 23. The heat dissipation carrier 10 is made of a high thermal conductivity metal such as copper.

The first encapsulant layer 30 is formed on the heat dissipation chip 10 to seal the gallium nitride HEMT chip 20, the first encapsulant layer 30 has a first molding height, in an example ≦ 50um, on the gallium nitride HEMT chip 20, the first encapsulant layer 30 is formed with a first through hole 31 to expose the first source pad 21, the first gate pad 22, and the first drain pad 23, and specifically, a plurality of first through holes 31 may be formed on one first source pad 21 or one first drain pad 23. In an example, the outer surface of the heat sink chip 10 may be slightly smaller than the bottom surface of the package (the bottom surface of the package is the inward surface of the package product bonded to the pcb, and the bottom surface of the package in fig. 1 is downward and includes the exposed surface of the heat sink chip 10, as shown in fig. 2 (B)), and the top surface of the package in fig. 1 is upward, and the first adhesive layer 30 may cover the peripheral sides of the heat sink chip 10, so as to more stably hold the heat sink chip 10.

A fan-out wiring layer 40 is formed on the first encapsulation glue layer 30, the fan-out wiring layer 40 including: a first source inner island 41 connected to the first source pad 21 by a via, a gate line 42 connected to the first gate pad 22 by a via, and a drain line 43 connected to the first drain pad 23 by a via, wherein the first source inner island 41 is formed in a section offset from the gallium nitride HEMT chip 20, one end of the drain line 43 is extended by fanout to be away from the gallium nitride HEMT chip 20, and the gate line 42 is located between the first source inner island 41 and the drain line 43. The fan-out wiring layer 40 is typically a wiring formed during wafer level packaging, and the first source inner island 41 may be equal to or slightly larger than the MOSFET chip 50. The first source inner island 41, the gate line 42 and the drain line 43 of the fan-out line layer 40 can be integrally filled in the first via hole 31 under the corresponding cover region of the first encapsulant layer 30 to electrically connect the corresponding first source pad 21, first gate pad 22 and first drain pad 23, respectively.

The MOSFET chip 50 is disposed on the first source inner island 41, so that the back drain layer 53 of the MOSFET chip 50 is electrically connected to the first source pad 21, and the front surface of the MOSFET chip 50 is provided with a second source pad 51 and a second gate pad 52. The semiconductor substrate of the MOSFET die 50 can be silicon or other non-gallium nitride silicon based semiconductor, such as silicon carbide, with the back drain layer 53 illustratively being located on a different die back surface than the die front surface of the second source pad 51 and the second gate pad 52. The back drain layer 53 may completely cover the back side of the MOSFET chip 50. The first in-source island 41 may be sized slightly larger than the backside of the MOSFET chip 50.

The second encapsulant layer 60 is formed on the first encapsulant layer 30 and the fan-out line layer 40, the second encapsulant layer 60 has a second encapsulant height, in an example ≦ 50um, on the MOSFET chip 50, the second encapsulant layer 60 is formed with a second through hole 61 to expose the second source pad 51 and the second gate pad 52. The first encapsulant layer 30 and the second encapsulant layer 60 are electrically insulating materials with low expansion coefficients, and may be the same material or different materials with expansion coefficients within a suitable adjustment range.

A metal island layer 70 is formed on the second encapsulation glue layer 60, the metal island layer 70 including: a via conductively interconnects the second source pad 51 with the second source inner island 71 of the gate line 42 and a via to the gate inner island 72 of the second gate pad 52. One specific arrangement of the second source inner island 71 and the gate inner island 72 can be seen in FIG. 2 (A).

The heat dissipation carrier 10 is divided into a source outer island 11 (as shown in fig. 2) at the periphery of the heat dissipation main island 10A and connected to the second source inner island 71, a gate outer island 12 connected to the gate inner island 72, and a drain outer island 13 connected to the fan-out end of the drain line 43, where a specific arrangement of the source outer island 11, the gate outer island 12, and the drain outer island 13 can be seen in fig. 2 (B). The third through hole 62 may penetrate through the second encapsulant layer 60 and the first encapsulant layer 30, so that the second source inner island 71 can be electrically connected to the source outer island 11 in the vertical direction.

One circuit structure of the gallium nitride HEMT chip integrated package structure can be seen in fig. 3. With the MOSFET chip 50 turned on or off in the positive and negative voltage operating ranges (the negative voltage operating range includes 0V), the potential of the first source pad 21 of the gallium nitride HEMT chip 20 can also be synchronously turned down or up to synchronously turn on or off the gallium nitride HEMT chip 20.

The basic principle of the embodiment is as follows: the second source pad 51 of the MOSFET chip 50 is shorted to the first gate pad 22 of the gan HEMT chip 20 by the second source inner island 71 to serve as the source connection of the whole package structure, and no wire bonding is needed, the second gate pad 52 of the MOSFET chip 50 can serve as the gate connection of the whole package structure through the gate outer island 12, so that the turn-off of the gate to the turn-on operating voltage can be increased to include 0V negative voltage turn-off and 0V positive voltage turn-on (in the prior art, the gan HEMT product is operated to include 0V negative voltage turn-on and turn-off and 0V turn-on), and when the gate voltage at the bottom surface of the package is ground or 0V potential, the power saving state is still maintained. In a practical application, the package structure can be turned off by 0V and turned on by 5V of the surface gate of the GaN HEMT chip 20. Under a FOPLP (Fan-Out Panel Level Package) packaging framework, the gallium nitride HEMT chip 20 and the MOSFET chip 50 are efficiently integrated, and the MOSFET chip 50 is arranged on the first source inner island 41 on the first packaging adhesive layer 30, so that the back drain layer 53 of the MOSFET chip 50 is electrically connected with the first source pad 21 of the gallium nitride HEMT chip 20, parasitic inductance can be reduced, and the size of the back drain layer 53 does not need to be matched to a degree smaller than that of the first source pad 21 of the gallium nitride HEMT chip 20; the MOSFET chip 50 is relatively deviated from the gallium nitride HEMT chip 20, the gallium nitride HEMT chip 20 is arranged on the heat dissipation slide 10, the gallium nitride HEMT chip 20 has higher external heat conductivity than the MOSFET chip 50, and the gallium nitride HEMT chip 20 is not directly thermally coupled with the MOSFET chip 50, providing a faster conduction path for dissipating heat to the outside for the high temperature energy of the gallium nitride HEMT chip 20 than through the MOSFET chip 50.

In a preferred example, the off-state operating voltage of the first drain pad 23 of the gallium nitride HEMT chip 20 is between 100-600V through the outer drain island 13, the first gate pad 22 of the gallium nitride HEMT chip 20 and the second source pad 51 of the MOSFET chip 50 are shorted through the second inner source island 71, the off-state and on-state operating voltages of the first gate pad 22 of the gallium nitride HEMT chip 20 are both less than 0V, when the first gate pad 22 is 0V, the source and drain of the gallium nitride HEMT chip 20 are turned on, and when the source and drain of the MOSFET chip 50 is turned off at less than or equal to 0V through the outer gate island 12, the voltage of the first source pad 21 of the gallium nitride HEMT chip 20 is passively raised, and the voltage ≦ 0V of the first gate pad 22 of the gallium nitride chip 20 is still not enough to turn on the gallium nitride chip 20.

Therefore, the second gate pad 52 of the MOSFET chip 50 is used as the gate connection of the whole package structure by using the outer gate island 12, and the second source pad 51 of the MOSFET chip 50 is shorted to the first gate pad 22 of the gallium nitride HEMT chip 20 by using the inner second source island 71, and is also used as the source connection of the whole package structure, so that the gate working voltage of the integrated package structure of the gallium nitride HEMT chip is changed, the interference of parasitic inductance is avoided, and the integrated package structure of the gallium nitride HEMT chip can be turned off at ground or 0 potential. The arrangement of the source and drain electrodes from the gallium nitride HEMT chip 20 to the bottom surface of the package is changed, the turn-off working voltage of the first drain electrode pad 23 of the gallium nitride HEMT chip 20 can be operated at a high voltage of 100-600V, even if the turn-off and turn-on working voltages of the first drain electrode pad 22 of the gallium nitride HEMT chip 20 are both less than 0V, when the MOSFET chip 50 is turned off at the source and drain electrodes, the voltage of the first source electrode pad 21 of the gallium nitride HEMT chip 20 is passively raised, the voltage ≦ 0V of the first gate electrode pad 22 of the gallium nitride HEMT chip 20 is not enough to turn on the gallium nitride HEMT chip 20, and the switching operation of the MOSFET chip 50 to the synchronous turn-on and synchronous turn-off of the gallium nitride HEMT chip 20 is realized.

The invention may in a preferred example be further configured to: the turn-off working voltage of the gate outer island 12 is ≦ 0V, the turn-on working voltage of the gate outer island 12 is 3-20V, and a Schottky diode 54 is reversely arranged in the MOSFET chip 50. When the power switch is switched and used, the voltage of the second source inner island 71 is stabilized at a negative voltage, the voltage change of the drain outer island 13 does not influence the voltage relatively far away from the gate outer island 12 (as shown in fig. 2 (B)), and the turn-on working voltage of the gate outer island 12 can be a relatively stable value with small fluctuation between 3 and 20V. A schottky diode 54 (shown in fig. 3) is disposed in the reverse direction in the MOSFET die 50 for eliminating the parasitic capacitance of the MOSFET die 50 based on silicon.

In a preferred example, the first source inner island 41 is relatively offset from the gallium nitride HEMT chip 20 and is larger in size than the first source pad 21, and the first source inner island 41 is also larger in size and contoured to correspond to the backside of the MOSFET chip 50 so that the drain layer 53 is substantially bonded to the first source inner island 41. The first source inner island 41 on the first packaging adhesive layer 30 is relatively deviated from the gallium nitride HEMT chip 20 in the integrated packaging structure and has a larger size than the first source pad 21, so that the MOSFET chip 50 does not need to be directly placed on the first source pad 21 of the gallium nitride HEMT chip 20, the MOSFET chip 50 can be larger than the first source pad 21 of the gallium nitride HEMT chip 20 in size, the size of the MOSFET chip 50 is not limited, and the on-resistance of the wire bonding wires in the packaging does not rise, so that the current performance of the MOSFET chip 50 is maintained.

In a preferred example, the second source inner island 71 is relatively deviated and has a larger size than the first source inner island 41, and the through hole of the first packaging adhesive layer 30 electrically connected with the second source inner island 71 corresponds to the through hole of the second packaging adhesive layer 60 in a through manner so as to shorten the conduction path to be less than 100um, and the package internal resistance of the gallium nitride HEMT chip integrated package structure is less than 0.2 milliohm. The second source inner island 71 is deviated relatively and has a size larger than that of the first source inner island 41, the through hole of the first packaging adhesive layer 30 electrically connected with the second source inner island 71 on the first gate pad 22 of the gallium nitride HEMT chip 20 corresponds to the through hole of the second packaging adhesive layer 60 in a through manner so as to shorten the conduction path to be less than 100um, the in-package resistance of the integrated packaging structure of the gallium nitride HEMT chip can also reach less than 0.2 milliohm, therefore, the transmission path of the first gate pad 22 and the first source pad 21 on the gallium nitride HEMT chip 20 is short, the configuration relationship between the gate and the source of the chip and the packaging structure is exchanged, and the form that the source of the chip is far away from the drain is changed into the form that the gate of the package is far away from the drain.

Referring to fig. 4 to 12, the present invention further provides a method for manufacturing a gallium nitride HEMT chip integrated package structure, which is used to manufacture the gallium nitride HEMT chip integrated package structure capable of being combined according to any of the above-mentioned technical solutions, and the method includes the following steps.

Referring to fig. 4, a heat sink chip 10 is provided, wherein the heat sink chip 10 may be designed in a whole chip, a groove pattern, or in a lead frame without leads or a motherboard with pre-cut grooves.

Referring to fig. 4, a gan HEMT chip 20 is disposed on the heat sink chip 10 such that the back surface of the gan HEMT chip 20 is thermally coupled to the heat sink chip 10, and the front surface of the gan HEMT chip 20 is disposed with a first source pad 21, a first gate pad 22 and a first drain pad 23. in the preferred example, in the step of disposing the gan HEMT chip 20, the first gate pad 22 is disposed between the first source pad 21 and the first drain pad 23.

Referring to fig. 5 and 6, a first encapsulant layer 30 is formed on the heat sink chip 10 by flat molding to seal the gan HEMT chip 20, the first encapsulant layer 30 has a first molding height on the gan HEMT chip 20, and the first encapsulant layer 30 is formed with a first through hole 31 to expose the first source pad 21, the first gate pad 22 and the first drain pad 23. In a preferred example, in the step of forming the first encapsulating adhesive layer 30 by flat molding, the first encapsulating adhesive layer 30 further covers the peripheral side of the heat dissipation chip 10. In the step of forming the first through hole 31, the first through hole 31 is formed by laser or patterned etching. In this example, a portion of the first through hole 31 formed at the periphery of the first encapsulant layer 30 exposes the gate outer island 12 and the drain outer island 13 of the heat spreader 10, or a predetermined formation region of the gate outer island and a predetermined formation region of the drain outer island of the heat spreader 10. Referring to fig. 7 and 8, a fan-out circuit layer 40 is formed on the first encapsulant layer 30, where the fan-out circuit layer 40 includes: a first source inner island 41 connected to the first source pad 21 by a via, a gate line 42 connected to the first gate pad 22 by a via, and a drain line 43 connected to the first drain pad 23 by a via, wherein the first source inner island 41 is formed in a section offset from the gallium nitride HEMT chip 20, one end of the drain line 43 is extended by fanout to be away from the gallium nitride HEMT chip 20, and the gate line 42 is located between the first source inner island 41 and the drain line 43. Referring to fig. 7, a precursor layer for forming the fan-out line layer 40 is a first deposited metal layer 40A, the first deposited metal layer 40A includes a metal body layer, such as a metal foil, formed on the first package adhesive layer 30 in advance before the first via hole 31 is opened, and a hole filling metal (not shown) formed by metal deposition after the first via hole 31 is opened, the metal body layer can protect contamination residues forming the first via hole 31 from adhering to the first package adhesive layer 30 and has an additional function of a hard mask, the fan-out line layer 40 is obtained by metal etching the first deposited metal layer 40A, and the first source inner island 41 serves as an island block for adhering the MOSFET chip 50. In a preferred example, in the step of forming the fan-out line layer 40, the first source inner island 41 is relatively offset from the gallium nitride HEMT chip 20 and has a size larger than the first source pad 21, and the first source inner island 41 also has a size larger than and a contour corresponding to the back surface of the MOSFET chip 50. In this example, the drain line 43 can be directly connected to the outer drain island 13 of the heat sink chip 10, or the predetermined formation region of the outer drain island of the heat sink chip 10.

Referring to fig. 9, a MOSFET chip 50 is disposed on the first source inner island 41, such that the back drain layer 53 of the MOSFET chip 50 is electrically connected to the first source pad 21, the front surface of the MOSFET chip 50 is provided with a second source pad 51 and a second gate pad 52, and in the step of disposing the MOSFET chip 50 on the first source inner island 41, in the preferred example, the drain layer 53 is fully and substantially bonded to the first source inner island 41.

Referring to fig. 10 and 11, a second encapsulant layer 60 is formed on the first encapsulant layer 30 and the fan-out circuit layer 40 by flat molding, the second encapsulant layer 60 has a second molding height above the MOSFET chip 50, and the second encapsulant layer 60 is opened with a second via hole 61 to expose the gate line 42, the second source pad 51 and the second gate pad 52. The second packaging adhesive layer 60 is further provided with a third through hole 62, and the third through hole 62 penetrates through the second packaging adhesive layer 60 and the first packaging adhesive layer 30 and is exposed to the source outer island 11 of the heat dissipation slide 10 or a region where the source outer island is to be formed, so that the subsequently formed second source inner island 71 can be longitudinally and electrically conducted to the source outer island 11.

Referring to fig. 12 and 13, a metal island layer 70 is formed on the second encapsulation adhesive layer 60, wherein the metal island layer 70 includes: a via conductively interconnects the second source pad 51 with the second source inner island 71 of the gate line 42 and a via to the gate inner island 72 of the second gate pad 52. The second source inner island 71 can occupy more than 70% of the area of the top surface of the package (as shown in fig. 2 (a)). In this example, the second source inner island 71 is further electrically connected to the source outer island 11 of the heat spreader 10 or the predetermined formation region of the source outer island of the heat spreader 10, and the gate inner island 72 is further electrically connected to the gate outer island 12 of the heat spreader 10 or the predetermined formation region of the gate outer island of the heat spreader 10. In a preferred example, referring to fig. 12, the precursor layer of the metal island layer 70 is formed as a second deposition metal layer 70A, the second deposition metal layer 70A includes a metal body layer, such as a metal foil, formed on the first package adhesive layer 30 in advance before the second via 61 is opened, and a hole filling metal (not shown) formed by metal deposition after the second via 61 is opened, the metal body layer can protect contamination residues forming the second via 61 from adhering to the second package adhesive layer 60, and has an additional function of a hard mask, and the metal island layer 70 is formed by metal etching the second deposition metal layer 70A. In a preferred example, in the step of forming the metal island layer 70, the second source inner island 71 is relatively deviated and has a larger size than the first source inner island 41, and the through hole of the first packaging adhesive layer 30 electrically connected to the second source inner island 71 corresponds to the through hole of the second packaging adhesive layer 60, so as to shorten the conduction path to less than 100um, thereby controlling the in-package resistance of the gallium nitride HEMT chip integrated package structure to less than 0.2 milliohm.

Thereafter, referring to fig. 1, the preferred steps further include: a third encapsulation glue layer 80 is formed on the second encapsulation glue layer 60 to cover the metal island layer 70. The third encapsulating layer 80 is a selective layer, which can be omitted in different embodiments, and the product without the third encapsulating layer 80 has the second source inner island 71 and the gate inner island 72 exposed on the top surface of the package for direct contact of the test probes, so as to perform electrical test on the second probe points of the source and gate on the top surface of the package.

Referring to fig. 1 and fig. 2, the heat dissipation chip 10 is divided into a source outer island 11 at the periphery of the heat dissipation main island 10A and connected to the second source inner island 71, a gate outer island 12 connected to the gate inner island 72, and a drain outer island 13 connected to the fan-out end of the drain line 43. The step of splitting the heat dissipation slide 10 may be performed in the step of providing the heat dissipation slide 10, or may be performed after the step of forming the metal island layer 70 or after the step of forming the third encapsulation adhesive layer 80, or the step of splitting the heat dissipation slide 10 may be split into two steps, the pre-step of splitting the upper half of the heat dissipation slide 10 is performed in the step of providing the heat dissipation slide 10, and the post-step of splitting the lower half of the heat dissipation slide 10 is performed after the step of forming the third encapsulation adhesive layer 80 and before the step of singulating the package. The method of cleaving the heat sink chip 10 may employ one or more of die cutting, sawing and etching prior to molding.

In a preferred example, the manufacturing method further includes a step of packaging a singulated gan HEMT chip integrated package structure to obtain a singulated gan HEMT chip integrated package structure, wherein the off-state operating voltage of the first drain pad 23 of the gan HEMT chip 20 is between 100 to 600V through the outer drain island 13, the first gate pad 22 of the gan HEMT chip 20 is short-circuited with the second source pad 51 of the MOSFET chip 50 through the inner source island 71, the off-state and on-state operating voltages of the first gate pad 22 of the gan HEMT chip 20 are both less than 0V, the voltage of the first source pad 21 of the gan HEMT chip 20 is passively raised when the source and drain of the MOSFET chip 50 are turned off through the outer gate island 12, the voltage of the first gate pad 22 of the gan chip 20 is less than 0V, preferably, the turn-off working voltage of the gate outer island 12 is ≦ 0V, the turn-on working voltage of the gate outer island 12 is 3-20V, and a Schottky diode 54 is reversely arranged in the MOSFET chip 50 (as shown in FIG. 3). The steps described above with respect to fig. 4-12 are specifically a FOPLP packaging process. In an example, the gan HEMT chip integrated package structure after packaging separation may have package sizes corresponding to DFN 4 × 4, DFN 5 × 6, DFN 8 × 8, and the like.

The basic principle of the embodiment is as follows: the FOPLP layer-by-layer packaging is utilized, firstly, a main heat dissipation path of the gallium nitride HEMT chip 20 is established, the first layer packaging is carried out, then, an electric path for interconnecting the MOSFET chip 50 and the second layer packaging are established, the fan-out circuit layer 40 is arranged on the first packaging adhesive layer 30, the fan-out circuit layer 40 comprises a first source inner island 41 which is conducted to the first source pad 21 through a through hole, the first source inner island 41 is formed in a block deviating from the gallium nitride HEMT chip 20, and when the MOSFET chip 50 is arranged, the back drain layer 53 of the MOSFET chip 50 can be electrically connected with the first source pad 21 of the gallium nitride HEMT chip 20. The metal island layer 70 includes a second source inner island 71 which is interconnected with the second source pad 51 and the gate line 42 by a through hole conduction, and the voltage difference between the source and the drain of the gallium nitride HEMT chip 20 is changed by the operation of the second gate switch of the MOSFET chip 50, so as to realize the synchronous opening and synchronous closing of the source and the drain of the gallium nitride HEMT chip 20, without connecting the gallium nitride HEMT chip 20 and the MOSFET chip 50 by an external circuit, and has the effect of heat dissipation type heterogeneous chip microminiaturization packaging integration.

Referring to fig. 14, another embodiment of the present invention further provides an integrated package structure of a gallium nitride HEMT chip, including: the heat dissipation carrier 10 capable of establishing an external heat dissipation path, a gallium nitride HEMT chip 20 arranged on the heat dissipation carrier 10, a MOSFET chip 50 sealed in a FOPLP (Fan-Out planar Level Packaging) Packaging adhesive layer and a FOPLP circuit structure, wherein the FOPLP circuit structure comprises a first source inner island 41 and a second source inner island 71, the first source inner island 41 is positioned in the FOPLP Packaging adhesive layer and connects a source electrode of the gallium nitride HEMT chip 20 and a drain electrode of the MOSFET chip 50 in an interlayer mode, the second source inner island 71 is positioned on one surface of the FOPLP Packaging adhesive layer and short-connects a grid electrode of the gallium nitride HEMT chip 20 and a source electrode of the MOSFET chip 50 in a long and short through hole mode, and the heat dissipation carrier 10 is split to include: a source outer island connected to the second source inner island 71, a gate outer island 12 connected to the gate inner island 72, and a drain outer island 13 connected to the fan-out end of the drain line 43 of the FOPLP line structure.

The basic principle of the embodiment is as follows: the source of the gallium nitride HEMT chip 20 and the drain of the MOSFET chip 50 are connected in an interlayer mode by using a first source inner island 41 in an FOPLP packaging adhesive layer, and a second source inner island 71 on the top surface of the package is in short circuit with the gate of the gallium nitride HEMT chip 20 and the source of the MOSFET chip 50 by using a mode of penetrating through the FOPLP packaging adhesive layer by a long through hole and a short through hole, so that the integrated package of the heterogeneous chip with the circuit structure that the gate is closed under the condition of grounding or 0V of the gate of the gallium nitride HEMT chip 20 is realized, the parasitic inductance is greatly reduced, and the heat dissipation of the gallium nitride HEMT chip 20 is improved.

In a preferred example, the heat dissipation chip 10 further includes a heat dissipation main island 10A, the back surface of the gallium nitride HEMT chip 20 is thermally coupled to the heat dissipation main island 10A, the gate inner island 72 is located on the same surface of the FOPLP encapsulant as the second source inner island 71, the drain outer island is originally connected to the drain of the gallium nitride HEMT chip 20, and the gate inner island 72 is originally connected to the gate of the MOSFET chip 50.

By adopting the preferable technical characteristics, the drain electrode of the gallium nitride HEMT chip 20 and the gate electrode of the MOSFET chip 50 are connected by the outer drain electrode island 133 and the inner gate electrode island 72 on the same surface of the FOPLP packaging adhesive layer, other active devices are not connected between the outer drain electrode island 13 and the drain electrode of the gallium nitride HEMT chip 20, other active devices are not connected between the inner gate electrode island 72 and the gate electrode of the MOSFET chip 50, the external lead-out path of the chip inside the package is shortened, the complicated and long routing length is not needed, and the gate electrode function of the MOSFET chip 50 is used as the gate electrode function of the gallium nitride HEMT chip integrated packaging structure of the gallium nitride HEMT chip.

Other examples of the present invention also provide an electronic apparatus including: a printed circuit board and a gallium nitride HEMT chip integrated package structure (an example structure is shown in FIG. 1 or FIG. 14) which is bonded on the printed circuit board and can be combined according to any technical scheme, in the bottom surface of the integrated package structure of the gallium nitride HEMT chip, the source outer island 11, the gate outer island 12 and the drain outer island 13 which are positioned on the same surface are respectively welded to the corresponding pins of the printed circuit board; the second source inner island 71 with an enlarged area is positioned on or close to the top surface of the package of the gallium nitride HEMT chip integrated package structure and can help heat dissipation (as shown in fig. 2 (a)); the back surface of the MOSFET chip 50 is not directly thermally coupled with the gallium nitride HEMT chip 20 under the obstruction of a packaging adhesive layer; the horizontal electric connection path between the drain of the MOSFET chip 50 and the source of the gallium nitride HEMT chip 20 does not exceed the projection area of the MOSFET chip 50 on the bottom surface of the package. Therefore, the electronic device can more quickly transfer heat out of the gallium nitride HEMT chip 20, and the heat sink 10 is only thermally coupled directly to the gallium nitride HEMT chip 20, so that the MOSFET chip 50 receives less heat from the gallium nitride HEMT chip 20.

The embodiments of the present invention are merely preferred embodiments for easy understanding or implementing of the technical solutions of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes in structure, shape and principle of the present invention should be covered by the claims of the present invention.