阅读说明：本技术 半导体模组及用于该半导体模组的半导体装置 (Semiconductor module and semiconductor device used for the same ) 是由 大泽青吾 大仓康嗣 中野贵博 水野直仁 竹中正幸 犬塚仁浩 于 2020-03-12 设计创作，主要内容包括：一种半导体模组,具备：第1散热部件(1、7)；半导体装置(2),具备半导体元件(20)、将其周围覆盖的封固件(21)、以及再布线层(24),搭载在第1散热部件上,上述再布线层具备与半导体元件电连接的第1布线(26)及第2布线(27),形成在半导体元件及封固件之上；第2散热部件(3、7),配置在半导体装置上；引线框(4),经由接合件(5)而与半导体装置电连接；以及封固件(6),将第1散热部件的一部分、半导体装置、以及第2散热部件的一部分覆盖。半导体装置的一部分从第2散热部件中的与半导体装置面对的另一面(3b)的外轮廓伸出,第2布线的一端延伸设置至半导体装置中的从另一面的外轮廓伸出的部分,一端经由接合件而与引线框电连接。(A semiconductor module includes: a 1 st heat sink member (1, 7); a semiconductor device (2) which is provided with a semiconductor element (20), a sealing member (21) covering the periphery of the semiconductor element, and a rewiring layer (24) which is mounted on the 1 st heat dissipation member, is provided with a 1 st wiring (26) and a 2 nd wiring (27) electrically connected with the semiconductor element, and is formed on the semiconductor element and the sealing member; a 2 nd heat dissipation member (3, 7) disposed on the semiconductor device; a lead frame (4) electrically connected to the semiconductor device via a bonding material (5); and a sealing member (6) that covers a part of the 1 st heat dissipation member, the semiconductor device, and a part of the 2 nd heat dissipation member. A part of the semiconductor device is extended from the outer contour of the other surface (3b) of the 2 nd heat sink member facing the semiconductor device, one end of the 2 nd wiring is extended to the part of the semiconductor device extended from the outer contour of the other surface, and one end is electrically connected to the lead frame via the bonding material.)

1. A semiconductor module is characterized in that,

the disclosed device is provided with:

a 1 st heat sink member (1, 7);

a semiconductor device (2) having a semiconductor element (20), a sealing member (21) covering the periphery thereof, and a rewiring layer (24) mounted on the 1 st heat sink member, the rewiring layer (24) having a 1 st wiring (26) and a 2 nd wiring (27) electrically connected to the semiconductor element and formed on the semiconductor element and the sealing member;

2 nd heat dissipation members (3, 7) disposed on the semiconductor device;

a lead frame (4) electrically connected to the semiconductor device via a bonding material (5); and

a sealing member (6) that covers a part of the 1 st heat dissipation member, the semiconductor device, and a part of the 2 nd heat dissipation member;

a part of the semiconductor device is extended from an outer contour of another surface (3b) of the 2 nd heat sink member facing the semiconductor device;

one end of the 2 nd wire extends to a portion of the semiconductor device protruding from the outer contour of the other surface, and the one end is electrically connected to the lead frame via the bonding material.

2. The semiconductor module of claim 1,

the semiconductor device is disposed inside an outer contour of an upper surface (1a) of the 1 st heat sink member facing the semiconductor device.

3. The semiconductor module according to claim 1 or 2,

the 1 st heat dissipation member and the 2 nd heat dissipation member are heat sinks (1, 3), respectively, and at least 1 constitutes a conductive path.

4. The semiconductor module according to claim 1 or 2,

the 1 st heat dissipation member and the 2 nd heat dissipation member are heat transfer insulating substrates (7), respectively.

5. The semiconductor module according to claim 1 or 2,

the 1 st heat dissipation member and the 2 nd heat dissipation member are respectively laminated with heat sinks (1, 3) and a heat transfer insulating substrate (7), and the heat transfer insulating substrate is connected to the semiconductor device via the joint.

6. The semiconductor module according to any one of claims 1 to 5,

setting the semiconductor element as a 1 st semiconductor element (201), wherein the semiconductor device has a relay member (29) and a 2 nd semiconductor element (202) at a portion extending from the outer contour of the other surface;

further comprising a 3 rd heat dissipation member (7, 8) and a 4 th heat dissipation member (7, 9) which are arranged to face each other with the 2 nd semiconductor element interposed therebetween;

a surface of the semiconductor device facing the 2 nd heat dissipation member is a front surface (2a), and an opposite surface thereof is a rear surface (2 b);

the 3 rd heat dissipating member is disposed to face the rear surface and to be spaced from the 1 st heat dissipating member by the sealing member;

the 4 th heat radiating member is disposed to face the surface and to be spaced from the 2 nd heat radiating member by the sealing member;

at least 1 of the relay members extends in a direction connecting the front surface and the rear surface, and has one end electrically connected to the 1 st heat dissipation member via a bonding member and the other end electrically connected to the 4 th heat dissipation member via a bonding member.

7. The semiconductor module of claim 6,

the relay member is offset in a portion exposed from the rewiring layer on the front surface and in a portion exposed from the sealing member on the rear surface, as viewed in a normal direction with respect to the front surface.

8. The semiconductor module of claim 7,

the relay member has a cross-sectional shape having at least 1 step in a direction connecting the front surface and the back surface.

9. The semiconductor module according to any one of claims 6 to 8,

the 3 rd heat dissipation member and the 4 th heat dissipation member are heat sinks (8, 9), respectively.

10. The semiconductor module according to any one of claims 6 to 8,

the 3 rd heat dissipation member and the 4 th heat dissipation member are each a heat transfer insulating substrate (7).

11. The semiconductor module according to any one of claims 1 to 10,

of the two ends of the lead frame, the end portion on the side connected with the 2 nd wiring via the bonding material is a 1 st end portion (4a), the end portion opposite to the 1 st end portion is a 2 nd end portion (4b), and the direction from the 1 st end portion to the 2 nd end portion is an extending direction;

the lead frame has a boundary portion (41) which is a boundary portion where the direction of the extending direction changes between the 1 st end portion and the 2 nd end portion, and a portion between the 1 st end portion and the boundary portion is a stress relaxation portion (42) where at least 1 of the thickness, the width, and the direction of the extending direction of the lead frame is different from the other portions of the lead frame.

12. The semiconductor module of claim 11,

a portion of the lead frame between the 1 st end portion and the boundary portion has a planar shape on the same plane;

the stress relaxing portion is provided in a direction different from the other portions in the extending direction.

13. The semiconductor module according to claim 1 or 2,

a surface of the second heat dissipating member 2 opposite to the other surface is defined as a first surface (3a), a region of the other surface of the second heat dissipating member 2 to which the semiconductor device is bonded via the bonding material is defined as a bonding region (3ba), the remaining portion thereof is defined as a non-bonding region (3bb), and a portion of the non-bonding region located in the vicinity of the bonding region is defined as a bonding vicinity region (3 bc);

the 2 nd heat dissipation component is a heat sink, and at least a part of the non-joint area is formed into a concave part (31) which is concave from the other surface to the one surface;

the clearance (D2) between the outer contour of the other surface in the non-bonding region and the semiconductor device is larger than the clearance (D1) between the outer contour of the other surface in the bonding vicinity region and the semiconductor device.

14. The semiconductor module of claim 13,

the concave portion is tapered so as to be inclined from the joining vicinity area toward the outer contour of the other surface.

15. The semiconductor module of claim 14,

the surface of the recess is an inclined surface, and an acute angle of an angle formed by the inclined surface and a surface formed by the joining region is a taper angle (θ) of 45 ° or less.

16. The semiconductor module of claim 13,

the recess includes the outer contour of the other surface and is formed in a stepped shape from the outer contour side of the other surface toward the joint vicinity region.

17. The semiconductor module according to any one of claims 1 to 16,

a roughened portion (261) in which a portion of the 1 st wiring exposed from the insulating layer (25) constituting the rewiring layer is roughened;

the 2 nd wiring is a roughened portion (271) in which a portion covered with the insulating layer and a portion exposed from the insulating layer are roughened.

18. The semiconductor module according to any one of claims 1 to 17,

of both ends of the lead frame, a 1 st end (4a) is provided as an end connected to the 2 nd wire via the bonding material, and a 2 nd end (4b) is provided as an end opposite to the 1 st end;

a part of the lead frame on the side of the 1 st end is a region in which wettability of the bonding material is higher than regions other than the region;

the lead frame is connected to the semiconductor device via the high-wettability region.

19. The semiconductor module of claim 18,

setting the exposed part of the 2 nd wiring from the insulating layer (25) forming the rewiring layer as an exposed part;

a groove (44) recessed toward the opposite side of the semiconductor device is formed in a portion of the lead frame closer to the 2 nd end portion than an opposing portion facing the exposed portion;

the groove portion and a region from the opposing portion to the groove portion are regions having higher wettability than other regions of the lead frame.

20. The semiconductor module according to any one of claims 1 to 12 and 16 to 19,

setting a surface of an outer surface of the semiconductor device facing the 2 nd heat dissipation member as a surface (2a), and setting a partial region in the vicinity of an outer contour of the surface and facing the other surface of the 2 nd heat dissipation member as an outer edge region (2 aa);

the semiconductor device includes a protrusion (2c) in the outer edge region, the protrusion suppressing contact between the other surface of the 2 nd heat dissipation member and the semiconductor device.

21. The semiconductor module of claim 20,

the protrusion is configured to include solder and is joined to the other surface of the 2 nd heat dissipation member.

22. A semiconductor device having a semiconductor module with a double-sided heat dissipation structure including a 1 st heat dissipation member (1, 7) and a 2 nd heat dissipation member (3, 7) and arranged between the 1 st heat dissipation member and the 2 nd heat dissipation member,

the disclosed device is provided with:

a semiconductor element (20);

a sealing member (21) for surrounding the periphery of the semiconductor element; and

a rewiring layer (24) formed on the semiconductor element and the sealing member;

the rewiring layer has an insulating layer (25), and a 1 st wiring (26) and a 2 nd wiring (27) which are formed in the insulating layer and one ends of which are connected to the semiconductor element;

the 1 st wiring is arranged inside an outer contour of the semiconductor element in a plan view;

the other end of the 2 nd wiring extends to a region outside the outer contour of the semiconductor element in a plan view.

Technical Field

The present invention relates to a semiconductor module having a double-sided heat dissipation structure implemented by two heat dissipation members arranged to face each other with a power semiconductor element interposed therebetween, and a semiconductor device used for the semiconductor module.

Background

Conventionally, as a semiconductor module having a double-sided heat dissipation structure including a power semiconductor element such as an IGBT and two heat dissipation members disposed to face each other with the power semiconductor element interposed therebetween, for example, a structure described in patent document 1 is given. In the semiconductor module described in patent document 1, a lower heat sink, a power semiconductor element, a heat dissipation block, and an upper heat sink are stacked in this order with solder interposed therebetween. The semiconductor module includes a lead frame, a wire electrically connecting the lead frame and the gate of the power semiconductor element, and a sealing member covering the lead frame and the gate of the power semiconductor element. The surfaces of the lower heat sink and the upper heat sink of the semiconductor module opposite to the power semiconductor element are exposed from the sealing material. That is, the semiconductor module is configured to release heat generated by applying current to the power semiconductor element to the outside through the two heat sinks, i.e., the heat dissipation members.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open No. 2001-156225

Disclosure of Invention

In the semiconductor module described above, the heat dissipation block is disposed so that a gap between two heat dissipation members is not less than a predetermined value, and the heat dissipation members are prevented from contacting the wire or short-circuiting the wire. However, the heat dissipation block is an obstacle to thinning of the semiconductor module, and also becomes a factor of increasing the thermal resistance from the power semiconductor element to the heat dissipation member.

The invention provides a semiconductor module having a power semiconductor element and two heat dissipation members arranged to face each other with the power semiconductor element interposed therebetween, and a double-sided heat dissipation structure thinner and lower in thermal resistance than conventional semiconductor modules, and a semiconductor device used for the semiconductor module.

According to one aspect of the present invention, a semiconductor module includes: a 1 st heat dissipating member; a semiconductor device including a semiconductor element, a sealing member covering the periphery of the semiconductor element, and a rewiring layer, the rewiring layer including a 1 st wire and a 2 nd wire electrically connected to the semiconductor element and formed on the semiconductor element and the sealing member, the rewiring layer being mounted on the 1 st heat dissipation member; a 2 nd heat dissipation member disposed on the semiconductor device; a lead frame electrically connected to the semiconductor device via a bonding material; and a sealing member covering a part of the 1 st heat dissipation member, the semiconductor device, and a part of the 2 nd heat dissipation member. A part of the semiconductor device is extended from the outer contour of the other surface of the 2 nd heat sink member facing the semiconductor device, one end of the 2 nd wiring is extended to the part of the semiconductor device extended from the outer contour of the other surface, and one end is electrically connected to the lead frame via solder.

Thus, the semiconductor module has a double-sided heat dissipation structure in which the semiconductor device and the 2 nd heat dissipation member, and the semiconductor device and the lead frame are connected by the bonding material. Therefore, the semiconductor module does not need a heat dissipation block and a wire rod which are required in the conventional structure, and the thickness and the thermal resistance are reduced accordingly, so that the semiconductor module is thinner and has lower thermal resistance than the conventional semiconductor module.

According to another aspect of the present invention, a semiconductor device is used for a semiconductor module having a double-sided heat dissipation structure including a 1 st heat dissipation member and a 2 nd heat dissipation member, and is disposed between the 1 st heat dissipation member and the 2 nd heat dissipation member; the disclosed device is provided with: a semiconductor element; a sealing member surrounding the semiconductor element; and a rewiring layer formed on the semiconductor element and the sealing member; the rewiring layer has an insulating layer, and a 1 st wiring and a 2 nd wiring formed in the insulating layer and having one end connected to the semiconductor element; the 1 st wiring is arranged inside the outer contour of the semiconductor element in a plan view; the second end of the 2 nd wiring extends to a region outside the outer contour of the semiconductor element in a plan view.

Thus, the semiconductor device can be solder-bonded to the 2 nd heat dissipation member and the lead frame without using a heat dissipation block and a wire, and is suitable for manufacturing a semiconductor module thinner and lower in thermal resistance than the conventional semiconductor device.

The parenthesized reference numerals given to the respective components and the like are used to show an example of the correspondence between the components and the like and the specific components and the like described in the embodiments described later.

Drawings

Fig. 1 is a cross-sectional view showing the structure of a semiconductor module according to embodiment 1.

Fig. 2 is a cross-sectional view showing the structure of the semiconductor device in fig. 1.

Fig. 3 is a perspective view showing the semiconductor device of fig. 2.

Fig. 4 is a cross-sectional view showing the structure of a conventional semiconductor module.

Fig. 5A is a sectional view showing a preparation process of a semiconductor substrate, which is a manufacturing process of a semiconductor device in the manufacturing process of the semiconductor module of fig. 1.

Fig. 5B is a cross-sectional view showing a manufacturing process of the semiconductor device next to fig. 5A.

Fig. 5C is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5B.

Fig. 5D is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5C.

Fig. 5E is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5D.

Fig. 5F is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5E.

Fig. 5G is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5F.

Fig. 5H is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5G.

Fig. 5I is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5H.

Fig. 5J is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5I.

Fig. 5K is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5J.

Fig. 5L is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5K.

Fig. 5M is a cross-sectional view showing a manufacturing process of the semiconductor device, which follows fig. 5L.

Fig. 6A is a sectional view showing a process of mounting a semiconductor device, which is a process of manufacturing the semiconductor module of fig. 1.

Fig. 6B is a cross-sectional view showing a manufacturing process of the semiconductor module, which follows fig. 6A.

Fig. 6C is a plan view showing the manufacturing process of fig. 6B.

Fig. 6D is a cross-sectional view showing a manufacturing process of the semiconductor module, which follows fig. 6B.

Fig. 7 is a cross-sectional view showing the structure of the semiconductor module according to embodiment 2.

Fig. 8 is a sectional view showing the structure of the semiconductor module according to embodiment 3.

Fig. 9 is a perspective view showing a semiconductor device in the semiconductor module of fig. 8.

Fig. 10 is a plan view showing an example of arrangement of each component in the semiconductor module of fig. 8.

Fig. 11 is a cross-sectional view showing a structure of a modification of the semiconductor module according to embodiment 3.

Fig. 12 is a cross-sectional view showing an example of the structure of a lead frame in the semiconductor module according to embodiment 4.

Fig. 13 is a view looking from the direction of XIII shown in fig. 12.

Fig. 14 is a diagram for explaining stress generated in a lead frame without a stress relaxing portion.

Fig. 15 is a view showing a 1 st modification of the stress relaxing section, and is a view corresponding to fig. 13.

Fig. 16 is a view showing a 2 nd modification of the stress relaxing section, and is a cross-sectional view corresponding to fig. 12.

Fig. 17 is a view from the direction of XVII shown in fig. 16.

Fig. 18 is a sectional view showing the structure of the semiconductor module according to embodiment 5.

Fig. 19 is a diagram for explaining a surface of the heat sink facing the semiconductor device.

Fig. 20 is a diagram for explaining a gap between the other surface of the heat sink and one surface of the semiconductor device.

Fig. 21 is a cross-sectional view showing a structure of a modification of the semiconductor module according to embodiment 5.

Fig. 22 is a cross-sectional view showing a configuration example of a semiconductor device in the semiconductor module according to embodiment 6.

Fig. 23 is a cross-sectional view showing an example of the structure of a lead frame in the semiconductor module according to embodiment 7.

Fig. 24 is a cross-sectional view showing a structure of a modification of the lead frame according to embodiment 7.

Fig. 25 is a cross-sectional view showing a configuration example of a semiconductor device in the semiconductor module according to embodiment 8.

Fig. 26 is a plan view showing an example of arrangement of the protruding portions in the semiconductor device according to embodiment 8.

Fig. 27 is a plan view showing another example of the arrangement of the protruding portions in the semiconductor device according to embodiment 8.

Fig. 28 is a sectional view showing the structure of another modification of embodiment 3.

Fig. 29 is a cross-sectional view showing a structure of a modification of the semiconductor device according to the other embodiment.

Fig. 30 is a sectional view showing a configuration of a modification of embodiment 2.

Fig. 31 is a sectional view showing the structure of another modification of embodiment 3.

Fig. 32 is a sectional view showing a configuration of a modification of embodiment 1.

Fig. 33 is a view showing a molding process of the sealing member in the manufacturing process of the semiconductor module shown in fig. 32.

Fig. 34 is a sectional view showing the structure of another modification of embodiment 5.

Fig. 35 is a cross-sectional view showing a configuration example of a semiconductor module using a heat transfer insulating substrate provided with a step portion.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent portions are given the same reference numerals and are described.

(embodiment 1)

The semiconductor module S1 of embodiment 1 will be described with reference to fig. 1 to 3. The semiconductor module S1 is suitably used, for example, in a power converter or the like that converts dc current into ac current for supplying power to a motor for running of an automobile, and may be referred to as a "power card".

In fig. 1, a wiring portion connected to the outside in another cross section of the 2 nd heatsink 3 described later is indicated by a broken line. In fig. 2, the boundaries of regions into which the insulating layer 25 described later is divided conveniently are indicated by broken lines. Fig. 2 corresponds to a cross-sectional view between II and II indicated by a one-dot chain line in fig. 3.

(Structure)

As shown in fig. 1, the semiconductor module S1 of the present embodiment includes a 1 st heatsink 1, a semiconductor device 2, a 2 nd heatsink 3, a lead frame 4, a bonding material 5, and a sealing material 6. The semiconductor module S1 is a double-sided heat dissipation structure in which two heat sinks 1 and 3 are arranged to face each other with the semiconductor device 2 interposed therebetween, and heat generated by the semiconductor device 2 is dissipated from both sides to the outside via the heat sinks 1 and 3.

The 1 st heatsink 1 is, as shown in fig. 1, plate-shaped and includes an upper surface 1a and a lower surface 1b having a relationship of a front surface and a rear surface, and is made of, for example, a metal material such as Cu (copper) or Fe (iron). The 1 st heatsink 1 mounts the semiconductor device 2 on the upper surface 1a via a bonding material 5 formed of solder, and the lower surface 1b is exposed from a sealing material 6. The 1 st heatsink 1 serves as a current path for the semiconductor device 2 during current conduction in the present embodiment, and a part of the upper surface 1a side extends to the outside of the sealing material 6 as shown in fig. 1, for example. That is, the 1 st heatsink 1 in the present embodiment functions as both a heat dissipation member and a wiring. In addition, the 1 st heatsink 1 may be referred to as a "1 st heat sink member".

As shown in fig. 2, the semiconductor device 2 is a plate-like device having a front surface 2a and a back surface 2b, and includes a semiconductor element 20, a sealing member 21, a 1 st electrode 22, a 2 nd electrode 23, and a rewiring layer 24. The semiconductor device 2 has a fan-out (fanout) type package structure (hereinafter referred to as an "FO package structure") as follows: the 2 nd wiring 27 connected to the 2 nd electrode 23 is provided as a part of the rewiring layer 24, and one end of the 2 nd wiring 27 is extended to the outside of the outer contour of the semiconductor element 20. The semiconductor device 2 may have an FO package structure, and may have a wafer-level package structure or a panel-level package structure.

As shown in fig. 1, the semiconductor device 2 is disposed inside the outer contour of the upper surface 1a of the 1 st heatsink 1. The semiconductor device 2 has the following structure: a part of the second wiring 27 protrudes outside the outer contour of the other surface 3b of the 2 nd heatsink 3, and one end of the second wiring extends to the protruding part. This is because the lead connection to the lead frame 4 and the heat dissipation block between the semiconductor device 2 and the 2 nd heatsink 3 are not required, and the thinning and low thermal resistance can be achieved compared to the conventional case. Details will be described later.

The semiconductor element 20 is mainly made of a semiconductor material such as silicon or silicon carbide, and is a power semiconductor element such as a MOS transistor or an IGBT (insulated gate bipolar transistor), for example, and is manufactured by a normal semiconductor process. In the semiconductor element 20, a 3 rd electrode, not shown, is formed on a surface opposite to the surface on which the 1 st electrode 22 and the 2 nd electrode 23 are formed, and the 3 rd electrode is electrically connected to the upper surface 1a of the 1 st heat sink 1 via the bonding material 5.

As shown in fig. 2, the sealing member 21 is a member that covers the periphery of the semiconductor element 20, and is made of any resin material such as epoxy resin, for example. The sealing member 21 covers the end face of the semiconductor element 20, and constitutes the rear surface 2b of the semiconductor device 2 together with the surface of the semiconductor element 20 opposite to the surface on which the 1 st electrode 22 is formed.

The 1 st electrode 22, the 2 nd electrode 23, and a 3 rd electrode not shown are made of a metal material such as Cu, for example, and are formed on one surface of the semiconductor element 20 by plating or the like. The 1 st electrode 22 and the 3 rd electrode are a pair and serve as a main current path of the semiconductor element 20. The 1 st electrode 22 is, for example, an emitter electrode. The 2 nd electrode 23 is formed in plural, at least 1 of which is, for example, a gate electrode for controlling on/off of a current between the 1 st electrode 22 and the 3 rd electrode. Among the plurality of 2 nd electrodes 23, an electrode different from the gate electrode is used as a sensor terminal on the element, for example.

Further, the 1 st electrode 22 and the 2 nd electrode 23 are formed of a metal material such as Cu by plating in the same manner as the 1 st wiring 26 and the 2 nd wiring 27 by a manufacturing method described later, and heat dissipation is improved as compared with the case of forming the electrodes of a material such as Al (aluminum).

As shown in fig. 2, the rewiring layer 24 includes an insulating layer 25, a 1 st wire 26 connected to the 1 st electrode 22, and a 2 nd wire 27 connected to the 2 nd electrode 23, and is formed on the semiconductor element 20 and the sealing member 21 by a normal rewiring technique.

The insulating layer 25 is made of an insulating material such as polyimide, and is formed by an arbitrary coating process or the like.

The 1 st wiring 26 and the 2 nd wiring 27 are made of, for example, a metal material such as Cu, and are formed by plating or the like. The 1 st wiring 26 is formed inside the outer contour of the semiconductor element 20 in plan view, and one end thereof is electrically and thermally connected to the 2 nd heat sink 3 via the bonding material 5. The 2 nd wiring 27 extends to the outside of the outer contour of the semiconductor element 20 at one end in a plan view, and is electrically connected to the lead frame 4 via the bonding material 5. As shown in fig. 3, for example, the 2 nd wiring 27 is formed in plural, and one end thereof extends to the outside of the outer contour of the semiconductor element 20. Fig. 3 shows an example in which 52 nd wirings 27 are formed and connected to different 2 nd electrodes 23, respectively, but the number of the 2 nd electrodes 23 and the 2 nd wirings 27 is arbitrary.

The 2 nd heatsink 3 is, as shown in fig. 1, plate-shaped having one surface 3a and the other surface 3b having a relationship of a front surface and a back surface, and is made of the same material as the 1 st heatsink 1. The 2 nd heatsink 3 is disposed to face a part of the front surface 2a of the semiconductor device 2in the present embodiment. The 2 nd heat sink 3 is electrically connected to the 1 st wiring 26 via the bonding material 5 in the present embodiment, and serves as a current path of the semiconductor element 20 similarly to the 1 st heat sink 1, and a part of the other surface 3b side extends to the outside of the sealing material 6 in the other cross section of fig. 1. That is, the 2 nd heatsink 3 functions as both a heat dissipation member and a wiring in the present embodiment. In addition, the 2 nd heatsink 3 may be referred to as a "2 nd heat dissipation member".

The lead frame 4 is made of a metal material such as Cu or Fe, for example, and is electrically connected to the 2 nd wiring 27 in the semiconductor device 2 via the bonding material 5, as shown in fig. 1. The lead frame 4 includes a plurality of conductors, for example, the same number as the 2 nd electrode 23. In addition, these conductors are connected by a tie bar (tie bar), not shown, before the sealing material 6 is formed, and after the sealing material 6 is formed, the tie bar is removed by pressing or the like to separate the conductors. The lead frame 4 may be configured as the same member as the 2 nd heatsink 3, and may be connected by a tie bar, not shown, before the sealing material 6 is formed. In this case, the lead frame 4 is separated from the 2 nd heat sink 3 by removing the tie bars by pressing or the like after the sealing material 6 is formed.

The bonding material 5 is a bonding material for bonding the components of the semiconductor module S1 to each other, and a conductive material, such as solder, is used for electrical connection. The joining material 5 is not limited to solder, but is made of a material different from at least the wire material.

The sealing member 6 is made of, for example, thermosetting resin such as epoxy resin, and covers the heat sinks 1 and 3, the semiconductor device 2, the lead frame 4, and the bonding material 5, as shown in fig. 1.

The above is the basic structure of the semiconductor module S1 of the present embodiment.

(Effect)

Next, the effect of the semiconductor module S1 of the present embodiment will be described in comparison with the semiconductor module S100 of the conventional structure shown in fig. 4.

First, the semiconductor module S100 of the conventional structure will be briefly described. Since the structure of the semiconductor module S100 is well known, the points different from the semiconductor device 2 will be mainly described here.

As shown in fig. 4, a semiconductor module S100 of a conventional structure includes a semiconductor device 101, heat sinks 1 and 3 arranged to face each other with the heat sink therebetween, a heat dissipation block 102, a wire 103, a lead frame 4, a bonding material 5, and a sealing material 6.

As shown in fig. 4, the semiconductor device 101 includes a semiconductor element 20 including a 1 st electrode 22, a 2 nd electrode 23, and a 3 rd electrode not shown, and does not include a sealing member 21 and a rewiring layer 24 unlike the semiconductor device 2. The semiconductor device 101 is mounted on the 1 st heat sink 1 via the bonding material 5, and is disposed inside the outer contour of the upper surface 1a of the 1 st heat sink 1 and inside the outer contour of the other surface 3b of the 2 nd heat sink 3.

Heat dissipation block 102 is made of a metal material such as Cu, and as shown in fig. 4, one surface thereof is connected to 1 st electrode 22 of semiconductor element 20 via bonding material 5, and the other surface thereof is connected to 2 nd heat sink 3 via bonding material 5. The heat dissipation block 102 constitutes a current path of the semiconductor element 20, and functions to transfer heat generated by the semiconductor element 20 to the 2 nd heat sink 3. Heat dissipation block 102 is disposed so that the gap between semiconductor element 20 and 2 nd heat sink 3 is equal to or larger than a predetermined value, and wire 103 connected to 2 nd electrode 23 is prevented from contacting and shorting to 2 nd heat sink 3.

The wire 103 is made of a metal material such as Al (aluminum) or Au (gold), and is bonded to the 2 nd electrode 23 and the lead frame 4 by wire bonding to electrically connect them.

Since the conventional semiconductor module S100 needs to have the heat dissipation block 102 disposed between the semiconductor device 101 and the 2 nd heatsink 3 to secure a gap, it is difficult to further reduce the thickness of the semiconductor module. Further, the semiconductor module S100 has two layers of bonding members and 1 heat dissipation block 102 between the semiconductor device 101 and the 2 nd heatsink 3, and accordingly the thermal resistance becomes large.

In contrast, in the semiconductor module S1 of the present embodiment, the semiconductor device 2 has the rewiring layer 24 and is disposed so that a part thereof protrudes outside the outer contour of the second surface 3b of the 2 nd heatsink 3. The semiconductor module S1 has a structure in which the 2 nd wiring 27 extending to the outside of the outer contour of the other surface 3b of the 2 nd heatsink 3 in the semiconductor device 2 is bonded to the lead frame 4 via a bonding material 5 made of solder. Thus, in semiconductor module S1, semiconductor device 2 and 2 nd heatsink 3 can be directly soldered, and heat dissipation block 102 and wire 103 are not required.

As a result, the 1 st-layer bonding material 5 connecting the semiconductor device 2 and the 2 nd heatsink 3 is reduced in thickness corresponding to the heat dissipation block 102 and the 1 st-layer bonding material 5, and a semiconductor module having a structure with a small heat resistance is obtained. From another point of view, the semiconductor device 2 can be soldered to the lead frame 4 by being formed into an FO package structure, and can be said to have a structure suitable for thinning and reducing the thermal resistance of a semiconductor module having a double-sided heat dissipation structure. Further, by configuring the semiconductor device 2 to have the rewiring layer 24, the planar size of the 1 st electrode 22 and the 2 nd electrode 23 and the planar size of the semiconductor element 20 can be reduced, and an effect of improvement in terms of cost can be expected.

It is also conceivable to reduce the area of the 2 nd heatsink 3 only, dispose the 2 nd electrode 23 of the semiconductor element 20, on which the rewiring layer 24 is not formed, outside the outer contour of the 2 nd heatsink 3, and connect the 2 nd electrode 23 to the lead frame 4 with the wire 103.

However, in this method, although the heat dissipation block 102 is not required and the thermal resistance is reduced accordingly, the planar size of the 2 nd heatsink 3 is also reduced and the thermal resistance is increased accordingly. As a result, the heat dissipation performance of the semiconductor module having such a structure may be unchanged from that of the conventional semiconductor module, and may be deteriorated. Further, in order to connect the wires 103, it is necessary to increase the planar size of the 2 nd electrode 23, and the planar size of the semiconductor element 20 is increased, which may deteriorate the cost. Further, when the wire 103 is used, a wiring length is required to prevent a short circuit, and since inductance is increased, noise is likely to be generated in a high-frequency signal when the wire is connected to an ac power supply.

Therefore, the semiconductor module S1 using the semiconductor device 2 having the FO package structure is expected to have effects of reducing noise of high-frequency signals and cost due to the miniaturization of the semiconductor element 20, in addition to the structure of being thinner and having a lower thermal resistance than the conventional one.

(production method)

Next, an example of a method for manufacturing the semiconductor module S1 according to the present embodiment will be described with reference to fig. 5A to 6C.

First, as shown in fig. 5A, a semiconductor element 20 manufactured by a normal semiconductor process is prepared, and the surface of the semiconductor element 20 on which the 1 st electrode 22 and the 2 nd electrode 23 are formed is attached to and held by the support substrate 110. The support substrate 110 may be any structure having an adhesive sheet, not shown, on the surface thereof, which has high adhesion to silicon.

Next, a mold, not shown, is prepared, the semiconductor element 20 held by the support substrate 110 is covered with a resin material such as an epoxy resin by compression molding or the like, and the package member 21 is molded by hardening by heating or the like as shown in fig. 5B. Then, the semiconductor element 20 covered with the sealing member 21 is peeled off from the support substrate 110.

Next, a solution containing a photosensitive resin material such as polyimide is applied to the exposed surface of the semiconductor element 20 by spin coating or the like, and dried, thereby forming a 1 st layer 251 constituting the insulating layer 25 as shown in fig. 5C.

Then, as shown in fig. 5D, after patterning the 1 st layer 251 by photolithography, a 1 st seed (seed) layer 281 made of Cu or the like is formed by a vacuum film formation method such as sputtering.

Next, as shown in fig. 5E, a resist layer 253 covering the 1 st layer 251 and the 1 st seed layer 281 is formed. The resist layer 253 can be formed by a spin coating method or the like as in the case of the 1 st layer 251, using a photosensitive resin material.

Next, by the same process as the patterning of the 1 st layer 251, the resist layer 253 is patterned to form an opening portion including a region where the 1 st layer 251 is removed, as shown in fig. 5F.

Next, a plating layer of Cu or the like is formed by plating or the like, and as shown in fig. 5G, the 1 st electrode 22 and the 2 nd electrode 23 are formed, and then, a part of the 1 st wiring 26 and a part of the 2 nd wiring 27 are formed.

Next, as shown in fig. 5H, after the resist layer 253 is removed by a stripping liquid or the like, the portion of the 1 st seed layer 281 exposed by the removal of the resist layer 253 is removed by an etching liquid.

Next, as shown in fig. 5I, a 2 nd layer 252 constituting the insulating layer 25 is formed by a spin coating method using a photosensitive resin material similarly to the 1 st layer 251, and then patterned by a photolithography method.

Next, as shown in fig. 5J, a 2 nd seed layer 282 made of Cu or the like is formed by a vacuum film forming method such as sputtering. After the formation of the 2 nd seed layer 282, a resist layer 253 is formed on the 2 nd layer 252 by the same process as described above, and patterning is performed, thereby forming the resist layer 253 covering the 2 nd layer 252, a part of the 1 st wiring 26, and a part of the 2 nd wiring 27 as shown in fig. 5K.

Next, after the remaining portions of the 1 st wiring 26 and the 2 nd wiring 27 made of Cu or the like are formed by plating or the like, the resist layer 253 is removed by a stripping liquid, and the 2 nd seed layer 282 exposed by the removal of the resist layer 253 is removed by an etching liquid or the like. As a result, as shown in fig. 5L, the rewiring layer 24 including the 1 st wiring 26 and the 2 nd wiring 27 is formed on the semiconductor element 20 and the sealing member 21.

Next, as shown in fig. 5M, the surface of the sealing member 21 opposite to the rewiring layer 24 is thinned by polishing or the like to expose the semiconductor element 20. Then, a 3 rd electrode, not shown, is formed on the exposed surface of the semiconductor element 20 by a vacuum film forming method such as sputtering. The 3 rd electrode not shown may be formed only on the exposed surface of the semiconductor element 20, or may be formed on the entire surface of the sealing member 21 including the polished surface on the opposite side of the rewiring layer 24 in addition to the exposed surface. In the former case, the 3 rd electrode can be formed only on the exposed surface of the semiconductor element 20 by using a metal mask not shown.

The semiconductor device 2 can be manufactured through the above steps, but any other semiconductor process than the above may be adopted. For example, in the step of preparing the semiconductor element 20 shown in fig. 5A, the semiconductor element 20 having the 3 rd electrode formed thereon may be prepared. In this case, after the 3 rd electrode is covered with the sealing member 21, the 3 rd electrode is exposed by thinning the sealing member 21, and there is no particular problem. In this way, the manufacturing process of the semiconductor device 2 can be appropriately changed.

Next, as shown in fig. 6A, the 1 st heatsink 1 made of a metal material such as Cu is prepared, and the semiconductor device 2 is soldered thereto. The 1 st heat sink 1 is obtained by an arbitrary step of, for example, subjecting a metal plate made of Cu to press working, and then forming a wiring portion connected to an external power supply or the like by dry etching.

Next, as shown in fig. 6B, after applying solder to the 1 st wiring 26 and the 2 nd wiring 27 of the semiconductor device 2, the 2 nd heatsink 3 prepared separately is placed on the 1 st wiring 26, and the lead frame 4 is placed on the 2 nd wiring 27, and soldering is performed. Thus, as shown in fig. 6C, the semiconductor device 2 is in the following state in plan view: is arranged inside the outer contour of the 1 st heat sink 1 and a part of which protrudes from the outer contour of the 2 nd heat sink 3 and is connected to the lead frame 4 at the protruding part. As shown in fig. 6C, the semiconductor device 2 preferably has a larger planar size than a portion of at least one of the heat sinks connected to the semiconductor device 2. This is to facilitate filling of the resin material during molding of the sealing member 6 described later and to suppress occurrence of voids. The 2 nd heatsink 3 is obtained by the same process as the 1 st heatsink 1. The lead frame 4 is obtained by subjecting a metal plate made of Cu to an arbitrary step such as press working, for example. Alternatively, after the semiconductor device 2 is bonded to the 2 nd heatsink 3 and the lead frame 4, the semiconductor device 2 may be bonded to the 1 st heatsink 1.

Next, as shown in fig. 6D, a mold 300 including an upper mold 301 and a lower mold 302 and having a cavity 303 corresponding to the outer shape of the sealing material 6 is prepared. Then, the semiconductor device 2 to which the heat sinks 1 and 3 and the lead frame 4 are bonded is put into the cavity 303. After the work is put in, a resin material such as epoxy resin is injected into the cavity 303 from an injection port not shown, and is hardened by heating or the like to mold the sealing material 6. After the molding of the sealing material 6, the work is released from the die 300, and the tie bars of the lead frame 4 are removed by press working or the like, whereby the semiconductor module S1 of the present embodiment can be manufactured.

According to the present embodiment, semiconductor device 2 having an FO package structure is directly soldered to heatsink 23 and leadframe 4, thereby providing semiconductor module S1 having a double-sided heat dissipation structure that does not require heat dissipation block 102 and wire 103. Therefore, the semiconductor module S1 is thinner and has a lower thermal resistance than the conventional semiconductor module S100 including the heat dissipation block 102 and the wire 103.

(embodiment 2)

The semiconductor module S2 of embodiment 2 will be described with reference to fig. 7. In fig. 7, in other cross section, a wiring extending from the heat transfer insulating substrate 7 described later to the outside is indicated by a broken line.

The semiconductor module S2 of the present embodiment is different from the above embodiment 1 in that 2 total heat transfer insulating substrates 7 are disposed between the 1 st heatsink 1 and the semiconductor device 2 and between the semiconductor device 2 and the 2 nd heatsink 3, as shown in fig. 7. In the present embodiment, the difference will be mainly described.

As shown in fig. 7, the heat transfer insulating substrate 7 includes a conductive portion 71, an insulating portion 72, and a heat conductive portion 73 stacked in this order. The conductive portion 71 of one of the heat transfer insulating substrates 7 is connected to the semiconductor device 2 via the bonding material 5, and the heat conductive portion 73 is connected to the 1 st heatsink 1 via solder or the like, not shown. The conductive portion 71 of the other heat transfer insulating substrate 7 is connected to the semiconductor device 2 via the bonding material 5, and the heat conductive portion 73 is connected to the 2 nd heatsink 3 via solder or the like, not shown.

The conductive portion 71, the insulating portion 72, and the thermally conductive portion 73 of the thermally conductive insulating substrate 7 are all made of a material having high thermal conductivity, and the thermal conductivity is improved as a whole, while the conductive portion 71 and the thermally conductive portion 73 are electrically independent from each other through the insulating portion 72. The semiconductor module S2 is configured such that the semiconductor device 2 is electrically independent from and thermally connected to the 1 st heatsink 1 and the 2 nd heatsink 3 through the heat-transfer insulating substrate 7. In other words, the semiconductor module S2 of the present embodiment can also be said to have a structure in which the 1 st heat dissipation member includes the 1 st heat sink 1 and the heat transfer insulating substrate 7, the 2 nd heat dissipation member includes the 2 nd heat sink 3 and the heat transfer insulating substrate 7, and the heat transfer insulating substrate 7 side is connected to the semiconductor device 2.

The heat-transfer insulating substrate 7, for example, the conductive portion 71 is mainly made of a metal material such as Cu, and the insulating portion 72 is mainly made of Al₂O₃The heat conduction portion 73 is mainly made of a metal material such as Cu. As the heat transfer insulating substrate 7, for example, a DBC (Direct Bonded coater) substrate is used.

A part of the conductive portion 71 of the heat transfer insulating substrate 7 is used as a wiring connected to an external power supply or the like, or is connected to another wiring such as the lead frame 4, and can electrically exchange with the semiconductor element 20.

In this embodiment, since heat radiation block 102 and wire 103 are unnecessary structures, the same effects as those of embodiment 1 can be obtained.

Further, the semiconductor module S2 is constructed as follows: the semiconductor device 2 and the heat sinks 1 and 3 are insulated by the heat transfer insulating substrate 7, and when connected to an external cooler or the like, it is not necessary to separately sandwich an insulating layer between the cooler or the like and the semiconductor module S2. Therefore, the semiconductor module S2 can be expected to have an effect of improving reliability when connected to an external cooler or the like.

(embodiment 3)

The semiconductor module S3 according to embodiment 3 will be described with reference to fig. 8 to 10.

As shown in fig. 8, the semiconductor module S3 of the present embodiment is different from the above-described embodiment 1 in that the semiconductor device 2 includes two semiconductor elements 20 and a relay member 29, and includes heat sinks 8 and 9 in addition to the heat sinks 1 and 3. In the present embodiment, the difference will be mainly described.

The semiconductor device 2 has 2 parts (hereinafter, referred to as an "element part" for convenience) in the present embodiment, and the element part includes a semiconductor element 20 having various electrodes and a 1 st wiring 26 and a 2 nd wiring 27 formed thereon. The semiconductor device 2 further includes a relay member 29 penetrating in the thickness direction between the two element portions.

In the following description, in order to distinguish the two semiconductor elements 20 from each other and to facilitate understanding, as shown in fig. 8, the semiconductor element 20 connected to the heat sinks 1 and 3 is referred to as a "1 st semiconductor element 201" and the other is referred to as a "2 nd semiconductor element 202" for convenience. In this embodiment, an example in which the semiconductor elements 201 and 202 have the same structure will be described.

As shown in fig. 9, for example, the 1 st semiconductor element 201 and the 2 nd semiconductor element 202 are each formed with a 1 st wiring 26 and a plurality of 2 nd wirings 27, and both element portions are arranged so as to be aligned with each other. The cross-sectional structure between II and II shown by the one-dot chain line in fig. 9 and the connection with the heat sinks 1 and 3 are the same as those of the semiconductor device 2 according to embodiment 1.

The relay member 29 includes, for example, as shown in fig. 8, a 1 st member 29a and a 2 nd member 29b, and is a member that electrically connects the heat sink and a member different from the heat sink in the thickness direction of the semiconductor device 2. The relay member 29 is made of a metal material such as Cu, and is formed by plating or the like. Specifically, for example, Cu pillars are disposed as the 2 nd members 29b between the two separated semiconductor elements 201 and 202, and these are covered with the sealing material 21. In the example shown in fig. 8, the 2 nd member 29b has the same dimension in the thickness direction as the semiconductor elements 201 and 202 on which the 1 st electrode 22 is formed, and is exposed together with the surface of the semiconductor elements 201 and 202 on the side on which the 1 st electrode 22 is formed after being covered with the sealing member 21. Then, when the rewiring layer 24 is formed, the 1 st member 29a as the remaining portion is extended over the Cu pillar in the same manner as the rewiring layer 24, whereby the relay member 29 can be formed. The posts covered with the sealing member 21 may be made of a material having conductivity, and may be other than Cu. The relay member 29 is used to connect the 1 st heatsink 1 and the 4 th heatsink 9, for example, as shown in fig. 8, and serves as a current path between the two semiconductor elements 20. In the example shown in fig. 8, the relay member 29 is disposed in a portion of the semiconductor device 2 exposed from the 2 nd heat sink 3 and located inside the outer contour of the 1 st heat sink 1. An example of the planar layout of the relay member 29 will be described later.

As shown in fig. 8, the 3 rd heatsink 8 has a plate shape having an upper surface 8a and a lower surface 8b in a front-back relationship, and is made of a metal material such as Cu, as in the 1 st heatsink 1. The 3 rd heatsink 8 mounts the element portion including the 2 nd semiconductor element 202 in the semiconductor device 2 on the upper surface 8a via the bonding material 5, and the lower surface 8b is exposed from the sealing material 6. The 3 rd heatsink 8 is disposed at a predetermined or more distance from the 1 st heatsink 1 so as not to be directly connected to the 1 st heatsink 1, i.e., not to be short-circuited. That is, the 3 rd heatsink 8 faces the rear surface 2b of the semiconductor device 2 facing the 1 st heatsink 1 and is disposed with the 1 st heatsink 1 interposed by the sealing member 6. The 3 rd heatsink 8 may also be referred to as a "3 rd heat dissipation member".

As shown in fig. 8, the 4 th heatsink 9 has a plate shape having one surface 9a and the other surface 9b in a surface-to-back relationship, and is made of a metal material such as Cu, as in the 2 nd heatsink 3. The second surface 9b of the 4 th heatsink 9 faces the element portion including the 2 nd semiconductor element 202 in the semiconductor device 2, and is electrically connected to the 2 nd semiconductor element 202 via the bonding material 5. One surface 9a of the 4 th heatsink 9 is exposed from the sealing member 6. The 4 th heatsink 9 is disposed at a predetermined interval or more from the 2 nd heatsink 3 in order to prevent direct connection with the 2 nd heatsink 3 and short circuit. That is, the 4 th heatsink 9 faces the surface 2a of the semiconductor device 2 facing the 2 nd heatsink 3 and is disposed with the 2 nd heatsink 3 interposed by the sealing member 6. In addition, the 4 th heatsink 9 may be referred to as a "4 th heat dissipation member".

In the semiconductor device 2, the element portion including the 2 nd semiconductor element 202 is arranged inside the outer contour of the upper surface 8a of the 3 rd heat sink 8. One end of the 2 nd wire 27 in this element portion is arranged outside the outer contour of the other surface 9b of the 4 th heatsink 9, and is soldered to the lead frame 4 in the other cross section of fig. 8, as in the above-described embodiment 1.

That is, the semiconductor module S3 of the present embodiment includes two element portions having a double-sided heat dissipation structure in the sealing material 6, and these are electrically connected in series via the relay member 29. Such a semiconductor module S3 may be referred to as a "2 in1 structure".

Next, an example of a planar layout of the 4 heat sinks 1, 3, 8, and 9 and the relay member 29 will be described with reference to fig. 10.

For example, as shown in fig. 10, the semiconductor module S3 has a structure in which the semiconductor device 2 including two semiconductor elements 20 is disposed between the heat sinks 1 and 3 disposed to face each other and the heat sinks 8 and 9 disposed to face each other. The semiconductor module S3 further includes a 5 th heatsink 10 disposed between the 1 st heatsink 1 and the 3 rd heatsink 8 and electrically connected to the 2 nd heatsink 3 via the relay member 29.

In such a configuration, the semiconductor device 2 includes two relay members 291 and 292. For example, as shown in fig. 10, the 1 st relay member 291 is disposed in a portion where the 1 st heatsink 1 and the 4 th heatsink 9 overlap each other when viewed in a normal direction to the one surface 3a, and is connected to each heatsink via the joining member 5. The 2 nd relay member 292 is disposed in a portion where the 2 nd heat sink 3 and the 5 th heat sink 10 overlap each other when viewed in a normal direction to the one surface 3a, and is connected to each heat sink via the joining member 5. The semiconductor module S3 having such a layout has a configuration in which the current value is appropriately changed by controlling the on/off of each of the two semiconductor elements 20.

As shown in fig. 10, the plurality of lead frames 4 are connected to the 2 nd wiring 27, not shown, formed in the two element portions outside the outer contours of the 2 nd heat sink 3 and the 4 th heat sink 9. Therefore, in the 2in1 structure as in the present embodiment, heat radiation block 102 and wire 103 are not required, and the thickness and the heat resistance are reduced compared to the conventional one.

According to the present embodiment, the same effects as those of the above embodiment 1 can be obtained.

(modification of embodiment 3)

A semiconductor module S4 as a modification of embodiment 3 will be described with reference to fig. 11. As shown in fig. 11, the semiconductor module S4 is different from the above-described embodiment 3 in that the cross-sectional shape of the relay member 29 is changed.

In the present modification, the relay member 29 has a shape having at least 1 step portion in cross section. As shown in fig. 11, the relay member 29 has a shape in which the 2 nd member 29b has a step portion, and the 1 st member 29a is extended with a positional shift, so that a portion exposed from the front surface 2a of the semiconductor device 2 and a portion exposed from the back surface 2b of the semiconductor device 2 are offset (offset). The relay member 29 is basically formed by the method described in the above embodiment 3. For example, first, a part of the Cu pillar having a step portion as the 2 nd member 29b is covered with the sealing member 21. In this case, the 2 nd member 29b is exposed from the sealing material 21 together with the surface of the semiconductor elements 201 and 202 on the side where the 1 st electrode 22 is formed, as in the above-described embodiment 3. Then, in a plan view, the 1 st member 29a is extended in the thickness direction by the same method as the rewiring layer 24 at a position offset from the portion of the Cu pillar exposed from the back surface 2 b. Thus, the relay member 29 has a stepped portion, and the portion exposed from the front surface 2a and the portion exposed from the rear surface 2b are offset. In the present modification, the column covered with the sealing member 21 may be a columnar shape or a shape having a stepped portion (for example, an L-shape in cross section), and may be any shape. In the former case, the relay member 29 is formed by forming a portion extending from the outer contour of the post in a plan view, and then extending the remaining portion in the thickness direction at the extended portion. In the latter case, the relay member 29 is formed by extending the remaining portion in the thickness direction at a position offset from the portion exposed on the surface of the pillar on the side where the rewiring layer 24 is formed, that is, the back surface side of the sealing member 21. In the above method, the relay member 29 formed so that the portion exposed from the front surface 2a and the portion exposed from the back surface 2b of the semiconductor device 2 are offset from each other has a cross-sectional shape having at least 1 step. This makes it possible to achieve not only a reduction in thickness but also a reduction in planar dimensions.

Specifically, when the cross-sectional shape of the relay member 29 is rectangular as in embodiment 3 described above, the 1 st heat sink 1 needs to have a larger width than the 2 nd heat sink 3 in order to prevent the relay member 29 from being short-circuited with the 2 nd heat sink 3. As shown in fig. 11, the interval between the 1 st heatsink 1 and the 3 rd heatsink 8 and the interval between the 2 nd heatsink 3 and the 4 th heatsink 9 need to be X equal to or greater than a predetermined value in order to prevent short circuits therebetween. In view of this, in embodiment 3, the width of the 1 st heatsink 1 is set to a size obtained by adding the space for connecting the relay member 29 to the 2 nd heatsink 3 in addition to at least the interval X from the 4 th heatsink 9.

In contrast, in the present modification, the relay member 29 is bent in the semiconductor device 2, and the portion connected to the 4 th heatsink 9 is offset from the portion connected to the 1 st heatsink 1. As a result, as shown in fig. 11, even if one end side of the relay member 29 is connected to the portion of the 1 st heat sink 1 that protrudes by the X width from the 2 nd heat sink 3, the other end side that is offset from the one end side can be connected to the 4 th heat sink 9.

Therefore, in the present modification, the 1 st heatsink 1 can have a smaller width dimension than that of the 3 rd embodiment. The 4 th heatsink 9 connected to the other end side of the relay member 29 does not need to be increased in width more than the 3 rd heatsink 8 for the same reason, and can be made smaller than that of the above-described embodiment 3. Thus, the semiconductor module S4 has a smaller planar size than that of embodiment 3 by reducing the width of the 1 st heatsink 1 and the 4 th heatsink 9.

According to this modification, in addition to the same effects as those of embodiment 3 described above, the semiconductor module S4 is also provided which has the effect of being able to be reduced in size in plan view.

(embodiment 4)

The semiconductor module according to embodiment 4 will be described with reference to fig. 12 and 13.

In fig. 12, in order to make it easy to observe a stress relaxation portion 42 of a lead frame 4 described later, a part of a semiconductor device 2, a part of a 2 nd heatsink 3, and a component other than the lead frame 4 among the components of the semiconductor module according to the present embodiment are omitted. In fig. 12, for the sake of convenience of explanation, the direction along the left-right direction of the drawing sheet is referred to as the X direction, the direction orthogonal to the plane of the drawing sheet is referred to as the Y direction, and the direction orthogonal to the X direction in the plane of the drawing sheet is referred to as the Z direction. This is also the same with respect to fig. 16 described later.

In fig. 13, for the same reason as in fig. 12, a part of the semiconductor device 2, and components other than the lead frame 4 and the bonding material 5 are omitted, and directions of X, Y, Z shown in fig. 12 are indicated by arrows or the like. This is also the same with respect to fig. 14, 15, and 17 described later.

The semiconductor module of the present embodiment is different from the above-described embodiment 1 in that, for example, as shown in fig. 12, the lead frame 4 connected to the 2 nd wiring 27 of the semiconductor device 2 via the bonding material 5 includes a stress relaxing portion 42. In the present embodiment, the difference will be mainly described.

Hereinafter, for the sake of convenience of explanation, as shown in fig. 12, the end portion of the lead frame 4 on the side connected to the 2 nd wire 27 is referred to as "1 st end portion 4 a", and the end portion on the opposite side is referred to as "2 nd end portion 4 b". Further, a direction along the lead frame 4 from the 1 st end portion 4a toward the 2 nd end portion 4b is referred to as an "extending direction".

In the present embodiment, the lead frame 4 includes the stress relaxing portion 42, and the stress relaxing portion 42 relaxes the stress generated on the 1 st end portion 4a side of the lead frame 4 in the manufacturing process, and reduces the load applied to the bonding material 5 connecting the 2 nd wire 27 and the lead frame 4. Specifically, in the step of manufacturing the semiconductor module, in the cooling step after the lead frame 4 is connected to the 2 nd wiring 27 via the bonding material 5, stress is generated in the 1 st end portion 4a due to thermal shrinkage of the lead frame 4, and a load acts on the bonding material 5 due to the stress. Since this load causes the joint 5 to crack, it is preferable to reduce the stress generated on the 1 st end 4a side from the viewpoint of securing the joint reliability. That is, the stress is concentrated on the stress relaxing portion 42, and the stress and the load on the joint 5 are reduced by elastically or plastically deforming the portion, thereby preventing the joint 5 from cracking.

As shown in fig. 12, for example, the lead frame 4 has a shape having a boundary portion 41, which is a boundary portion where the extending direction changes between the 1 st end portion 4a and the 2 nd end portion 4 b. Specifically, the lead frame 4 may be formed into, for example, the following shape: a portion including the 1 st end portion 4a and a portion including the 2 nd end portion 4b are along the X direction, and a portion therebetween is along the Z direction. In this case, the extending direction of the lead frame 4 is changed from the X direction to the Z direction, and the boundary thereof is the boundary portion 41.

Further, a portion between the 1 st end portion 4a of the lead frame 4 and the boundary portion 41 is formed as a stress relaxation portion 42 extending in a direction different from the other portion. Specifically, as shown in fig. 13, for example, the lead frame 4 is formed as a stress relaxation portion 42 in which the extending direction of a predetermined portion including the 1 st end portion 4a changes to the Y direction side along the X direction and in the middle of reaching the boundary portion 41. In other words, in the present embodiment, the stress relaxing portion 42 is provided, so that the portion from the 1 st end portion 4a to the boundary portion 41 has a substantially L-shape. In addition, the lead frame 4 has a planar shape in which a portion from the 1 st end 4a to the boundary 41 and a portion from the 2 nd end 4b to the boundary 41 are not arranged in the same straight line in a plan view. That is, the lead frame 4 has a shape different from a straight line from the 1 st end 4a to the boundary 41.

When the portion from the 1 st end 4a to the boundary 41 is linear, the lead frame 4 is thermally contracted in the extending direction in the cooling step after the lead frame 4 is connected to the semiconductor device 2 by the bonding material 5, and stress indicated by an open arrow in fig. 14 is generated. If the thermal stress is large, the bonding material 5 may crack, and the reliability of the semiconductor module may be lowered. The stress relaxation portion 42 acts to relax the thermal stress acting on the joint 5 by changing the extending direction of the portion from the 1 st end portion 4a to the boundary portion 41. The stress relaxing section 42 is formed by, for example, pressing a plate material made of a metal material.

According to the present embodiment, the semiconductor module has the following effects: in addition to the effects of embodiment 1 described above, the occurrence of cracks in the bonding material 5 connecting the 2 nd wiring 27 of the semiconductor device 2 and the lead frame 4 can be suppressed, and the reliability can be improved.

(modification of embodiment 4)

The stress relaxing portion 42 may be a structure capable of relaxing the stress generated on the 1 st end portion 4a side, and is not limited to the above example. The stress relaxing portion 42 may have a substantially U-shape in the XY plane in plan view, as shown in fig. 15, for example.

The stress relaxing section 42 may have a substantially U-shape deformed in the Z direction in cross section as shown in fig. 16, for example. In this case, as shown in fig. 17, for example, the lead frame 4 has a structure in which a portion from the 1 st end 4a to the boundary portion 41 and a portion from the 2 nd end 4b to the boundary portion 41 are located on the same straight line in a plan view. However, since the extending direction of the lead frame 4 changes from the boundary portion 41 to the 1 st end portion 4a by the stress relaxing portion 42, the thermal stress generated at the 1 st end portion 4a in the cooling step after the connection with the semiconductor device 2 is reduced.

In addition, the stress relaxing portion 42 is preferably formed to be flush with the portion from the 1 st end portion 4a to the boundary portion 41 from the viewpoint of machining accuracy. In order to concentrate stress on the stress relaxation portion 42 and elastically or plastically deform the portion, as described above, the stress relaxation portion 42 may have the following shape: not only the direction of the lead frame 4 in the extending direction but also the width and thickness are locally different from those of other portions. In other words, the stress relaxing portion 42 is a portion where at least 1 of the thickness, width, and extending direction of the lead frame 4 is different from the other portions between the 1 st end portion 4a and the boundary portion 41. The width of the lead frame 4 described here is a dimension in a direction perpendicular to the extending direction.

The same effects as those of embodiment 4 can be obtained by this modification as well.

(embodiment 5)

The semiconductor module according to embodiment 5 will be described with reference to fig. 18 to 20.

In fig. 18, the sealing material 6 is omitted and the outer contour thereof is indicated by a two-dot chain line in order to facilitate the observation of a recess 31 formed in the 2 nd heatsink 3, which will be described later.

The semiconductor module of the present embodiment is different from the above-described embodiment 1 in that a concave portion 31 is formed on the other surface 3b of the 2 nd heatsink 3 connected to the 1 st wiring 26 of the semiconductor device 2, as shown in fig. 18, for example. In the present embodiment, the difference will be mainly described.

In the present embodiment, the 2 nd heatsink 3 has the following shape: a recess 31 that is recessed toward the one surface 3a is formed in a region of the other surface 3b that is different from the region joined to the 1 st wiring 26 of the semiconductor device 2, and a gap between the semiconductor device 2 and the 2 nd heatsink 3 can be secured. Specifically, as shown in fig. 19, the second surface 3b of the 2 nd heatsink 3 includes a bonding region 3ba bonded to the semiconductor device 2 and a non-bonding region 3bb, which is a region closer to the outer contour of the second surface 3b than the bonding region 3ba, and at least a part of the non-bonding region 3bb is a recess 31.

The recess 31 is tapered such that, for example, a part of the non-joining region 3bb, which is located near the joining region 3ba, is the joining vicinity region 3bc, and is inclined from an end of the joining vicinity region 3bc toward the outer contour of the other surface 3 b. The recess 31 can be formed by any processing method such as punching, cutting, casting, or etching. As shown in fig. 20, for example, the surface of the recess 31 is an inclined surface, and an acute angle of an angle formed by the surface of the bonding region 3ba and the inclined surface is a taper angle θ, and the taper angle θ is preferably 45 ° or less. This is to secure a region of the 2 nd heat sink 3 for diffusing heat transferred from the semiconductor device 2 to the outside, and to prevent a decrease in heat radiation performance of the semiconductor device 2.

The recess 31 has the following shape: the gap D2 between the outer contour of the other surface 3b in the non-bonding region 3bb and the semiconductor device 2 is larger than the gap D1 between the bonding vicinity region 3bc and the semiconductor device 2. This is to facilitate the flow of the sealing material into the gap between the semiconductor device 2 and the 2 nd heatsink 3 during the formation of the sealing material 6, thereby ensuring the filling property of the sealing material.

For example, when the other surface 3b is a flat surface as a whole, if the thickness of the bonding material 5 is 100 μm or less and a sealing material containing a filler is flowed, the filler is less likely to enter the gap between the semiconductor device 2 and the 2 nd heat sink 3, and a void may be generated. If such a void is formed in the sealing material 6, when the cycle of heat generation and cooling of the semiconductor module is repeated, the action of alleviating the thermal stress of the bonding material 5 becomes weak, and there is a possibility that a crack is generated, which is not preferable from the viewpoint of securing reliability.

In contrast, in the present embodiment, the 2 nd heat sink 3 includes the concave portion 31 on the other surface 3b, and the gap between the semiconductor device 2 and the 2 nd heat sink 3 is widened from the junction vicinity region 3bc toward the outside. Therefore, even when the thickness of the bonding material 5 is small and a sealing material containing a filler is used, the sealing material easily flows into the gap between the semiconductor device 2 and the 2 nd heat sink 3, so that the filling property is improved and the generation of the air holes in the sealing member 6 is suppressed.

According to the present embodiment, the semiconductor module has the following effects: in addition to the effects of embodiment 1 described above, the filling property of the sealing material 6 in the gap between the semiconductor device 2 and the 2 nd heat sink 3 is further improved, the occurrence of voids in the sealing material 6 is suppressed, and the reliability is further improved.

(modification of embodiment 5)

The recess 31 of the 2 nd heat sink 3 is not limited to the above-described tapered shape, as long as the resin material constituting the sealing member 6 is filled in the gap between the semiconductor device 2 and the 2 nd heat sink 3 when the sealing member 6 is formed. The recess 31 may have a stepped shape as shown in fig. 21, for example. In this case, the gap between the semiconductor device 2 and the non-bonding region 3bb of the other surface 3b of the 2 nd heat sink 3 is also larger at the outer edge portion of the other surface 3b than at the bonding vicinity region 3 bc. Therefore, the filling property of the sealing member in the gap between the semiconductor device 2 and the 2 nd heatsink 3 can be ensured.

The same effects as those of the above-described embodiment 5 can be obtained by this modification as well.

(embodiment 6)

The semiconductor module according to embodiment 6 will be described with reference to fig. 22.

The semiconductor module of the present embodiment is different from the above-described embodiment 1 in that, for example, as shown in fig. 22, a part of the 1 st wiring 26 and the 2 nd wiring 27 in the semiconductor device 2 is roughened to be roughened portions 261 and 271. In the present embodiment, the difference will be mainly described.

In the present embodiment, as shown in fig. 22, the portion of the 1 st wiring 26 exposed from the insulating layer 25 constituting the rewiring layer 24 is roughened to be a roughened portion 261. In the present embodiment, the portion of the 2 nd wiring 27 covered with the insulating layer 25 and the portion exposed from the insulating layer 25 are roughened to be the roughened portion 271. The roughened portions 261 and 271 can be formed by any method such as a roughened plating method described in, for example, japanese patent application laid-open No. 2019-181710, or a method in which after wiring is formed in a normal plating forming step, roughening is performed by a post-treatment step such as laser irradiation.

The roughened portions 261 and 271 serve to increase the specific surface area at the interface with the bonding material 5 and the insulating layer 25, improve the adhesion with the material in contact therewith, and improve the reliability of the semiconductor module, as compared with the case where the roughening is not provided.

The term "roughened portion" as used herein means, for example, a calculated average surface roughness Ra (unit: μm) set by Japanese Industrial Standards (JIS) of 0.3 or more.

According to the present embodiment, the semiconductor module has the following effects: in addition to the effects of embodiment 1 described above, the adhesion of the 2 nd wiring 27 in the rewiring layer 24 of the semiconductor device 2 and the adhesion of the wirings 26 and 27 to the bonding material 5 are improved, and the bonding reliability is further improved.

(7 th embodiment)

The semiconductor module according to embodiment 7 will be described with reference to fig. 23.

In fig. 23, in order to make it easy to observe a cap layer 43 of a lead frame 4 described later, a part of a semiconductor device 2, a part of a 2 nd heatsink 3, and a component other than the lead frame 4 are omitted from the components of the semiconductor module of the present embodiment.

The semiconductor module of the present embodiment is different from the above embodiment 1 in that the cap layer 43 is provided on the lead frame 4. In the present embodiment, the difference will be mainly described.

In the present embodiment, the lead frame 4 includes a cap layer 43, and the cap layer 43 covers a part of the region on the 1 st end 4a side, that is, a predetermined region including a portion connected to the 2 nd wiring 27. The cap layer 43 is formed to prevent the bonding member 5, which is melted when the lead frame 4 is connected to the 2 nd wiring 27 by the bonding member 5, from protruding to an undesired region such as the 2 nd heatsink 3 side, and the lead frame 4 from being short-circuited to the undesired region. For example, when the bonding material 5 is applied to the semiconductor device 2 and the melted bonding material 5 protrudes to the 2 nd heat sink 3 side, the protruding bonding material 5 may directly connect the 2 nd heat sink 3 and the lead frame 4 to cause a short circuit. The cap layer 43 is formed to suppress the wetting diffusion of the bonding material 5 to an undesired region.

Specifically, the cover layer 43 is made of any material having higher wettability of the bonding material 5 than the lead frame 4, and functions to control the wetting and spreading direction of the melted bonding material 5. For example, when the lead frame 4 is made of Cu and the bonding material 5 is solder, the cap layer 43 is made of, for example, Au (gold), Ag (silver), Sn (tin), or an alloy thereof. The cap layer 43 is formed by any method such as evaporation or sputtering.

Assuming that the portion of the 2 nd wiring 27 exposed from the insulating layer is an exposed portion, and the portion of the lead frame 4 facing the exposed portion of the 2 nd wiring 27 is an opposing portion, the cap layer 43 continuously covers a predetermined region from the opposing portion to the 2 nd end portion 4b side. Thus, when the melted joining member 5 comes into contact with the cover layer 43, the joining member 5 wetly spreads toward the 2 nd end 4b side along the cover layer 43, and thus, the protrusion toward the 2 nd heat sink 3 side is suppressed.

According to the present embodiment, the semiconductor module has the following effects: in addition to the effects of embodiment 1, the flow of the joint 5 in an undesired direction can be prevented during the manufacturing process, and insulation failure can be suppressed.

In the above description, the manufacturing process of applying the bonding material 5 to the semiconductor device 2 and then connecting the lead frame 4 having the cap layer 43 is described as an example. However, the present invention is not limited to this manufacturing process, and the bonding material 5 may be applied to the back surface 2b of the semiconductor device 2 and the 1 st and 2 nd wirings 26 and 27 in advance, and the lead frame 4 provided with the cap layer 43 may be connected to the semiconductor device 2. In this case, the semiconductor device 2 can be bonded together with the 1 st heatsink 1, the 2 nd heatsink 3, and the lead frame 4, and the manufacturing process can be simplified.

The lead frame 4 may have a structure that can suppress the wetting diffusion of the bonding material 5, and may not have the cap layer 43. For example, the lead frame 4 may be formed without forming the cap layer 43, and the wettability of the region other than the region corresponding to the cap layer 43 may be lower than that of the other region, thereby suppressing the wetting and spreading of the bonding material 5. Examples of a method for locally deteriorating the wettability of the bonding material 5 on the lead frame 4 include laser irradiation and the like. That is, the lead frame 4 may have a structure in which a region with relatively high wettability of the bonding material 5 and a region with relatively low wettability of the bonding material 5 are provided, and the region with relatively high wettability of the bonding material 5 extends from the 1 st end 4a to the 2 nd end 4b side. This is the same in the modification described below.

(modification of embodiment 7)

As shown in fig. 24, for example, the lead frame 4 may have a groove 44 formed in a portion on the 2 nd end 4b side of the facing portion facing the 2 nd wiring 27 and spaced apart from the facing portion by a predetermined distance. In this case, the cap layer 43 is formed to cover at least the region from the opposing portion to the groove portion 44 in the lead frame 4.

As shown in fig. 24, for example, the groove portion 44 functions to absorb an excess amount of the bonding material 5 when the excess amount is applied to the 2 nd wiring 27, and to prevent the bonding material 5 from flowing into an undesired region. The groove portion 44 is formed into a substantially V-shaped groove by any processing method such as V-groove processing or half etching, but may have any shape, depth, or the like as long as an excessive amount of the joining material 5 can flow into the groove portion. The groove 44 is formed in a region of a predetermined range from the facing portion on the 1 st end 4a side of the boundary portion 41, for example, because it is difficult to absorb an excessive amount of the joining material 5 if it is too far away from the facing portion.

According to this modification, even when an excess bonding material 5 is applied to semiconductor device 2, the excess amount can be absorbed by groove portions 44, and bonding material 5 can be prevented from protruding into an undesired region, and the semiconductor module having the structure in which the effect of embodiment 7 is further improved can be obtained.

(embodiment 8)

A semiconductor module according to embodiment 8 will be described with reference to fig. 25 to 27.

In fig. 25, a part of the 1 st heatsink 1 and the sealing material 6 are omitted for easy observation of the protrusion 2c described later.

The semiconductor module of the present embodiment is different from the above-described embodiment 1, for example, in that a protrusion 2c is formed in the semiconductor device 2, and the semiconductor device 2 and the 2 nd heatsink 3 do not contact each other at an undesired portion, as shown in fig. 25. In the present embodiment, the difference will be mainly described.

In the semiconductor device 2 of the present embodiment, as shown in fig. 26, for example, a plurality of protrusions 2c are formed in the region near the outer contour of the surface 2a on the 1 st wiring 26 side. This is to prevent the filling failure of the sealing material 6 due to the surface 2a of the semiconductor device 2 and the end of the other surface 3b of the 2 nd heatsink 3 coming into contact over a wide range and blocking the gap therebetween when the end of the semiconductor device 2 is warped toward the 2 nd heatsink 3 side in the manufacturing process.

That is, the protrusion 2c is formed near the outer contour of the semiconductor device 2 where the fluctuation due to the warpage is large, and is a portion that comes into contact with the other surface 3b of the 2 nd heatsink 3 prior to the front surface 2a of the semiconductor device 2 when the semiconductor device 2 is warped. Thereby, the protrusion 2c functions as follows: gaps between the semiconductor device 2 and the 2 nd heat sink 3 are ensured, and the sealing material is assisted to flow into these gaps, preventing the generation of air holes in the sealing member 6.

The protrusion 2c is made of any material such as a resin material or a metal material. When the protrusion 2c is made of a resin material, it can be formed by any wet film forming method such as potting. When the protrusion 2c is made of a metal material, it can be formed by any method such as plating. In the latter case, the projection 2c is electrically independent from a circuit portion of the semiconductor device 2 that transmits an electrical signal such as a high-frequency signal.

The projection 2c may be in contact with only the 2 nd heat sink 3, or may be joined to the 2 nd heat sink 3. For example, the projection 2c may be joined to the 2 nd heatsink 3 in a structure including solder, and in this case, a structure of soldering may be provided on the semiconductor device 2 side. This can also expect an effect of further improving the heat dissipation of the semiconductor device 2.

The protruding portion 2c is, for example, columnar, and as shown in fig. 26, a plurality of protruding portions are arranged in a region where the semiconductor device 2 has a large warpage and can be brought into contact with the 2 nd heatsink 3. Specifically, a region facing the second surface 3b of the 2 nd heatsink 3 in a predetermined region near the outer contour of the front surface 2a of the semiconductor device 2 is defined as an outer edge region 2aa, and the protrusion 2c is formed in the outer edge region 2 aa. The protrusions 2c are scattered in an outer edge region 2aa outside the 1 st wiring 26, for example, and are arranged so as to surround the 1 st wiring 26.

The projection 2c is not limited to the above arrangement and shape as long as it prevents the surface 2a of the semiconductor device 2 from contacting the second surface 3b of the 2 nd heatsink 3 due to the warp of the semiconductor device 2 and does not obstruct the inflow of the sealing member. For example, the projection 2c may have a wall shape as shown in fig. 27, or may have any other shape, and the arrangement may be changed as appropriate in the outer edge region 2 aa.

According to the present embodiment, the semiconductor module has the following effects: in addition to the effects of embodiment 1 described above, even if warpage of the semiconductor device 2 occurs during the manufacturing process, the gap between the semiconductor device 2 and the 2 nd heatsink 3 is secured, and the occurrence of voids in the sealing member 6 is suppressed, thereby further improving reliability.

(other embodiments)

The invention has been described in terms of embodiments, but it is to be understood that the invention is not limited to the embodiments and constructions. The present invention also includes various modifications and modifications within the equivalent scope. In addition, various combinations and forms, and further, combinations and forms including only one of the elements and combinations and forms including more than one of the elements or less than one of the elements also fall within the scope and spirit of the present invention.

(1) For example, in embodiment 3 and its modified example, the heat transfer insulating substrate 7 may be disposed between the semiconductor device 2 and the heat sinks 1, 3, 8, and 9 as shown in fig. 28. In this case, the relay member 29 is electrically connected to the conductive portion 71 of the heat transfer insulating substrate 7, and is electrically independent from but thermally connected to the heat sinks 1, 3, 8, and 9.

(2) In embodiment 3 and its modified examples, the 2in1 structure in which two element portions are covered with 1 sealing material 6 has been described, but the number of element portions may be 3 or more. In this case, the semiconductor module can be made thinner and have a lower thermal resistance than conventional semiconductor modules.

(3) In the above embodiments, the 1 st wiring 26 and the 2 nd wiring 27 of the semiconductor device 2 have been described as having a shape protruding outward from the outer surface of the insulating layer 25, but may have a shape recessed inward from the outer surface of the insulating layer 25 as shown in fig. 29.

(4) In embodiment 2 described above, an example is described in which the 1 st heat sink member includes the 1 st heat sink 1 and the heat transfer insulating substrate 7, and the 2 nd heat sink member includes the 2 nd heat sink 3 and the heat transfer insulating substrate 7. However, as shown in fig. 30, the 1 st heat dissipation member and the 2 nd heat dissipation member may be constituted only by the heat transfer insulating substrate 7.

Similarly, in the other modification of embodiment 3 described in (1), the 1 st to 4 th heat dissipation members may be configured only by the heat transfer insulating substrate 7 as shown in fig. 31. In this case, the semiconductor module has a structure in which the 1 st and 3 rd heat dissipation members are constituted by only 1 heat conductive insulating substrate 7, and the 2 nd and 4 th heat dissipation members are constituted by only 1 heat conductive insulating substrate 7. The heat transfer insulating substrate 7 has a structure in which a portion connected to the semiconductor element 201 and a portion connected to the semiconductor element 202 in the conductive portion 71 are electrically independent from each other, and the heat transfer portion 73 may not be patterned.

(5) In the above-described embodiments 1 and 2, the description has been given on the assumption that the semiconductor element 20 in the semiconductor device 2 has a so-called vertical structure in which a current in the thickness direction is generated, but the semiconductor element 20 is not limited to this. For example, the semiconductor element 20 may have a structure in which the 1 st electrode 22, the 2 nd electrode 23, and the 3 rd electrode are formed in the same plane.

(6) In embodiment 1 described above, the 2 nd heatsink 3 may be formed with a through-hole 32 connecting the first surface 3a and the second surface 3b at a position outside the region joined to the semiconductor device 2, as shown in fig. 32, for example. The through-hole 32 functions as a filling path for filling a resin material (hereinafter, referred to as a "sealing material") constituting the sealing member 6 between the semiconductor device 2 and the 2 nd heatsink 3 when the sealing member 6 is molded.

Specifically, as shown in fig. 33, for example, the through-hole 32 is a path into which the sealing material flows when the sealing material is injected after the work, to which the 1 st heatsink 1, the semiconductor device 2, the 2 nd heatsink 3, and the lead frame 4 are bonded, is set in the mold 310. In addition, the work is arranged such that one surface 3a of the 2 nd heatsink 3 does not contact the inner wall of the metal mold 310. As shown by the arrows in fig. 33, the sealing material flows from the one surface 3a toward the other surface 3b, and fills the gap between the semiconductor device 2 and the 2 nd heatsink 3. Further, the semiconductor module shown in fig. 32 can be manufactured by exposing the one surface 3a of the 2 nd heatsink 3 by, for example, grinding after hardening the sealing material. Thus, the semiconductor module having the structure in which the filling property of the sealing member 6 is improved is obtained as in the case of the above-described embodiment 5.

As shown in fig. 34, the through-hole 32 may be formed in the 2 nd heatsink 3 in the 5 th embodiment and the modification thereof. In this case, the through-hole 32 is formed in the recess 31 of the 2 nd heatsink 3, and functions to improve the filling property of the sealing material 6 in the gap between the semiconductor device 2 and the 2 nd heatsink 3 together with the recess 31.

Further, the through-hole 32 may be formed in the 2 nd heatsink 3 in embodiment 3 and its modified example. In this case, if a through hole corresponding to the through hole 32 is formed in the 4 th heatsink 9, the filling property of the sealing material 6 is further improved, which is preferable.

(7) When part or all of the heat dissipation members 2 and 4 are formed of the heat transfer insulating substrate 7, the heat transfer insulating substrate 7 may have a step portion 74 formed on the outer periphery of the conductive portion 71, as shown in fig. 35, for example. Thus, the sealing material 6 is easily inserted into the gap between the heat transfer insulating substrate 7 and the front surface 2a of the semiconductor device 2, and the filling property of the sealing material 6 is improved.