阅读说明：本技术 晶圆级芯片尺寸封装结构及其制造方法 (Wafer-level chip scale package structure and manufacturing method thereof ) 是由 林俊辰 于 2020-08-25 设计创作，主要内容包括：本发明提供一种晶圆级芯片尺寸封装结构及其制造方法,晶圆级芯片尺寸封装结构包括第一芯片、重布线路层、多个球底金属层、多个导电柱、第二芯片、封装胶体以及多个连接部。重布线路层位于第一芯片上且电性连接至其焊垫。球底金属层位于重布线路层上。导电柱位于一部分的球底金属层上。第二芯片位于另一部分的球底金属层上。第二芯片具有面向所述多个球底金属层的有源面。导电柱围绕第二芯片。封装胶体至少包封第二芯片与导电柱的部分侧壁。封装胶体的顶面低于导电柱的顶面。连接部位于导电柱上且通过导电柱以及球底金属层与重布线路层电性连接。连接部延伸至封装胶体的顶面。(The invention provides a wafer-level chip size packaging structure and a manufacturing method thereof. The redistribution layer is located on the first chip and electrically connected to the pad. The under bump metallurgy layer is located on the redistribution layer. The conductive post is located on a portion of the UBM layer. The second chip is located on the other part of the under-ball metal layer. The second chip has an active surface facing the plurality of under-ball-metallurgy layers. The conductive posts surround the second chip. The encapsulant encapsulates at least the second chip and a portion of the sidewalls of the conductive pillars. The top surface of the packaging colloid is lower than the top surface of the conductive post. The connecting part is positioned on the conductive column and is electrically connected with the redistribution circuit layer through the conductive column and the under ball metal layer. The connecting part extends to the top surface of the packaging colloid.)

1. A wafer level chip scale package structure, comprising:

a first chip having a plurality of pads;

a redistribution layer on the first chip and electrically connected to the pads;

a plurality of under-bump-metallurgy layers on the redistribution layer;

a plurality of conductive pillars located on a portion of the plurality of ubm layers;

a second chip located on another portion of the plurality of ubm layers and having an active surface facing the plurality of ubm layers, wherein the plurality of conductive pillars surround the second chip;

the packaging colloid at least encapsulates the second chip and partial side walls of the plurality of conductive columns, wherein the top surface of the packaging colloid is lower than the top surfaces of the plurality of conductive columns; and

and the connecting parts are positioned on the conductive posts, are electrically connected with the redistribution circuit layer through the conductive posts and the under bump metallurgy layers, and extend to the top surface of the packaging colloid.

2. The wafer-level chip scale package structure of claim 1, wherein the plurality of connections are solder in a block, hemisphere, or sphere shape.

3. The wafer-level chip scale package structure of claim 2, wherein the plurality of connecting portions cover another portion of the sidewalls of the plurality of conductive pillars.

4. A method for manufacturing a wafer-level chip scale package structure, comprising:

providing a wafer, wherein the wafer comprises a plurality of first chips, and each of the plurality of first chips is provided with a plurality of welding pads;

forming a redistribution layer on the wafer and electrically connected to the plurality of pads;

forming a plurality of under bump metallurgy layers on the redistribution layer;

forming a plurality of conductive pillars on the plurality of under bump metallurgy layers, wherein an opening is formed between two adjacent conductive pillars;

disposing a second chip in the opening, wherein the second chip has an active surface facing the plurality of under-bump-metallurgy layers and is electrically connected to the plurality of under-bump-metallurgy layers;

forming an encapsulant to encapsulate at least the second chip and a portion of the sidewalls of the conductive pillars; and

forming a plurality of connection portions on the conductive pillars, wherein the connection portions are electrically connected to the redistribution layer through the conductive pillars and the under bump metallurgy layers.

5. The method of manufacturing a wafer level chip scale package structure of claim 4, further comprising:

forming a plurality of first mask layers on the redistribution layer;

and carrying out an electroplating process to form the plurality of under-bump-metallurgy layers between the plurality of first mask layers.

6. The method of manufacturing a wafer level chip scale package structure of claim 4, further comprising:

forming a plurality of second mask layers on a part of the plurality of under bump metallurgy layers and exposing another part of the plurality of under bump metallurgy layers;

performing an electroplating process to form the conductive pillars on the exposed other portions of the under bump metallurgy layers; and

removing the plurality of second mask layers to form the opening.

7. The method as claimed in claim 4, further comprising the steps of:

and carrying out a wafer back grinding process on the wafer to thin the thickness of the wafer.

8. The method as claimed in claim 4, further comprising the steps of:

and carrying out a cutting process on the wafer to form a separated wafer-level chip size packaging structure.

9. The method of manufacturing a wafer level chip scale package structure of claim 8, wherein the step of forming the plurality of connections comprises:

forming a plurality of solder layers on the conductive posts, wherein the forming method of the plurality of solder layers comprises screen printing, electroplating or coating.

10. The method as claimed in claim 9, wherein the step of forming the solder layers on the conductive pillars further comprises:

and carrying out a reflow soldering process on the plurality of solder layers.

Technical Field

The present invention relates to a package structure and a method for manufacturing the same, and more particularly, to a wafer level chip scale package structure and a method for manufacturing the same.

Background

Wafer Level Packaging (Wafer Level Packaging) is a Packaging technology that performs chip size on an entire Wafer, i.e., most of the Packaging work is completed at the Wafer stage, so that the Wafer Level chip size Packaging can reduce the size of the package, and is also advantageous in terms of process and material costs.

Generally, there are many factors that affect the reliability of wafer level chip scale packages. For example, if the components on the wafer have poor bonding strength or are damaged in the process, the wafer-level chip scale package is adversely affected, thereby reducing the reliability of the wafer-level chip scale package. Therefore, it is a challenge for researchers in the field to reduce the adverse effect on the wafer-level chip scale package, so as to improve the reliability of the wafer-level chip scale package.

Disclosure of Invention

The invention aims at a wafer-level chip size packaging structure and a manufacturing method thereof, which can reduce the occurrence of adverse effects on the wafer-level chip size packaging structure and further improve the reliability of the wafer-level chip size packaging structure.

According to an embodiment of the present invention, a wafer level chip scale package structure includes a first chip, a redistribution layer, a plurality of ubm layers, a plurality of conductive pillars, a second chip, a molding compound, and a plurality of connecting portions. The first chip has a plurality of bonding pads. The redistribution layer is located on the first chip and electrically connected to the bonding pad. The under bump metallurgy layer is located on the redistribution layer. The conductive post is located on a portion of the UBM layer. The second chip is located on the other part of the under ball metal layer, and the second chip has an active surface facing the under ball metal layer. The conductive posts surround the second chip. The encapsulant encapsulates at least the second chip and a portion of the sidewalls of the conductive pillars. The top surface of the packaging colloid is lower than the top surfaces of the plurality of conductive posts. The connecting part is positioned on the conductive column. The connecting part is electrically connected with the redistribution circuit layer through the conductive column and the under ball metal layer, and the connecting part extends to the top surface of the packaging colloid.

According to an embodiment of the invention, a method for manufacturing a wafer-level chip scale package structure includes providing a wafer. The wafer comprises a plurality of first chips, and each first chip is provided with a plurality of bonding pads. Forming a redistribution layer on the wafer and electrically connecting to the pads. Forming a plurality of under bump metallurgy layers on the redistribution layer. A plurality of conductive posts are formed on the plurality of under bump metallurgy layers, wherein two adjacent conductive posts have an opening. And arranging a second chip in the opening, wherein the second chip is provided with an active surface facing the plurality of under-ball metal layers and is electrically connected to the plurality of under-ball metal layers. An encapsulant is formed to encapsulate at least the second chip and a portion of the sidewalls of the conductive pillars. And forming a plurality of connecting parts on the conductive posts. The connecting part is electrically connected with the redistribution circuit layer through the conductive column and the under-ball metal layer.

Based on the above, the invention can reduce the occurrence of adverse effects on the wafer-level chip scale package structure (for example, the second chip and the conductive pillar on the wafer have poor bonding strength or the second chip is damaged in the process) through the configuration of the under bump metallurgy and the package colloid, thereby improving the reliability of the wafer-level chip scale package structure. On the other hand, the connecting portion can extend to the top surface of the encapsulant, so that the connecting portion can have better bonding strength to further improve the reliability of the wafer-level chip scale package structure.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to 6A and fig. 1B to 6B are a partial top view and a partial cross-sectional view of a wafer-level chip scale package structure in a different stage of the manufacturing process according to an embodiment of the invention. In these figures, a partial top view will be presented first, followed by a partial cross-sectional view along line a-a' in the partial top view. For example, fig. 1A is a partial top view of a wafer level chip scale package structure during one stage of fabrication. Fig. 1B is a partial sectional view taken along line a-a' in fig. 1A.

Fig. 6C to 6D are partial sectional views continuing to fig. 6B.

Fig. 7A to 7D are partial cross-sectional views of the forming method of fig. 3B to 4B.

Description of the reference numerals

10 first mask layer

20 second mask layer

100 wafer level chip scale package structure

110: wafer

112 first chip

1121 bonding pad

120: redistribution layer

122 conductive layer

124 dielectric layer

1241 through hole

130. 132, 134 metal layer under ball

140 conductive pole

140a, 160a top surface

140s, 140s1, 140s2 side wall

150 second chip

150a active surface

150b back side

152 conductive part

160 packaging adhesive

170 connecting part

172 solder layer

OP is an opening

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Directional phrases used herein (e.g., upper, lower, right, left, front, rear, top, bottom) are used only as referring to the drawings and are not intended to imply absolute orientation.

Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The same or similar reference numerals denote the same or similar components, and the following paragraphs will not be repeated.

Fig. 1A to 6A and fig. 1B to 6B are a partial top view and a partial cross-sectional view of a wafer-level chip scale package structure in a different stage of the manufacturing process according to an embodiment of the invention. Fig. 6C to 6D are partial sectional views continuing to fig. 6B. Fig. 7A to 7D are partial cross-sectional views of the forming method of fig. 3B to 4B.

In the present embodiment, the method for manufacturing the wafer-level chip scale package structure 100 may include the following steps.

Referring to fig. 1A and fig. 1B, a wafer 110 is provided, wherein the wafer 110 includes a plurality of first chips 112, and the first chips 112 have a plurality of bonding pads 1121. As shown in fig. 1A, a plurality of first chips 112 may be arranged in an array on the wafer 110. In an embodiment, the pad 1121 may be an aluminum pad, but the invention is not limited thereto. The pad 1121 can be any suitable conductive pad.

Referring to fig. 2A and fig. 2B, a redistribution layer 120 is formed on the wafer 110. For example, the redistribution layer 120 may be formed on the first chip 112 of the wafer 110 and electrically connected to the pad 1121. In the present embodiment, the redistribution layer 120 may include a conductive layer 122 and a dielectric layer 124. The step of forming the redistribution layer 120 may be as follows. First, a conductive material (not shown) is formed on the wafer 110. Then, a patterning process is performed on the conductive material to form a conductive layer 122, wherein the conductive layer 122 is electrically connected to the pad 1121. Then, a dielectric material (not shown) is formed on the conductive layer 122. Then, a plurality of vias 1241 are formed in the dielectric material to form the dielectric layer 124 and expose a portion of the conductive layer 122. Therefore, the component in the via 1241 can be electrically connected to the pad 1121 through the conductive layer 122.

Further, as shown in fig. 2A, the plurality of vias 1241 in the dielectric layer 124 may have different sizes. For example, the through hole 1241 near the edge of the first chip 112 may have a larger size, and the through hole 1241 near the center of the first chip 112 may have a smaller size, but the present invention is not limited thereto.

In addition, although fig. 2B only shows one conductive layer 122 and one dielectric layer 124, the number of the conductive layer 122 and the dielectric layer 124 is not limited by the invention, and may be determined according to the requirement of the actual design. In addition, the conductive layer 122 and the dielectric layer 124 may be formed by suitable materials and formation methods.

Referring to fig. 3A and fig. 3B, a plurality of ubm layers 130 are formed on the redistribution layer 120, wherein the ubm layers 130 can enhance the bonding strength of the subsequent components on the wafer 110, thereby reducing the adverse effect on the wafer-level chip scale package structure 100 due to poor bonding strength, and further enhancing the reliability of the wafer-level chip scale package structure 100.

In this embodiment, the ubm layer 130 may include a first ubm layer 132 and a second ubm layer 134, wherein the first ubm layer 132 on each first chip 112 may surround the second ubm layer 134. In other words, the first ubm layer 132 on each first chip 112 is located on both sides of the second ubm layer 134. Furthermore, different components may be disposed on the first ubm layer 132 and the second ubm layer 134 in the subsequent processes.

Referring to fig. 4A and fig. 4B, a plurality of conductive pillars 140 are formed on the plurality of ubm layers 130, wherein the conductive pillars 140 can be electrically connected to the first chip 112. For example, a plurality of conductive pillars 140 may be formed on a portion of the ubm layer 130 (e.g., the first ubm layer 132), and electrically connected to the first chip 112 through a portion of the ubm layer 130 (e.g., the first ubm layer 132) and the conductive layer 122 of the redistribution layer 120. On the other hand, an opening OP may be formed between two adjacent conductive pillars 140, for example, the opening OP may expose another portion of the ubm layer 130 (e.g., the second ubm layer 134). In other words, the conductive pillars 140 may not be formed on another portion of the ubm layer 130 (e.g., the second ubm layer 134).

Referring to fig. 5A and 5B, a second chip 150 is disposed on the ubm layer 130. For example, the second chip 150 may be disposed on another portion of the ubm layer 130 (e.g., the second ubm layer 134). Further, the second chip 150 may be disposed in the opening OP between two adjacent conductive pillars 140, so that the conductive pillars 140 may surround the second chip 150. Here, the first chip 112 and the second chip 150 may be any suitable chips, such as active or passive chips.

In the present embodiment, the second chip 150 has an active surface 150a facing the ubm layer 130. In other words, the back surface 150b of the second chip 150 opposite to the active surface 150a may be far away from the ubm layer 130. The second chip 150 may be electrically connected to the ubm layer 130 by using a flip-chip (flip-chip) method. For example, the second chip 150 may further have a plurality of conductive portions 152 located on the active surface 150a, and the plurality of conductive portions 152 are bonded to the ubm layer 130 (e.g., the second ubm layer 134). Thus, the electrical connection between the second chip 150 and the ubm layer 130 (e.g., the second ubm layer 134) can be realized.

Referring to fig. 6A and fig. 6B, the encapsulant 160 is formed to encapsulate at least the second chip 150 and a portion of the sidewalls 140s1 of the conductive pillars 140, so as to effectively protect the second chip 150, reduce the occurrence of adverse effects on the wafer-level chip-scale package structure 100 caused by the damage of the second chip 150 in the process, and further improve the reliability of the wafer-level chip-scale package structure 100. The material of the encapsulant 160 is, for example, Epoxy Molding Compound (EMC) and is formed by, for example, a mold, but the present invention is not limited thereto.

In the present embodiment, the height of the conductive pillars 140 relative to the conductive layer 122 may be higher than the height of the second chip 150 relative to the conductive layer 122 and the height of the encapsulant 160 relative to the conductive layer 122. Further, the conductive posts 140, the encapsulant 160, and the second chip 150 are sequentially disposed from high to low relative to the conductive layer 122. In other words, the back surface 150b of the second chip 150 may be lower than the top surface 160a of the encapsulant 160, and the top surface 160a of the encapsulant 160 may be lower than the top surfaces 140a of the conductive pillars 140, so as to expose another portion of the sidewalls 140s2 of the conductive pillars 140. However, the invention is not limited thereto, and in an embodiment not shown, the top surface 160a of the encapsulant 160 may be substantially coplanar with the top surfaces 140a of the conductive pillars 140. In other words, the encapsulant 160 may completely cover the sidewalls 140s2 of the conductive pillars 140. Note that, for clarity of description, the encapsulant 160 is omitted from fig. 6A.

Referring to fig. 6C and fig. 6D, after the encapsulant 160 is formed, a plurality of solder layers 172 may be formed on the conductive pillars 140. The material of the solder layer 172 is, for example, tin. The method for forming the plurality of solder layers 172 may include screen printing, electroplating or coating. Next, a reflow process may be performed on the solder layer 172 to form a connection portion 170 on the conductive pillar 140, wherein the connection portion 170 may be electrically connected to the redistribution layer 120 through the conductive pillar 140 and the ubm layer 130. In some embodiments, the connection 170 may be a solder in a block shape, a hemispherical shape, or a spherical shape. It should be noted that the connecting portion 170 of the present invention is not limited to the above-mentioned method, and may be determined according to the actual design requirement.

Further, the connection portion 170 may extend to the top surface 160a of the encapsulant 160, and the connection portions 170 may cover another portion of the sidewalls 140s2 of the conductive pillars 140, so as to relatively increase the contact area between the connection portion 170 and the conductive pillars 140, in other words, because the top surface of the conductive pillars 140 and the sidewalls 140s2 are completely covered in the connection portion 170, the connection portion 170 may have better bonding strength and larger conductive area, and meanwhile, the encapsulant 160 also seals the sidewalls 140s1 of the conductive pillars 140, so as to relatively increase the stability and structural strength of the conductive pillars 140, so as to further improve the reliability of the wafer-level chip scale package structure 100.

Thereafter, in order to further reduce the volume of the wafer-level chip scale package structure 100, a back grinding process may be optionally performed on the wafer 110 to thin the thickness of the wafer 110. The wafer 110 may then be subjected to a dicing process to form individual wafer-level chip-scale packages 100. The cutting process includes, for example, cutting with a rotating blade or a laser beam.

The fabrication of the wafer-level chip scale package structure 100 of the present embodiment can be substantially completed through the above processes. The arrangement of the ubm layer 130 and the encapsulant 160 can reduce the occurrence of adverse effects on the wafer-level chip-scale package structure 100 (e.g., the second chip 150 and the conductive pillars 140 on the wafer have poor bonding strength or the second chip 150 is damaged in the process). On the other hand, since the connection portion 170 may extend to the top surface 160a of the encapsulant 160, the connection portion 170 may have better bonding strength, further improving the reliability of the wafer-level chip-scale package structure 100.

In an embodiment, the forming method of fig. 3B to 4B may include at least the following steps. Specifically, the following description is merely exemplary in that fig. 3B to 4B may be formed by the method of fig. 7A to 7D, but the present invention is not limited thereto, and fig. 3B to 4B may be formed by a suitable method.

Referring to fig. 7A and 7B, first, a plurality of first mask layers 10 may be formed on the redistribution layer 120. The first mask layer 10 may have a plurality of openings corresponding to the vias 1241 to define the formation locations of the ubm layer 130. In the present embodiment, the first mask layer 10 may expose a portion of the dielectric layer 124 and a portion of the conductive layer 124 exposed by the via 1241. Next, an electroplating process may be performed to form the ubm layer 130 between the first mask layers 10. Thereafter, the first mask layer 10 (not shown) is removed.

Referring to fig. 7C and fig. 7D, after the ubm layer 130 is formed, the second mask layer 20 is formed on a portion of the ubm layer 130 (e.g., the second ubm layer 134) and another portion of the ubm layer 130 (e.g., the first ubm layer 132) is exposed. Next, an electroplating process is performed to form the conductive pillars 140 on the exposed other portion of the ubm layer 130 (e.g., the first ubm layer 132). Thereafter, the second mask layer 20 is removed to form an opening OP. Here, the first mask layer 10 and the second mask layer 20 may be formed by suitable materials and formation methods.

In summary, the invention can reduce the occurrence of adverse effects on the wafer-level chip scale package structure (for example, the second chip and the conductive pillar on the wafer have poor bonding strength or the second chip is damaged in the process) by the configuration of the under bump metallurgy and the encapsulant, thereby improving the reliability of the wafer-level chip scale package structure. On the other hand, the connecting portion can extend to the top surface of the encapsulant, so that the connecting portion can have better bonding strength to further improve the reliability of the wafer-level chip scale package structure.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.