阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 孟完柱 陈玄洙 姜世勋 任基彬 尹卿烈 于 2021-02-24 设计创作，主要内容包括：一种半导体器件包括：第一电极；第二电极；以及位于第一电极与第二电极之间电介质层叠层,该电介质层叠层包括第一反铁电层、第二反铁电层以及在第一反铁电层与第二反铁电层之间的铁电层。(A semiconductor device includes: a first electrode; a second electrode; and a dielectric stack between the first and second electrodes, the dielectric stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first and second anti-ferroelectric layers.)

1. A semiconductor device, comprising:

a first electrode;

a second electrode; and

a dielectric stack between the first electrode and the second electrode, the dielectric stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer disposed between the first anti-ferroelectric layer and the second anti-ferroelectric layer.

2. The semiconductor device of claim 1, wherein the first anti-ferroelectric layer, the ferroelectric layer, and the second anti-ferroelectric layer are vertically arranged between the first electrode and the second electrode.

3. The semiconductor device of claim 1, wherein the first and second antiferroelectric layers comprise the same antiferroelectric material or different antiferroelectric materials.

4. The semiconductor device of claim 1, wherein the first anti-ferroelectric layer, the second anti-ferroelectric layer, and the ferroelectric layer comprise an oxide comprising hafnium, zirconium, and oxygen.

5. The semiconductor device of claim 1, wherein the first and second antiferroelectric layers comprise antiferroelectric hafnium zirconium oxide and the ferroelectric layer comprises ferroelectric hafnium zirconium oxide.

6. The semiconductor device of claim 1, wherein the first and second antiferroelectric layers comprise hafnium zirconium oxide having a zirconium content greater than a hafnium content.

7. The semiconductor device of claim 1, wherein the ferroelectric layer comprises a hafnium zirconium oxide having a hafnium content that is the same as a zirconium content.

8. The semiconductor device of claim 1, wherein each of the first anti-ferroelectric layer, the second anti-ferroelectric layer, and the ferroelectric layer comprises hafnium zirconium oxide, and

the first and second antiferroelectric layers have a zirconium content that is at least twice the hafnium content, an

The ratio of the hafnium content to the zirconium content of the ferroelectric layer is 1: 1.

9. The semiconductor device of claim 1, wherein the first and second antiferroelectric layers comprise PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃Or NaNbO₃。

10. The semiconductor device of claim 1, wherein the ferroelectric layer comprises BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃Or BaSrTiO₃。

11. The semiconductor device of claim 1, further comprising:

an interfacial layer disposed between the dielectric laminate layer and the second electrode; and

an additional interfacial layer disposed between the first electrode and the dielectric laminate layer.

12. The semiconductor device of claim 11, wherein the interfacial layer comprises a material that is reduced prior to the dielectric stack.

13. The semiconductor device of claim 11, wherein the interface layer and the additional interface layer comprise materials that are more electronegative than the first and second antiferroelectric layers and the ferroelectric layer.

14. The semiconductor device of claim 11, wherein the interfacial layer and the additional interfacial layer comprise titanium oxide, tantalum oxide, niobium oxide, or tin oxide.

15. A semiconductor device, comprising:

a first electrode;

a second electrode; and

an alternating stack between the first electrode and the second electrode, the alternating stack comprising a plurality of dielectric layer stacks and a plurality of leakage barriers that are alternately stacked,

wherein each of the plurality of dielectric layer stacks comprises a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer.

16. The semiconductor device of claim 15, wherein the first anti-ferroelectric layer, the ferroelectric layer, and the second anti-ferroelectric layer are vertically disposed between the first electrode and the second electrode.

17. The semiconductor device of claim 15, wherein the first and second antiferroelectric layers comprise antiferroelectric hafnium zirconium oxide and the ferroelectric layer comprises ferroelectric hafnium zirconium oxide.

18. The semiconductor device of claim 15, wherein the first and second antiferroelectric layers comprise hafnium zirconium oxide having a zirconium content greater than a hafnium content.

19. The semiconductor device of claim 15, wherein the ferroelectric layer comprises a hafnium zirconium oxide having a hafnium content that is the same as a zirconium content.

20. The semiconductor device of claim 15, wherein the first and second antiferroelectric layers comprise PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃Or NaNbO₃。

21. The semiconductor device of claim 15, wherein the ferroelectric layer comprises BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃Or BaSrTiO₃。

22. The semiconductor device of claim 15, further comprising:

an interfacial layer disposed between the second electrode and the alternating stack; and

an additional interfacial layer disposed between the first electrode and the alternating stack.

23. The semiconductor device of claim 22, wherein the interfacial layer comprises a material that is reduced prior to the dielectric stack.

24. The semiconductor device of claim 22, wherein the interface layer and the additional interface layer comprise materials that are more electronegative than the first and second antiferroelectric layers and the ferroelectric layer.

25. The semiconductor device of claim 22, wherein the interfacial layer and the additional interfacial layer comprise titanium oxide, tantalum oxide, niobium oxide, or tin oxide.

26. The semiconductor device of claim 15, wherein the first electrode comprises a cylinder, pillar, or hybrid pillar shape.

27. The semiconductor device of claim 15, further comprising:

a support for supporting the first electrode.

28. The semiconductor device of claim 15, further comprising:

a semiconductor substrate including a first doped region and a second doped region;

a word line buried in the semiconductor substrate between the first doped region and the second doped region;

a bit line formed over the word line and coupled to the first doped region; and

a storage node contact plug coupled to the second doped region,

wherein the first electrode is electrically connected to the storage node contact plug.

29. The semiconductor device of claim 15, wherein the first electrode, the alternating stack, and the second electrode form a Dynamic Random Access Memory (DRAM) capacitor.

Technical Field

Various embodiments of the present invention relate generally to a semiconductor device and, more particularly, to an improved semiconductor device that includes both antiferroelectric and ferroelectric materials.

Background

In order to ensure sufficient operating characteristics with further scaling down the size of capacitors in semiconductor devices, sufficient capacitance must be maintained. One way to achieve this includes increasing the dielectric constant of the dielectric material employed in the capacitor. However, known materials compatible with semiconductor processing are limited, and thus the current limitation is to scale down the size of capacitors in semiconductor devices while maintaining effective capacitance.

Disclosure of Invention

Embodiments of the present invention are directed to a semiconductor device including a dielectric layer stack (dielectric stack) having a high dielectric constant. The semiconductor device may include a capacitor.

According to an embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; and a dielectric stack between the first electrode and the second electrode, the dielectric stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer disposed between the first anti-ferroelectric layer and the second anti-ferroelectric layer.

According to another embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; and an alternating stack between the first electrode and the second electrode, the alternating stack including a plurality of dielectric layer stacks and a plurality of leakage barriers alternately stacked, wherein each of the plurality of dielectric layer stacks includes a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer.

These and other features and advantages of the present invention will be understood by those of ordinary skill in the art from the following drawings and detailed description.

Drawings

Fig. 1 shows a semiconductor device according to an embodiment of the present invention.

Fig. 2A and 2B show polarization characteristics of the ferroelectric material and the antiferroelectric material, respectively.

Fig. 2C shows the polarization characteristics of a stack comprising both ferroelectric and antiferroelectric materials.

Fig. 3 to 8B show semiconductor devices according to other embodiments of the present invention.

Fig. 9A to 9C are views showing a memory cell.

Fig. 10A to 10F are views showing application examples of a capacitor of a memory cell.

Fig. 11 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers to not only a case where the first layer is directly formed on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.

It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. Further, the connections/couplings may not be limited to physical connections but may also include non-physical connections such as wireless connections.

In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

When a first element is referred to as being "over" a second element, it refers not only to a case where the first element is directly formed on the second element but also to a case where a third element exists between the first element and the second element.

It is to be understood that the figures are simplified schematic diagrams of the devices described and that well-known details may not be included to avoid obscuring the features of the invention.

It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the invention.

It is also noted that, in the various drawings, like reference numerals designate like elements.

Hafnium oxide (HfO)₂) With zirconium oxide (ZrO)₂) The combination of (a) may be adjusted to have ferroelectric or antiferroelectric properties. Therefore, it is desirable to control polarization switching to occur near the operating voltage of volatile memories such as Dynamic Random Access Memories (DRAMs) and to use a maximized dielectric constant in this region.

When a ferroelectric material is used, the coercive field as an operating voltage can be low, but even when the operating voltage is removed (for example, the operating voltage is 0V), the polarization does not become 0 and the remanent polarization remains. This may limit the use of ferroelectric materials for DRAMs.

When an antiferroelectric material is used, since the coercive field in which polarization switching occurs is relatively large, it is necessary to lower the coercive field in order to use a DRAM.

The dielectric material of the capacitor of the DRAM according to an embodiment of the present invention provides a combination of a low coercive field (which is characteristic of ferroelectric materials), no remanent polarization (which is characteristic of antiferroelectric materials), and a high dielectric constant during polarization switching operation (which is a common feature of ferroelectric and antiferroelectric materials).

The dielectric constant of the ferroelectric material is largest in the vicinity of the coercive field. Some researchers are developing memory devices using ferroelectric materials with relatively low coercive fields. However, such devices may have problems because the polarization does not become 0 at 0V and the residual polarization remains. Therefore, the use of ferroelectric materials in volatile memories is limited. On the other hand, the antiferroelectric material has a polarization of 0 at 0V, but has a relatively high coercive field, which limits its application in volatile memories.

In the following embodiments of the present invention, a semiconductor device including a stacked-layer structure is provided, which employs both a ferroelectric material and an antiferroelectric material. The stacked structure achieves low switching voltage (i.e., low coercive field), high capacitance, and no remanent polarization.

Fig. 1 illustrates a semiconductor device 100 according to an embodiment of the present invention.

Referring to fig. 1, a semiconductor device 100 may be a portion of a memory. The semiconductor device 100 may be part of a volatile memory. The semiconductor device 100 may be a part of a DRAM. The semiconductor device 100 may include a DRAM capacitor.

The semiconductor device 100 may include a first electrode 101, a second electrode 102, and a dielectric stack 110, the dielectric stack 110 being located between the first electrode 101 and the second electrode 102. The dielectric stack 110 may be in direct contact with the first electrode 101 and the second electrode 102.

The first electrode 101 may include a metal-containing material. The first electrode 101 may comprise, for example, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The first electrode 101 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO)₂) Iridium oxide (IrO)₂) Niobium nitride (NbN), molybdenum nitride (MoN), or combinations thereof. According to another embodiment of the present invention, the first electrode 101 may include a silicon-containing material. The first electrode 101 may comprise, for example, silicon germanium, or a combination thereof. According to another embodiment of the present invention, the first electrode 101 may comprise a stack of a metal-containing material and a silicon-containing material. The first electrode 101 may also be referred to as a 'bottom electrode' or storage node。

The second electrode 102 can include a silicon-containing material, a germanium-containing material, a metal-containing material, or a combination thereof. The second electrode 102 may comprise, for example, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The second electrode 102 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO)₂) Niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO)₂) Silicon (Si), germanium (Ge), silicon germanium (SiGe), or combinations thereof. The second electrode 102 may comprise a 'Si/SiGe stack' in which silicon germanium is stacked on silicon. In one embodiment, the second electrode 102 may comprise a 'Ge/SiGe stack' in which silicon germanium is stacked on germanium. In another embodiment, the second electrode 102 may be formed by stacking silicon germanium on a metal nitride. For example, the second electrode 102 may be formed by stacking silicon germanium (SiGe) on titanium nitride (TiN). According to another embodiment of the present invention, the second electrode 102 may include titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W), which are stacked in the stated order. According to another embodiment of the present invention, the second electrode 102 may include titanium nitride (TiN), silicon germanium (SiGe), and tungsten nitride (WN), which are stacked in the stated order.

Dielectric stack 110 may include at least one high-k material having a high dielectric constant of about 7 or more. The high-k material may have a higher dielectric constant than silicon oxide and silicon nitride. The dielectric stack 110 may comprise at least one ultra-high k material. The ultra-high k material may be a material having a higher dielectric constant than the high k material. The ultra-high k material may have a high dielectric constant of about 60 or higher. Dielectric stack 110 may include at least one ferroelectric material and at least one antiferroelectric material.

The dielectric stack 110 may comprise a multi-layer stack of different dielectric materials. The dielectric layer stack 110 may comprise a stack of three layers comprising a first dielectric layer 111, a second dielectric layer 112 and a third dielectric layer 113. The third dielectric layer 113 may be located between the first dielectric layer 111 and the second dielectric layer 112. The first, second, and third dielectric layers 111, 112, and 113 may be vertically disposed between the first and second electrodes 101 and 102.

At least one of the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 may be a ferroelectric material FE. For example, the third dielectric layer 113 may be a ferroelectric material FE. The first dielectric layer 111 and the second dielectric layer 112 may be a different material than the third dielectric layer 113. The first dielectric layer 111 and the second dielectric layer 112 may be the same material or different materials. At least one of the first dielectric layer 111 and the second dielectric layer 112 may be an antiferroelectric material AFE. In the embodiment of fig. 1, both the first dielectric layer 111 and the second dielectric layer 112 may be antiferroelectric materials AFE1, AFE 2.

The first dielectric layer 111 may include a first antiferroelectric material AFE1, and the second dielectric layer 112 may include, for example, a second antiferroelectric material AFE 2. The first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be the same antiferroelectric material. Alternatively, the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be different antiferroelectric materials. For example, the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may include, for example, hafnium (Hf) and zirconium (Zr). The first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may be made of a first hafnium zirconium oxide (HfZrO).

Other suitable materials for the first antiferroelectric material AFE1 and the second antiferroelectric material AFE2 may include PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃、NaNbO₃Or a combination thereof.

The third dielectric layer 113 may include a ferroelectric material FE. The ferroelectric material FE may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric material FE may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric material FE may comprise, for example, a second hafnium zirconium oxide (HfZrO).

Other suitable materials for the ferroelectric material FE may include BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

The first and second antiferroelectric materials AFE1 and AFE2 may include a first hafnium zirconium oxide, and the third dielectric layer 113 may include, for example, a second hafnium zirconium oxide. The first hafnium zirconium oxide and the second hafnium zirconium oxide may have different hafnium component ratios. The first hafnium zirconium oxide and the second hafnium zirconium oxide may have different zirconium component ratios. The first hafnium zirconium oxide and the second hafnium zirconium oxide may have different hafnium component ratios and zirconium component ratios.

The dielectric layer stack 110 of the semiconductor device 100 of fig. 1 may comprise a multi-layer stack structure of a ferroelectric material and an antiferroelectric material. A low coercive field can be obtained by the ferroelectric material FE, and no remanent polarization (i.e., zero level of remanent polarization) can be maintained by the first antiferroelectric material AFE1 and the second antiferroelectric material AFE 2.

In the embodiment of fig. 1, forming first and second antiferroelectric materials AFE1 and AFE2 in direct contact with first and second electrodes 101 and 102, respectively, enables a polarization of '0' to be obtained when no voltage (0V) is applied between first and second electrodes 101 and 102. When the voltage applied between the first electrode 101 and the second electrode 102 is gradually increased, as the ferroelectric material FE first starts to switch, a high dielectric constant can be ensured. Then, when the applied voltage is turned off (i.e., 0V), the polarization becomes '0' again (i.e., no remanent polarization), thereby achieving an operation of the volatile memory.

Dielectric stack 110 may be referred to as an "AFE-FE-AFE stack" because one ferroelectric material FE is located between two antiferroelectric materials AFE1 and AFE 2. The dielectric laminate 110 may have a polarity-voltage characteristic whose hysteresis loop shows two polarization characteristics (AFE-type and FE-type). The hysteresis loop of the dielectric stack 110 may have a non-linear direct contact. Here, the polarization of the nonlinear direct contact point may be '0'.

Fig. 2A depicts the polarity-voltage characteristics of a ferroelectric material. Fig. 2B shows the polarity-voltage characteristics of the antiferroelectric material. Fig. 2C shows the polarity-voltage characteristics of the AFE-FE-AFE stack.

Referring to fig. 2A, the ferroelectric material FE may have a high capacitance at a low voltage, but residual polarization (Pr and-Pr) may be present.

Referring to fig. 2B, the antiferroelectric material AFE may not have residual polarization (Pr), but may have low capacitance at low voltage.

Referring to fig. 2C, the AFE-FE-AFE stack may have a polarity-voltage characteristic exhibiting two kinds of polarization characteristics (AFE type and FE type). The ferroelectric hysteresis loop of the AFE-FE-AFE stack may have ferroelectric polarization (FE type), antiferroelectric polarization (AFE type), and nonlinear direct contact. Here, when the applied voltage is 0V, the polarization of the nonlinear direct contact point may be '0'. In the antiferroelectric hysteresis loop of fig. 2B, the portion polarized to '0' may be linear.

Referring to fig. 2C, it can be seen that the AFE-FE-AFE stack has high capacitance at low voltage and has a hysteresis loop with no remanent polarization.

Fig. 3 shows a semiconductor device according to another embodiment of the present invention.

The constituent elements of the semiconductor device 200 shown in fig. 2 may be the same as those of the semiconductor device 100 shown in fig. 1, except for the dielectric laminate layer 120. Hereinafter, with respect to the description of the first electrode and the second electrode, reference will be made to fig. 1. The semiconductor device 200 may be part of a memory. The semiconductor device 200 may be part of a volatile memory. The semiconductor device 200 may be part of a DRAM. The semiconductor device 200 may include a DRAM capacitor.

Referring to fig. 3, the semiconductor device 200 may include a first electrode 101, a second electrode 102, and a dielectric stack 120 between the first electrode 101 and the second electrode 102.

The dielectric stack 120 may comprise different hafnium zirconium oxides stacked on top of each other. Here, different hafnium zirconium oxides may have different hafnium component ratios,may have different zirconium component ratios, or may have different hafnium component ratios and zirconium component ratios. Different hafnium zirconium oxides may have different thicknesses. Different hafnium zirconium oxides may have different polarization characteristics. The hafnium zirconium oxide may comprise Hf_xZr_yO(x>0，y>0, and x + y ═ 1).

Hafnium zirconium oxide (Hf) according to the ratio of hafnium content (x) to zirconium content (y)_xZr_yO) may have ferroelectric or antiferroelectric properties. The ferroelectric hafnium zirconium oxide may have a hafnium content (x) of about 0.46 to about 0.75 and a zirconium content (y) of about 0.25 to about 0.54. The antiferroelectric hafnium zirconium oxide may have a hafnium content (x) of about 0.2 to about 0.45 and a zirconium content (y) of about 0.55 to about 0.8.

The dielectric layer stack 120 may include a first hafnium zirconium oxide (HZO1)121, a second hafnium zirconium oxide (HZO2)122, and a third hafnium zirconium oxide (HZO3)123 between the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122. The reference marks HZO1, HZO2 and HZO3 may denote Hf, respectively_xZr_yO。

The first hafnium zirconium oxide 121 and the third hafnium zirconium oxide 123 may have different hafnium component ratios. The first hafnium zirconium oxide 121 and the third hafnium zirconium oxide 123 may have different zirconium component ratios. The first hafnium zirconium oxide 121 and the third hafnium zirconium oxide 123 may have different hafnium component ratios and different zirconium component ratios. The first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122 may have the same hafnium component ratio and the same zirconium component ratio.

The first hafnium zirconium oxide 121 may include Hf_xZr_yO(x>0，y>0, x is 0.46 to 0.75, y is 0.25 to 0.54, and x + y is 1). At Hf_xZr_yIn O, the hafnium content (x) and the zirconium content (y) may be the same. In one example, the hafnium content (x) may be 0.5 and the zirconium content (y) may be 0.5.

The second hafnium zirconium oxide 122 may include Hf_xZr_yO(x>0，y>0, x is 0.46 to 0.75, y is 0.25 to 0.54, and x + y is 1). In the second hafnium zirconium oxide 122, the hafnium content (x) and the zirconium content (y) may be the same. For example,the ratio of hafnium content (x) to zirconium content (y) may be about 1: 1. For example, the hafnium content (x) may be about 0.5, and the zirconium content (y) may be about 0.5.

The third hafnium zirconium oxide 123 may comprise Hf_xZr_yO(x>0，y>0, x is 0.2 to 0.45, y is 0.55 to 0.8, x + y is 1, and y>x). At Hf_xZr_yIn O, the hafnium content (x) may be smaller than the zirconium content (y). For example, the zirconium content (y) may be at least twice the hafnium content (x). For example, the ratio of the zirconium content (y) to the hafnium content (x) may be about 2: 1. As an example, the hafnium content (x) may be about 0.3, and the zirconium content (y) may be about 0.7. Thus, a hafnium zirconium oxide having a high zirconium content (y) may be referred to as a 'zirconium (Zr) rich hafnium zirconium oxide' or a 'zirconium oxide rich hafnium zirconium oxide'. The third hafnium zirconium oxide 123 may have a larger zirconium content than the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122.

Hafnium zirconium oxide (Hf)_xZr_yO) may have a ferroelectric FE characteristic or an antiferroelectric AFE characteristic based on the hafnium content (x) and the zirconium content (y). In addition, the critical concentration at which the change between the ferroelectric FE characteristic and the antiferroelectric AFE characteristic appears may be different based on the hafnium content (x) and the zirconium content (y).

For example, when the hafnium content (x) and the zirconium content (y) are the same, Hf_0.5Zr_0.5O may have ferroelectric properties.

When the zirconium content is greater than the hafnium content (i.e., zirconium-rich Hf)_xZr_yO), e.g. Hf_0.3Zr_0.7O, which may have antiferroelectric AFE characteristics.

Referring to fig. 3, the third hafnium zirconium oxide 123 having ferroelectric properties may be controlled to have a ratio of the hafnium content to the zirconium content of 1:1, and the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122 having antiferroelectric properties may be controlled to have a ratio of the zirconium content to the hafnium content of at least 2 times or more as large as the zirconium to the hafnium (e.g., y/x is at least equal to 2: 1).

As the dielectric layer 123 is formed by controlling the combination of the zirconium content and the hafnium content in this manner, the polarization-voltage curve may start to switch at a low voltage, and the polarization becomes '0' again at '0V', thereby implementing an operation as a volatile memory.

In the embodiment of fig. 1, the first and second dielectric layers 111 and 112 are in direct contact with the first and second electrodes 101 and 102, respectively. Furthermore, in the embodiment of fig. 3, the first hafnium zirconium oxide 121 and the second hafnium zirconium oxide 122 are in direct contact with the first electrode 101 and the second electrode 102, respectively.

Fig. 4 is a view for describing a semiconductor device according to another embodiment of the present invention. The semiconductor device 300 of fig. 4 may have the same constituent elements as the semiconductor device 100 of fig. 1, except for the interface layer 331. Hereinafter, with respect to detailed description of the first electrode and the second electrode, reference may be made to fig. 1 and the description thereof. The semiconductor device 300 may be part of a memory. The semiconductor device 300 may be part of a volatile memory. The semiconductor device 300 may be part of a DRAM. The semiconductor device 300 may include a DRAM capacitor.

Referring to fig. 4, the semiconductor device 300 may include a first electrode 101, a second electrode 102, and a dielectric stack 320, the dielectric stack 320 being disposed between the first electrode 101 and the second electrode 102. The semiconductor device 300 may further include an interfacial layer 331 disposed between the second electrode 102 and the dielectric stack 320.

Dielectric stack 320 may include multiple stacks of layers of different dielectric materials. The dielectric layer stack 320 may have a stack of three layers including a first antiferroelectric layer 321, a second antiferroelectric layer 322, and a ferroelectric layer 323. The ferroelectric layer 323 may be located between the first antiferroelectric layer 321 and the second antiferroelectric layer 322.

The first and second antiferroelectric layers 321 and 322 may be made of the same antiferroelectric material or different antiferroelectric materials. The first and second antiferroelectric layers 321 and 322 may include, for example, hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 321 and 322 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 321 and 322 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first and second antiferroelectric layers 321 and 322 may include a zirconium-rich content with a ratio of zirconium content to hafnium content of 2:1Hafnium zirconium oxide (Zr rich HfZrO). Other suitable materials for the first and second antiferroelectric layers 321, 322 may include PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃、NaNbO₃And combinations thereof.

The ferroelectric layer 323 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may include hafnium zirconium oxide (HfZrO) having a ratio of zirconium content to hafnium content of 1: 1. Other suitable materials for the ferroelectric layer 323 may include BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

The interfacial layer 331 may be used to suppress leakage current of the dielectric stack 320. The interface layer 331 may be used to protect the dielectric stack 320 when forming the second electrode 102. The interfacial layer 331 may include a material that is reduced prior to the dielectric stack 320 when forming the second electrode 102. The interfacial layer 331 may function as a leakage current barrier having a large effective work function (eWF) and a large Conduction Band Offset (CBO). Furthermore, the interfacial layer 331 may not increase the equivalent oxide film thickness T of the dielectric stack 320_ox. The interface layer 331 may be used as a part of the second electrode 102.

The interface layer 331 may be a material having a large electronegativity. The interface layer 331 may have a greater Pauling electronegativity (Pauling electronegativity) than the dielectric layer stack 320. The interface layer 331 may include a material having a greater pauling electronegativity (hereinafter, abbreviated as 'electronegativity') than the first and second antiferroelectric layers 321 and 322 and the ferroelectric layer 323. The interface layer 331 may have a sufficiently large electronegativity so that it is hardly oxidized and is easily reduced. Therefore, the interfacial layer 331 may lose oxygen instead of the dielectric stack 320, and therefore the interfacial layer 331 may prevent oxygen loss of the dielectric stack 320.

The interface layer 331 may include atoms having a large electronegativity, for example, metal atoms, silicon atoms, or germanium atoms. The interfacial layer 331 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

The interfacial layer 331 may comprise, for example, titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO)₂) Tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof. According to another embodiment of the present invention, the interfacial layer 331 may comprise a stack of molybdenum and molybdenum nitride (Mo/MoN) or a stack of tungsten and tungsten nitride (W/WN).

Fig. 5 is a view illustrating a semiconductor device 301 according to another embodiment of the present invention. The constituent elements of the semiconductor device 301 of fig. 5 may be the same as those of the semiconductor device 300 shown in fig. 4, except for the additional interface layer 332. The semiconductor device 301 may be part of a memory. The semiconductor device 301 may be part of a volatile memory. The semiconductor device 301 may be a part of a DRAM. The semiconductor device 301 may include a DRAM capacitor.

Referring to fig. 5, the semiconductor device 301 may include: a first electrode 101; a second electrode 102; a dielectric stack 320 disposed between the first electrode 101 and the second electrode 102; and an interfacial layer 331 between the second electrode 102 and the dielectric stack 320. The semiconductor device 301 may further comprise an additional interface layer 332, which is arranged between the first electrode 101 and the dielectric stack 320.

Dielectric stack 320 may include multiple stacks of layers of different dielectric materials. The dielectric layer stack 320 may include a stack of three layers including a first antiferroelectric layer 321, a second antiferroelectric layer 322, and a ferroelectric layer 323. The ferroelectric layer 323 may be located between the first antiferroelectric layer 321 and the second antiferroelectric layer 322.

The first and second antiferroelectric layers 321 and 322 may be the same antiferroelectric material or different antiferroelectric materials. The first and second antiferroelectric layers 321 and 322 may include, for example, hafnium (Hf) and zirconium (Zr). The first anti-ferroelectric layer 321 and the second anti-ferroelectric layer 322 may beIncluding oxides of hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 321 and 322 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first and second antiferroelectric layers 321, 322 may include a zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) with a ratio of zirconium content to hafnium content of about 2: 1. Other suitable materials for the first and second antiferroelectric layers 321, 322 may include PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃、NaNbO₃And combinations thereof.

The ferroelectric layer 323 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323 may include hafnium zirconium oxide (HfZrO) having a ratio of zirconium content to hafnium content of about 1: 1. Other suitable materials for the ferroelectric layer 323 may include BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

The interfacial layer 331 and the additional interfacial layer 332 may be used to suppress leakage current of the dielectric stack 320. The interface layer 331 may be used to protect the dielectric stack 320 when forming the second electrode 102. The interfacial layer 331 may include a material that is reduced prior to the dielectric stack 320 when forming the second electrode 102. The interfacial layer 331 and the additional interfacial layer 332 may function as a leakage current block having a large effective work function (eWF) and a large Conduction Band Offset (CBO). Furthermore, the interfacial layer 331 and the additional interfacial layer 332 may not increase the equivalent oxide film thickness T of the dielectric stack 320_ox. The interface layer 331 may be used as a part of the second electrode 102.

The interface layer 331 and the additional interface layer 332 may be the same material. The interface layer 331 and the additional interface layer 332 may have the same thickness. The interface layer 331 and the additional interface layer 332 may be thinner than the first and second antiferroelectric layers 321 and 322 and the ferroelectric layer 323.

The additional interface layer 332 may be a material with a large electronegativity. The additional interfacial layer 332 may have a greater pauling electronegativity than the dielectric stack 320. The additional interface layer 332 may include a material having a greater pauling electronegativity (hereinafter, abbreviated as 'electronegativity') than the first and second antiferroelectric layers 321 and 322 and the ferroelectric layer 323. The additional interface layer 332 may have a sufficiently large electronegativity so that it is hardly oxidized and is easily reduced.

The interface layer 331 and the additional interface layer 332 may include atoms having a large electronegativity, such as metal atoms, silicon atoms, or germanium atoms. The interfacial layer 331 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

The interfacial layer 331 and the additional interfacial layer 332 may include titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO)₂) Tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof. According to another embodiment of the present invention, the interfacial layer 331 may comprise a stack of molybdenum and molybdenum nitride (Mo/MoN) or a stack of tungsten and tungsten nitride (W/WN).

Fig. 6 shows a semiconductor device 400 according to another embodiment of the invention. The semiconductor device 400 of fig. 6 may be similar to the semiconductor device 100 of fig. 1. The semiconductor device 400 may be part of a memory. The semiconductor device 400 may be part of a volatile memory. The semiconductor device 400 may be a part of a DRAM. The semiconductor device 400 may include a DRAM capacitor.

Referring to fig. 6, a semiconductor device 400 may include a first electrode 101, a second electrode 102, and a dielectric stack 420 between the first electrode 101 and the second electrode 102. Hereinafter, with respect to a detailed description of the first electrode 101 and the second electrode 102, reference may be made to fig. 1 and the description thereof.

Dielectric layer stack 420 may include at least one antiferroelectric layer and at least one ferroelectric layer. The dielectric stack 420 may include a first stack 420A and a second stack 420B. The dielectric stack 420 may further include a high band gap layer 424, the high band gap layer 424 being disposed between the first stack 420A and the second stack 420B.

Stack 420A may comprise a multi-layer stack of different dielectric materials. The stack 420A may include a stack of three layers including a first antiferroelectric layer 421, a second antiferroelectric layer 422, and a ferroelectric layer 423. The ferroelectric layer 423 may be located between the first antiferroelectric layer 421 and the second antiferroelectric layer 422. The first and second antiferroelectric layers 421 and 422 may be the same antiferroelectric material or different antiferroelectric materials. The first and second antiferroelectric layers 421 and 422 may include, for example, hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 421 and 422 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 421 and 422 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first and second antiferroelectric layers 421 and 422 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content and a hafnium content of about 2: 1. Other suitable materials for the first antiferroelectric layer 421 and the second antiferroelectric layer 422 may include PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃、NaNbO₃And combinations thereof. The ferroelectric layer 423 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 423 may be made of an oxide including hafnium (Hf) and zirconium (Zr). Ferroelectric layer 423 may include hafnium zirconium oxide (HfZrO) having a ratio of zirconium content to hafnium content of about 1: 1. Other suitable materials for the ferroelectric layer 423 may include BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

The second stack 420B may comprise a multi-layer stack of different dielectric materials. The second stack 420B may include a stack of three layers including a first antiferroelectric layer 421 ', a second antiferroelectric layer 422 ', and a ferroelectric layer 423 '. The ferroelectric layer 423 ' may be located between the first antiferroelectric layer 421 ' and the second antiferroelectric layer 422 '. The first antiferroelectric layer 421 'and the second antiferroelectric layer 422' may be the same antiferroelectric material or different antiferroelectric materials.The first and second antiferroelectric layers 421 'and 422' may include, for example, hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 421 'and 422' may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 421 'and 422' may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first and second antiferroelectric layers 421 'and 422' may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content and a hafnium content of about 2: 1. Other suitable materials for the first antiferroelectric layer 421 'and the second antiferroelectric layer 422' may include PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃Or NaNbO₃. The ferroelectric layer 423' may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 423' may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer 423' may include hafnium zirconium oxide (HfZrO) having a zirconium content and a hafnium content of about 1: 1. Other suitable materials for the ferroelectric layer 423' may include BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

The height (thickness) of the first stack 420A and the height (thickness) of the second stack 420B may be the same or different. The first laminate 420A and the second laminate 420B may have the same structure.

In this embodiment, the first stack layer 420A and the second stack layer 420B may each have a three-layer stack structure including two antiferroelectric layers and one ferroelectric layer. The first antiferroelectric layer 421 of the first stack 420A and the first antiferroelectric layer 421' of the second stack 420B may be made of the same antiferroelectric material or different antiferroelectric materials. The second antiferroelectric layer 422 of the first stack 420A and the second antiferroelectric layer 422' of the second stack 420B may be made of the same antiferroelectric material or different antiferroelectric materials. The ferroelectric layer 423 of the first stack 420A and the ferroelectric layer 423' of the second stack 420B may be made of the same ferroelectric material or different ferroelectric materials.

The first and second antiferroelectric layers 421 and 421 'and 422' may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first and second antiferroelectric layers 421 and 421 'and 422' may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) with a ratio of zirconium content to hafnium content of about 2: 1. Other suitable materials for the first antiferroelectric layers 421 and 421 'and the second antiferroelectric layers 422 and 422' may include PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃、NaNbO₃And combinations thereof. Ferroelectric layers 423 and 423' may include hafnium zirconium oxide (HfZrO) with a ratio of zirconium content to hafnium content of about 1: 1. Other suitable materials for the ferroelectric layers 423 and 423' may include BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

High band gap layer 424 may be used to prevent leakage current of dielectric stack 420. The high bandgap layer 424 may comprise a high bandgap energy material. The high bandgap layer 424 can have a bandgap energy of about 8.8eV to about 10.6 eV. The high bandgap layer 424 may comprise a material with a higher bandgap energy than the first stack of layers 420A and the second stack of layers 420B. The high band gap layer 424 may include a material having a band gap energy higher than that of the first anti-ferroelectric layers 421 and 421 ', the second anti-ferroelectric layers 422 and 422 ', and the ferroelectric layers 423 and 423 '. The high bandgap layer 424 may comprise a different material than the first stack of layers 420A and the second stack of layers 420B. The high bandgap layer 424 may include a high-k material, but may have a lower dielectric constant than the first stack 420A and the second stack 420B. The high bandgap layer 424 may have a higher dielectric constant than silicon oxide and silicon nitride. The high bandgap layer 424 may comprise aluminum oxide or beryllium oxide. The high bandgap layer 424 may be thinner than the first stack 420A and the second stack 420B. Since the high bandgap layer 424 has a relatively low dielectric constant compared to the dielectric constant of the first stack 420A and the second stack 420B, the high bandgap layer 424 can be formed very thin to increase capacitance.

Fig. 7 shows a semiconductor device 401 according to another embodiment of the invention. The semiconductor device 401 of fig. 7 may be similar to the semiconductor device 400 of fig. 6. The semiconductor device 401 may be part of a memory. The semiconductor device 401 may be part of a volatile memory. The semiconductor device 401 may be part of a DRAM. Semiconductor device 401 may include a DRAM capacitor.

Referring to fig. 7, a semiconductor device 401 may include a first electrode 101, a second electrode 102, and a dielectric stack 420' between the first electrode 101 and the second electrode 102. Hereinafter, for a detailed description of the first electrode 101 and the second electrode 102, reference may be made to fig. 1 and the description thereof.

The dielectric layer stack 420' may include at least one antiferroelectric layer and at least one ferroelectric layer. The dielectric stack 420' may comprise at least one tri-layer stack TL and at least one high band gap layer HBG. The dielectric layer stack 420' may be formed by alternately stacking the three-layer stack TL with the high band gap layer HBG at least two or more times. Thus, the dielectric layer stack 420' may be a stack comprising a plurality of alternating three-layer stacks TL and high band gap layers HBG. The bottom tri-layer stack TL among the tri-layer stacks TL may directly contact the first electrode 101, and the top tri-layer stack TL among the tri-layer stacks TL may directly contact the second electrode 102. The high band gap layer HBG may not be in direct contact with the first electrode 101 and the second electrode 102. According to another embodiment of the invention, a high bandgap layer HBG may be added between the top three-layer stack TL and the second electrode 102.

The three layer stack TL may correspond to the first stack 420A or the second stack 420B of fig. 6. The three-layer stack TL may have a structure in which a ferroelectric layer is located between antiferroelectric layers. The high band gap layer HBG may correspond to the high band gap layer 424 of fig. 6.

The tri-layer stack TL may comprise a first antiferroelectric layer AFEL1, a second antiferroelectric layer AFEL2, and a ferroelectric layer FEL disposed between the first antiferroelectric layer AFEL1 and the second antiferroelectric layer AFEL 2. The first and second antiferroelectric layers AFEL1 and AFEL2 may be made of the same antiferroelectric material or different antiferroelectric materials. A first antiferroelectric layer AFEL1 and a second antiferroelectric layer AFEL1The antiferroelectric layer AFEL2 may include, for example, hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers AFEL1 and AFEL2 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers AFEL1 and AFEL2 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first and second antiferroelectric layers AFEL1, 2 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) with a ratio of zirconium content to hafnium content of about 2: 1. According to another embodiment of the present invention, the first and second antiferroelectric layers AFEL1 and AFEL2 may be made of other suitable materials, including PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃、NaNbO₃And combinations thereof. The ferroelectric layer FEL may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer FEL may be made of an oxide including hafnium (Hf) and zirconium (Zr). The ferroelectric layer FEL may comprise hafnium zirconium oxide (HfZrO) with a ratio of zirconium content to hafnium content of about 1: 1. According to another embodiment of the invention, the ferroelectric layer FEL may be made of other suitable materials including BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

The high band gap layer HBG may be used to prevent leakage current of the dielectric stack 420'. The high band gap layer HBG may comprise a high band gap energy material. The high bandgap layer HBG may have a bandgap energy of about 8.8eV to about 10.6 eV. The high band gap layer HBG may comprise a material having a higher band gap energy than the three layer stack TL. The high band gap layer HBG may include a material having a band gap energy higher than that of the first and second antiferroelectric layers AFEL1 and AFEL2 and the ferroelectric layer FEL. The high band gap layer HBG may comprise a different material than the three layer stack TL. The high band gap layer HBG may comprise a high-k material, but may have a lower dielectric constant than the three layer stack TL. The high band gap layer HBG may have a higher dielectric constant than silicon oxide and silicon nitride. The high bandgap layer HBG may comprise aluminum oxide or beryllium oxide. The high band gap layer HBG may be thinner than the three layer stack TL. Since the high band gap layer HBG has a relatively low dielectric constant compared to the three-layer stack TL, the high band gap layer HBG can be formed very thin to increase capacitance.

Fig. 8A and 8B illustrate semiconductor devices according to other embodiments of the present invention. The semiconductor device 402 of fig. 8A and the semiconductor device 403 of fig. 8B may be similar to the semiconductor device 400 of fig. 6. Each of the semiconductor devices 402 and 403 may be a part of a memory. Each of the semiconductor devices 402 and 403 may be a part of a volatile memory. Each of the semiconductor devices 402 and 403 may be a part of a DRAM. Each of the semiconductor devices 402 and 403 may include a DRAM capacitor.

Referring to fig. 8A, the semiconductor device 402 may include: a first electrode 101; a second electrode 102; a dielectric stack 420 between the first electrode 101 and the second electrode 102; and an interfacial layer 431 between the second electrode 102 and the dielectric stack 420.

The dielectric stack 420 may include a first stack 420A, a second stack 420B, and a high band gap layer 424, the high band gap layer 424 being disposed between the first stack 420A and the second stack 420B. The first stack 420A may include a first anti-ferroelectric layer 421, a second anti-ferroelectric layer 422, and a ferroelectric layer 423, wherein the ferroelectric layer 423 is disposed between the first anti-ferroelectric layer 421 and the second anti-ferroelectric layer 422. The second stack 420B may include a first antiferroelectric layer 421 ', a second antiferroelectric layer 422', and a ferroelectric layer 423 ', the ferroelectric layer 423' being disposed between the first antiferroelectric layer 421 'and the second antiferroelectric layer 422'.

Hereinafter, a detailed description of the first electrode 101, the second electrode 102, and the dielectric stack 420 will be described with reference to the above-described embodiments of the present invention.

The interface layer 431 may correspond to the interface layer 331 of fig. 4.

The interface layer 431 may be located between the second stack 420B and the second electrode 102. The interface layer 431 may be a material having a large electronegativity. The interfacial layer 431 may have a higher pauling electronegativity than the dielectric stack 420. The interface layer 431 may include a material having electrical negativity greater than that of the first anti-ferroelectric layers 421 and 421 ', the second anti-ferroelectric layers 422 and 422 ', and the ferroelectric layers 423 and 423 '. Therefore, the interfacial layer 431 can prevent oxygen loss of the dielectric stack 420.

The interface layer 431 may include atoms having a large electronegativity, such as metal atoms, silicon atoms, or germanium atoms. The interfacial layer 431 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

Interfacial layer 431 may comprise titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO)₂) Tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof. According to another embodiment of the present invention, the interfacial layer 431 may comprise a stack of molybdenum and molybdenum nitride (Mo/MoN) or a stack of tungsten and tungsten nitride (W/WN).

The semiconductor device 403 of fig. 8B may have the same constituent elements as those of the semiconductor device 402 of fig. 8A, except for the additional interface layer 432.

The semiconductor device 403 may include: a first electrode 101; a second electrode 102; a dielectric stack 420 disposed between the first electrode 101 and the second electrode 102; an interfacial layer 431 between the second electrode 102 and the dielectric stack 420; and an additional interfacial layer 432 disposed between first electrode 101 and dielectric stack 420.

Additional interfacial layers 432 and 431 may be used to suppress leakage current of the dielectric stack 420. The interface layer 431 may be used to protect the dielectric stack 420 when forming the second electrode 102. The interface layer 431 may include a material that is reduced prior to the dielectric stack 420 when forming the second electrode 102. The interface layer 431 and the additional interface layer 432 may serve as a large leakage current block having a large effective work function (eWF) and a large Conduction Band Offset (CBO). Furthermore, the interface layer 431 and the additional interface layer 432 may not increase the equivalent oxide film thickness T of the dielectric stack 420_ox. The interface layer 431 may be used as a part of the second electrode 102.

The interface layer 431 and the additional interface layer 432 may be made of the same material. The interface layer 431 and the additional interface layer 432 may have the same thickness. The interface layer 431 and the additional interface layer 432 may be thinner than the first and second antiferroelectric layers 421 and 422 and the ferroelectric layer 423.

The additional interface layer 432 may be a material having a large electronegativity. The additional interfacial layer 432 may have a greater bowlin electronegativity than the dielectric stack 420. The additional interface layer 432 may include a material having electrical negativity greater than that of the first anti-ferroelectric layers 421 and 421 ', the second anti-ferroelectric layers 422 and 422 ', and the ferroelectric layers 423 and 423 '.

The additional interface layer 432 may include atoms having a large electronegativity, such as metal atoms, silicon atoms, or germanium atoms. The interfacial layer 331 may include, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni), or a combination thereof.

Additional interfacial layer 432 may comprise titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO)₂) Tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof.

In accordance with another embodiment of the present invention, dielectric stack 420 of semiconductor devices 402 and 403 may be replaced with an alternating stack corresponding to dielectric stack 420' of fig. 7.

Fig. 9A to 9C are views showing a memory cell. Fig. 9B is a sectional view taken along line a-a' in fig. 9A. Fig. 9C is a sectional view taken along line B-B' in fig. 9A.

The memory cell 500 may include a cell transistor including a buried word line 508, a bit line 514, and a capacitor 600. Capacitor 600 may include a dielectric stack and the dielectric stack may include one of the dielectric stacks of the above-described embodiments of the present invention.

The memory cell 500 will now be described in detail.

An isolation layer 503 and an active region 504 may be formed over the substrate 501. A plurality of active regions 504 may be defined by the isolation layer 503. The substrate 501 may be a material suitable for semiconductor processing. The substrate 501 may include a semiconductor substrate. The substrate 501 may be formed of a silicon-containing material. Substrate 501 may include, for example, silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon doped silicon, combinations thereof, or multilayers thereof. The substrate 501 may also comprise other semiconductor materials, such as germanium. Substrate 501 may comprise a group III/V semiconductor substrate, for example a compound semiconductor substrate such as GaAs. The substrate 501 may comprise a silicon-on-insulator (SOI) substrate. The isolation layer 503 may be formed in the isolation trench 502 through a Shallow Trench Isolation (STI) process.

A word line trench 506 may be formed in the substrate 501. The word line trench 506 may be referred to as a gate trench. A gate dielectric layer 507 may be formed on the surface of the word line trench 506. A buried word line 508 partially filling the word line trench 506 may be formed over the gate dielectric layer 507. The buried word lines 508 may be referred to as buried gate electrodes. A word line capping layer 509 may be formed over the buried word line 508. The top surface of the buried word line 508 may be located at a lower level than the surface of the substrate 501. The buried word line 508 may be made of a metal material with low resistance. The buried word line 508 may be made of a stack in which titanium nitride and tungsten are sequentially stacked. According to another embodiment of the present invention, the buried word lines 508 may be formed of only titanium nitride (only TiN).

A first impurity region 510 and a second impurity region 511 may be formed in the substrate 501. The first impurity region 510 and the second impurity region 511 may be spaced apart from each other by the word line trench 506. The first impurity region 510 and the second impurity region 511 may be referred to as a first source/drain region and a second source/drain region. The first impurity region 510 and the second impurity region 511 may include an N-type impurity such As arsenic (As) or phosphorus (P). Accordingly, the buried word line 508 and the first and second impurity regions 510 and 511 may become a cell transistor. The cell transistor can improve short channel effects by burying the word line 508.

A bit line contact plug 513 may be formed over the substrate 501. The bit line contact plug 513 may be coupled to the first impurity region 510. Bit line contact plugs 513 may be located in the bit line contact holes 512. The hard mask layer 505 may be utilized to form the bit line contact hole 512. A hard mask layer 505 may be formed over the substrate 501. The bit line contact hole 512 may expose the first impurity region 510. The bottom surface of the bit line contact plug 513 may be lower than the top surface of the substrate 501. The bit line contact plug 513 may be formed of, for example, polysilicon or a metal material. A portion of the bit line contact plug 513 may have a line width smaller than the diameter of the bit line contact hole 512. The bit line 514 may be formed over the bit line contact plug 513. A bitline hard mask 515 may be formed over the bitline 514. The stacked structure of the bit line 514 and the bit line hard mask 515 may be referred to as a bit line structure BL. The bit lines 514 may have a line shape extending in a direction crossing the buried word lines 508. A portion of bit line 514 may be coupled to bit line contact plug 513. The bit line 514 may include a metallic material. The bitline hard mask 515 may comprise a dielectric material.

The bit line spacers 516 may be formed on sidewalls of the bit line structure BL. The bottom portion of the bit line spacer 516 may extend to be formed at both sides of the bit line contact plug 513. The bit line spacers 516 may comprise, for example, silicon oxide, silicon nitride, or a combination thereof. According to another embodiment of the invention, the bit line spacers 516 may include air gaps. For example, it may be a NAN (nitride-air gap-nitride) structure, in which air gaps are located between silicon nitrides.

The storage node contact plug SNC may be formed between adjacent bit line structures BL. The storage node contact plug SNC may be formed in the storage node contact hole 518. The storage node contact plug SNC may be coupled to the second impurity region 511. The storage node contact plug SNC may include a lower plug 519 and an upper plug 521. The storage node contact plug SNC may further include an ohmic contact layer 520 disposed between the lower plug 519 and the upper plug 521. The ohmic contact layer 520 may include a metal silicide. The upper plug 521 may include a metal material and the lower plug 519 may include a silicon-containing material.

From the viewpoint of the direction parallel to the bit line structure BL, a plug isolation layer 517 may be formed between the adjacent storage node contact plugs SNC. A plug isolation layer 517 may be formed between adjacent bit line structures BL, and may provide a storage node contact hole 518 together with the hard mask layer 505.

The capacitor 600 may be coupled to the storage node contact plug SNC.

Fig. 10A to 10F are views showing application examples of the capacitor 600 of the memory cell. Hereinafter, the lower electrodes 601, 601P, and 601L may correspond to the first electrode 101 of the above-described embodiment of the present invention, and the upper electrode 602 may correspond to the second electrode 102.

Referring to fig. 10A, a capacitor 611 may include a lower electrode 601, a dielectric stack 603, and an upper electrode 602. The lower electrode 601 may have a cylindrical shape (cylindrical shape). The dielectric stack 603 may correspond to one of the dielectric stacks of the above embodiments. Thus, dielectric stack 603 may include a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer. Dielectric stack 603 may include, for example, two zirconium-rich hafnium zirconium oxide layers and one hafnium zirconium oxide layer. The two zirconium-rich hafnium zirconium oxide layers may include a zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a ratio of zirconium content to hafnium content of about 2: 1. A hafnium zirconium oxide layer may include a hafnium zirconium oxide having a ratio of zirconium content to hafnium content of about 1: 1.

Hereinafter, detailed description of a portion overlapping with the embodiment of fig. 10A in fig. 10B to 10F will be omitted.

Referring to fig. 10B, the capacitor 612 may include a lower electrode 601, a dielectric laminate 603, and an upper electrode 602, which are formed in a cylindrical shape. The capacitor 612 may further include a support 600S. The support 600S may be a structure supporting an outer wall of the lower electrode 601. The support 600S may include, for example, silicon nitride. According to another embodiment of the present invention, a multi-stage supporter formed of a plurality of supporters 600S may support the lower electrode 601. For example, the multi-stage support may be a two-stage support structure formed by a lower stage support and an upper stage support. Further, the multi-stage support may be a three-stage support structure formed of a lower stage support, a middle stage support, and an upper stage support.

Referring to fig. 10C and 10D, the capacitor 613 and the capacitor 614 may include a lower electrode 601P, a dielectric stack 603, and an upper electrode 602, wherein the lower electrode has a pillar shape. The capacitor 614 in fig. 10D may further include a support 600S.

Referring to fig. 10E and 10F, the capacitors 615 and 616 may include a lower electrode 601L, a dielectric stack 603, and an upper electrode 602, where the lower electrode has a pillar shape (fig. 10E) or a hybrid pillar-cylinder shape (fig. 10F). The capacitor 616 of fig. 10F may also include a support 600S. The lower electrode 601L may be a hybrid structure in which a columnar shape and a cylindrical shape are combined. More specifically, the lower electrode 601L may have a columnar lower portion and a cylindrical upper portion. Such a hybrid structure of a columnar shape and a cylindrical shape may be simply referred to as a hybrid column-cylinder shape. In one embodiment, the support 600S may be in columnar contact with the lower electrode 601L.

The dielectric laminate according to the above-described embodiments of the present invention can be applied to peripheral circuits of a DRAM. For example, the DRAM may include: a memory cell region including a memory cell (500 in fig. 9A) and a peripheral circuit region including a peripheral transistor. The gate dielectric layer of the peripheral transistor may comprise one of the above-described embodiments of the dielectric layer stack of the present invention. For example, the gate dielectric layer of the peripheral transistor may include a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric layer. The gate dielectric layer of the peripheral transistor may include two zirconium-rich hafnium zirconium oxide layers and one hafnium zirconium oxide layer. The two zirconium-rich hafnium zirconium oxide layers may include a zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a ratio of zirconium content to hafnium content of about 2: 1. A hafnium zirconium oxide layer may include a hafnium zirconium oxide having a ratio of zirconium content to hafnium content of about 1: 1.

Fig. 11 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

Referring to fig. 11, a semiconductor device 700 may include a transistor. The semiconductor device 700 may include a semiconductor substrate 701, a gate dielectric layer 710, a gate electrode 720, a source region 740, and a drain region 750. A gate dielectric layer 710 may be formed over the semiconductor substrate 701, and a gate electrode 720 may be formed over the gate dielectric layer 710. A source region 740 and a drain region 750 may be formed in the semiconductor substrate 701.

Gate dielectric layer 710 may comprise one of the dielectric layer stacks according to the above-described embodiments of the present invention. In this embodiment, the gate dielectric layer 710 may be a stack of three layers including a first antiferroelectric layer 711, a second antiferroelectric layer 712, and a ferroelectric layer 713, the ferroelectric layer 713 being disposed between the first antiferroelectric layer 711 and the second antiferroelectric layer 712. The first and second antiferroelectric layers 711 and 712 may be made of the same antiferroelectric material or different antiferroelectric materials. The first and second antiferroelectric layers 711 and 712 may include, for example, hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 711 and 712 may be made of an oxide including hafnium (Hf) and zirconium (Zr). The first and second antiferroelectric layers 711 and 712 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The first and second antiferroelectric layers 711 and 712 may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content and a hafnium content of about 2: 1. Other suitable materials for the first anti-ferroelectric layer 711 and the second anti-ferroelectric layer 712 may include PbZrO₃、PbHfO₃、PbMgWO₃、PbZrTiO₃、BiNaTiO₃、NaNbO₃And combinations thereof. The ferroelectric layer 713 may include, for example, hafnium (Hf) and zirconium (Zr). The ferroelectric layer 713 may be made of an oxide including hafnium (Hf) and zirconium (Zr). Ferroelectric layer 713 may include hafnium zirconium oxide (HfZrO) having a ratio of zirconium content to hafnium content of about 1: 1. Other suitable materials for the ferroelectric layer 713 may include BaTiO₃、PbTiO₃、BiFeO₃、SrTiO₃、PbMgNdO₃、PbMgNbTiO₃、PbZrNbTiO₃、PbZrTiO₃、KNbO₃、LiNbO₃、GeTe、LiTaO₃、KNaNbO₃、BaSrTiO₃And combinations thereof.

The gate electrode 720 may be a metal gate electrode including a metal-based material. The gate electrode 720 may comprise, for example, tungsten, aluminum, tungsten nitride, titanium, or combinations thereof.

The source region 740 and the drain region 750 may include impurities of the same conductivity type. The source region 740 and the drain region 750 may include N-type impurities or P-type impurities. The N-type impurity may include, for example, phosphorus or arsenic, and the P-type impurity may include boron or indium.

According to another embodiment of the present invention, a thin interfacial layer may be further formed between the gate dielectric layer 710 and the semiconductor substrate 701. The thin interfacial layer may comprise, for example, silicon oxide or silicon oxynitride.

According to another embodiment of the invention, the gate dielectric layer 710 may be applied to a gate dielectric layer of a fin FET.

The dielectric stack according to the above-described embodiments of the present invention may be applied to a metal-insulator-metal (MIM) capacitor. For example, a MIM capacitor may include a first metal electrode, a second metal electrode, and a dielectric stack formed between the first metal electrode and the second metal electrode. The dielectric stack of the MIM capacitor may comprise one of the above-described embodiments of the dielectric stack of the present invention. For example, the dielectric layer stack may include a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer.

The dielectric layer stack according to the above-described embodiments of the invention may be applied to an embedded DRAM. For example, an embedded DRAM may include a logic circuit and a capacitor, and the capacitor of the embedded DRAM may include a lower electrode, a dielectric stack, and an upper electrode. The dielectric stack of the capacitor of the embedded DRAM may comprise one of the above-described embodiments of the dielectric stack of the present invention. For example, the dielectric layer stack may include a first antiferroelectric layer, a second antiferroelectric layer, and a ferroelectric layer disposed between the first antiferroelectric layer and the second antiferroelectric layer.

The dielectric layer stack according to the above-described embodiment of the present invention can be applied to 3D NAND (three-dimensional NAND). For example, a 3D NAND may comprise a dielectric stack comprising: a columnar channel layer; word lines surrounding the pillar-type channel layer; and a tunneling dielectric layer between the pillar-type channel layer and the word line. The tunnel dielectric layer in the dielectric layer stack of the at least 3D NAND may include at least one of the first anti-ferroelectric layer, the second anti-ferroelectric layer, and the ferroelectric layer of the above-described embodiment of the present invention.

According to embodiments of the present invention, the switching voltage, capacitance and polarization of the dielectric layer stack may be controlled by controlling the composition ratio between the ferroelectric material and the antiferroelectric material. Thus, a volatile memory can be implemented.

Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.