阅读说明：本技术 半导体装置及半导体装置的制造方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 仲野逸人 于 2021-03-26 设计创作，主要内容包括：本发明提供一种半导体装置。其能够抑制封装部件的体积的增加,并且能够将封装部件恰当地渗入壳体内。在半导体装置中,具备被填充到收纳部(32b)而将半导体芯片(25a)和印刷电路基板(37b)封装的封装部件(40b)。封装部件(40b)的正面的封装面的从封装部件(40b)的背面起算的高度在印刷电路基板(37b)侧高于在半导体芯片(25a)侧。由此,封装部件(40b)渗入到收纳部(32b)内,从而能够将半导体芯片(25a)和印刷电路基板(37b)进行恰当地封装。因此,防止在封装部件(40b)内产生空隙等。(The invention provides a semiconductor device. Which can suppress an increase in volume of the package member and can appropriately infiltrate the package member into the case. A semiconductor device is provided with a packaging member (40b) which is filled in a housing section (32b) and packages a semiconductor chip (25a) and a printed circuit board (37 b). The height of the front surface of the package member (40b) from the back surface of the package member (40b) is higher on the printed circuit board (37b) side than on the semiconductor chip (25a) side. Thus, the packaging member (40b) penetrates into the housing section (32b), and the semiconductor chip (25a) and the printed circuit board (37b) can be appropriately packaged. Therefore, the generation of voids and the like in the package member (40b) is prevented.)

1. A semiconductor device is characterized by comprising:

a semiconductor chip having a main electrode on a front surface thereof;

an insulating circuit board having an insulating plate and a circuit pattern formed on a front surface of the insulating plate and provided on a back surface side of the semiconductor chip;

a case having a frame portion that has a rectangular opening in a plan view, is surrounded on all sides by inner wall surfaces, and houses the insulating circuit board, and a printed circuit board that is provided in a flat plate shape and protrudes from one of the inner wall surfaces toward the housing portion; and

a packaging member filled in the housing portion to package the semiconductor chip and the printed circuit board,

the height of the package surface of the front surface of the package component from the back surface of the package component is higher on the printed circuit board side than on the semiconductor chip side.

2. The semiconductor device according to claim 1,

the package face is monotonously inclined so as to become lower from the printed circuit substrate side to the semiconductor chip side.

3. The semiconductor device according to claim 1 or 2,

the printed circuit board is provided at least one corner portion of corner portions of the one inner wall surface side of the housing portion in a plan view.

4. The semiconductor device according to claim 1,

the one inner wall surface is one short side of the housing portion,

the printed circuit board protrudes from the one short side toward the housing section.

5. The semiconductor device according to claim 3,

the case further includes a first external connection terminal having a first internal connection portion at an end portion thereof, and the first internal connection portion protrudes toward the housing portion at a center portion of the one inner wall surface of the frame portion in a plan view and is sealed by the sealing member.

6. The semiconductor device according to claim 5,

the first internal connection portion is disposed at a position higher than the printed circuit substrate with respect to the back surface.

7. The semiconductor device according to claim 1,

the height of the package surface is higher on the semiconductor chip side than on a pair of long sides of the housing section when a cross section orthogonal to the one inner wall surface of the housing section is viewed.

8. The semiconductor device according to claim 2,

the package surface is monotonously inclined so as to become lower from the other inner wall surface side facing the one inner wall surface to the semiconductor chip side.

9. The semiconductor device according to claim 8,

the case further includes a second external connection terminal having a second internal connection portion at an end portion thereof, and the second internal connection portion protrudes toward the housing portion at a center portion of the other inner wall surface of the frame portion in a plan view, and is sealed by the sealing member.

10. The semiconductor device according to claim 1,

the package member contains an epoxy resin containing a filler as a main component.

11. The semiconductor device according to claim 10,

the frame portion contains a polyphenylene sulfide resin containing a filler as a main component.

12. The semiconductor device according to claim 11,

the printed circuit board has an insulating layer containing a glass epoxy resin or a phenol resin as a main component and a circuit layer formed on the front surface of the insulating layer and containing copper as a main component, and the printed circuit board has a resist film on the surface.

13. The semiconductor device according to claim 1,

a first short side of the insulated circuit board facing the one inner wall surface is separated from an end of the printed circuit board on the side of the housing portion by a first distance in a plan view.

14. The semiconductor device according to claim 13,

the insulating circuit board is rectangular in plan view and includes the first short side and a pair of long sides orthogonal to the first short side,

the frame portion of the housing further includes a pair of long-side inner wall surfaces orthogonal to the one inner wall surface,

the pair of long sides is separated from the pair of long side inner wall surfaces by a second distance in a plan view.

15. The semiconductor device according to claim 14,

the pair of long sides are parallel to the inner wall surfaces of the pair of long sides in a plan view,

the pair of long-side inner wall surfaces are flat.

16. The semiconductor device according to claim 14 or 15,

the insulating circuit substrate further includes:

a second short side facing the first short side in a plan view and shorter than the first short side; and

a pair of corner sides connecting the pair of long sides and the second short side and corresponding to a corner portion,

the housing portion of the housing further includes a pair of long-side inner wall surfaces that are connected to the pair of long-side inner wall surfaces, are separated from the pair of long-side inner wall surfaces, and are parallel to the pair of long-side inner wall surfaces.

17. The semiconductor device according to claim 14,

the semiconductor chip is provided to the circuit pattern except for a first stress concentration region set between a pair of first symmetrical lines parallel to the one inner wall surface and the other inner wall surface of the housing portion opposed to the inner wall surface and spaced apart from a center line passing through a center of the housing portion by a first object distance on the one inner wall surface side and on the other inner wall surface side, respectively, in a plan view.

18. The semiconductor device according to claim 17,

the circuit pattern is formed on the front surface of the insulating plate in a manner of crossing the first stress concentration region,

the semiconductor chip is disposed on at least one side of the circuit pattern with the first stress concentration region therebetween.

19. The semiconductor device according to claim 17 or 18,

the first target distance is 2% or more and 6% or less of a length between the one inner wall surface and the other inner wall surface of the housing portion.

20. The semiconductor device according to claim 17 or 18,

the insulated circuit board further includes:

a side circuit pattern formed on the front surface of the insulating plate so as to face the pair of long sides; and

and a wiring member, one end portion of which is bonded to a position outside the pair of long sides of the printed circuit board in a plan view, and the other end portion of which is bonded to the side circuit pattern so as to straddle the pair of long sides.

21. The semiconductor device according to claim 20,

the other end portion is formed in a second stress concentration region set between a pair of second symmetrical lines separated from the center line by a second object distance longer than the first object distance in a plan view.

22. The semiconductor device according to claim 21,

the second target distance is 10% or more and 15% or less of a length between the one inner wall surface and the other inner wall surface of the housing portion.

23. The semiconductor device according to claim 13,

the first distance is 4% or more and 16% or less of a length between the one inner wall surface and the other inner wall surface of the housing portion.

24. The semiconductor device according to claim 14,

the second distance is 4% to 16% of a length between the pair of long-side inner wall surfaces of the housing section.

25. A method for manufacturing a semiconductor device, comprising:

a preparation step of preparing a semiconductor chip having a main electrode on a front surface, an insulating circuit board having an insulating plate and a circuit pattern formed on the front surface of the insulating plate and provided on a back surface side of the semiconductor chip, a case having a frame portion having a housing portion having a rectangular opening in a plan view and surrounded by inner wall surfaces at all sides, and a printed circuit board provided in a flat plate shape and protruding from one of the inner wall surfaces toward the housing portion;

a housing step of housing the insulating circuit board in the housing section; and

a packaging step of discharging the packaging member to the housing portion to package the semiconductor chip and the printed circuit board,

in the sealing step, the sealing member is discharged from the discharge port after the discharge port from which the sealing member is discharged is set above the storage portion, and the sealing member is sealed by moving the discharge port in a direction perpendicular to the one inner wall surface while discharging the sealing member.

26. The method for manufacturing a semiconductor device according to claim 25,

in the sealing step, the discharge port is reciprocated between the one inner wall surface and the other inner wall surface located on the opposite side of the one inner wall surface in the storage portion.

27. The method for manufacturing a semiconductor device according to claim 25,

in the sealing step, the discharge port is formed to extend between one central portion of the one inner wall surface and another central portion of the other inner wall surface opposite to the one central portion in a plan view.

28. The method for manufacturing a semiconductor device, according to any one of claims 25 to 27,

in the sealing step, the ejection port reciprocates along a pair of long sides of the housing portion.

29. The method for manufacturing a semiconductor device according to claim 25,

the ejection amount of the ejection port per unit time of the sealing member is constant.

30. The method for manufacturing a semiconductor device according to claim 25,

the moving speed of the ejection port is constant.

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background

The semiconductor device includes a power device, and is used as a power conversion device. The power device includes a semiconductor chip. Examples of the Semiconductor chip include an Insulated Gate Bipolar Transistor (IGBT) and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Such a semiconductor device includes at least a semiconductor chip, a ceramic circuit board on which the semiconductor chip is disposed, and a printed circuit board. The printed circuit board inputs a gate voltage to the gate of the semiconductor chip at a predetermined timing. The semiconductor device includes a case for housing a ceramic circuit board and a printed circuit board on which semiconductor chips are arranged, and a package member for packaging the case. The case includes an external connection terminal having a connection portion at an end portion thereof, the connection portion being electrically connected to the ceramic circuit board in the case. The connection portion of the external connection terminal is also enclosed in the housing by an enclosing member.

Documents of the prior art

Patent document

Patent document 1: international publication No. 2017/163583

Disclosure of Invention

Technical problem

In a semiconductor device, a ceramic circuit board on which a semiconductor chip is disposed, a printed circuit board, a connection portion of an external connection terminal, and the like in a case are packaged by a packaging member. Such sealing is performed by filling a sealing member in a molten state into the case. However, depending on the arrangement position, shape, and the like of the ceramic circuit board, the printed circuit board, the connection portion of the external connection terminal, and the like in the case, a portion into which the sealing member cannot sufficiently penetrate may be generated. Such a portion becomes a void, and the reliability of the semiconductor device is lowered.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device and a method for manufacturing the semiconductor device, in which a package member can be appropriately infiltrated into a case.

Technical scheme

According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor chip having a main electrode on a front surface thereof; an insulating circuit board having an insulating plate and a circuit pattern formed on a front surface of the insulating plate and provided on a rear surface side of the semiconductor chip; (ii) a A case having a frame portion and a printed circuit board, the frame portion including a housing portion that is open in a rectangular shape in a plan view, is surrounded on all sides by inner wall surfaces, and houses the insulated circuit board, the printed circuit board being provided in a flat plate shape and protruding from one of the inner wall surfaces toward the housing portion; and a package member that is filled in the housing portion and packages the semiconductor chip and the printed circuit board, wherein a height of a package surface of a front surface of the package member from a rear surface of the package member is higher on the printed circuit board side than on the semiconductor chip side.

In addition, according to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including: a preparation step of preparing a semiconductor chip having a main electrode on a front surface, an insulating circuit board having an insulating plate and a circuit pattern formed on the front surface of the insulating plate and provided on a back surface side of the semiconductor chip, a case having a frame portion having a storage portion having a rectangular opening in a plan view and surrounded by inner wall surfaces at all sides, and a printed circuit board provided in a flat plate shape and protruding from one of the inner wall surfaces toward the storage portion; a housing step of housing the insulating circuit board in the housing section; and a sealing step of sealing the semiconductor chip and the printed circuit board by discharging the sealing member to the housing portion, wherein the sealing step sets a discharge port for discharging the sealing member above the housing portion, and then starts discharging the sealing member from the discharge port, thereby sealing the semiconductor chip by moving the discharge port in a direction perpendicular to the one inner wall surface while discharging the sealing member.

Effects of the invention

The semiconductor device and the method for manufacturing the semiconductor device having the above-described configuration can appropriately penetrate the package member into the case, suppress the occurrence of voids, and prevent the reliability from being lowered.

Drawings

Fig. 1 is a perspective view of a semiconductor device according to a first embodiment.

Fig. 2 is a circuit diagram showing an equivalent circuit formed by the semiconductor device of the first embodiment.

Fig. 3 is a flowchart illustrating a method of manufacturing the semiconductor device of the first embodiment.

Fig. 4 is a perspective view of a semiconductor unit included in the semiconductor device of the first embodiment.

Fig. 5 is a plan view of the front surface side of the case included in the semiconductor device of the first embodiment.

Fig. 6 is a plan view of the back surface side of the case included in the semiconductor device of the first embodiment.

Fig. 7 is a diagram for explaining a wiring step included in the method for manufacturing a semiconductor device according to the first embodiment.

Fig. 8 is a diagram for explaining a packaging process included in the method for manufacturing a semiconductor device according to the first embodiment.

Fig. 9 is a flowchart showing a packaging process included in the method for manufacturing a semiconductor device according to the first embodiment.

Fig. 10 is a diagram (1) for explaining a package member included in the semiconductor device of the first embodiment.

Fig. 11 is a diagram (2) for explaining a package member included in the semiconductor device of the first embodiment.

Fig. 12 is a flowchart showing a packaging process included in the method for manufacturing a semiconductor device according to the second embodiment.

Fig. 13 is a diagram for explaining a packaging process included in the method for manufacturing a semiconductor device according to the second embodiment.

Fig. 14 is a plan view of the semiconductor device according to the third embodiment.

Fig. 15 is a plan view of a main portion of a semiconductor device according to a third embodiment.

Description of the symbols

10: semiconductor device with a plurality of semiconductor chips

20,20 a: semiconductor unit

21: ceramic circuit board

22: insulating board

22a1,22a 2: long side

22a3,22a 4: short side

22a5,22a 6: corner edge

23a,23b,23c,23d,23e,23f,23g,23 h: circuit pattern

24: metal plate

25a,25 b: semiconductor chip

26a,26 b: lead frame

26a1,26a2,26b1,26b 2: joint part

26a3,26b 3: wiring part

27: joint member

28: heat radiation plate

29: block-shaped part

30: shell body

31: frame part

31a,31 b: frame long side

31c,31 d: short side of frame

32a,32b,32 c: storage part

32b1,32b2,32b3,32b4,32f,32g,32h,32 i: inner wall surface

32d,32 e: partition part

32h 1: upper inner wall surface

32h 2: step part

32h 3: lower inner wall surface

33a,33b,33 c: p terminal

33a1,33b1,33c 1: p connection part

34a,34b,34 c: n terminal

34a1,34b1,34c 1: n connecting part

35 a: u terminal

35a 1: u connecting part

35 b: v terminal

35b 1: v-shaped connecting part

35 c: w terminal

35c 1: w connection part

36a,36b,36 c: control terminal

37a,37b,37 c: printed circuit board

38,38a,38 b: bonding wire

39: binder

40a,40b,40 c: packaging component

41 a: output side region

41b,42 b: middle zone

41 c: input side region

42a,42 c: receive the long side region

50: dispenser

51: discharge port

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In this embodiment, the front surface (upper side) represents a surface (direction) facing upward of the semiconductor device 10 in fig. 1. Fig. 1, which is a perspective view, shows the front and side surfaces of a semiconductor device 10. For example, the sealing surfaces of the sealing members 40a,40b,40c that seal the housing portions 32a,32b,32c of the case 30 are the front surfaces (upper surfaces). The back surface (lower surface) represents a surface (direction) facing downward in the semiconductor device 10 of fig. 1. For example, the surface of the case 30 on which the heat dissipation plate 28 is disposed is the back surface (lower surface). The front (upper) and the back (lower) outside fig. 1 also mean the same directivity.

[ first embodiment ]

A semiconductor device according to a first embodiment will be described with reference to fig. 1 and 2. Fig. 1 is a perspective view of a semiconductor device according to a first embodiment, and fig. 2 is a circuit diagram showing an equivalent circuit formed by the semiconductor device according to the first embodiment. In fig. 1, only the main components are denoted by reference numerals.

As shown in fig. 1, the semiconductor device 10 includes a semiconductor unit (not shown), a case 30 for housing the semiconductor unit, and package members 40a,40b, and 40c for packaging the semiconductor unit. A heat sink 28 may be provided, and the heat sink 28 may be provided on the back surface of the case 30, in which the semiconductor unit is disposed (not shown in fig. 1, see fig. 11). The semiconductor unit will be described in detail later.

The case 30 is substantially rectangular in plan view, and includes a pair of long frame sides 31a,31b and a pair of short frame sides 31c,31 d. The case 30 includes storage portions 32a,32b, and 32c along the pair of frame long sides 31a and 31 b. The storage portions 32a,32b,32c are partitioned by partitions 32d,32e, respectively. The partitions 32d and 32e are provided parallel to the pair of frame short sides 31c and 31d and orthogonal to the pair of frame long sides 31a and 31 b. Therefore, each of the receiving portions 32a,32b,32c has a substantially rectangular shape in plan view. The semiconductor units are housed in the housing portions 32a,32b,32c, respectively, and are packaged by the packaging members 40a,40b,40c, respectively. As indicated by the broken line of the storage portion 32a, the storage portion 32a has an output side region 41a, an intermediate region 41b, and an input side region 41c set in this order from the frame long side 31b (short side on one side of the storage portion 32 a) side toward the frame long side 31a (short side on the other side of the storage portion 32 a) side. Although not shown, the output-side region 41a, the intermediate region 41b, and the input-side region 41c are similarly set in this order in the storage sections 32b and 32 c. As indicated by the broken line of the storage portion 32c, the storage portion 32c has a storage long-side region 42a, an intermediate region 42b, and a storage long-side region 42c in this order from the frame short side 31c (long side on one side of the storage portion 32 c) side toward the frame short side 31d (short side on the other side of the storage portion 32 c) side. Although not shown, the storage sections 32a and 32b are similarly provided with the storage long-side regions 42a and 42c and the intermediate region 42b in this order.

The packaging members 40a,40b,40c package the semiconductor units disposed in the housing portions 32a,32b,32 c. The encapsulation members 40a,40b,40c may be a thermosetting resin. The thermosetting resin is, for example, an epoxy resin, a phenol resin, a maleimide resin, a polyester resin. Epoxy resins are preferred. Further, the sealing members 40a,40b, and 40c may be added with a filler. The filler is an insulating ceramic having high thermal conductivity. Such fillers are, for example, silicon oxide, aluminum oxide, boron nitride or aluminum nitride. The filler content is 10 vol% or more and 70 vol% or less with respect to the entire package members 40a,40b, and 40 c.

The package face of the package component 40a,40b,40c is not parallel to the back face of the package component 40a,40b,40 c. That is, the height of the package surface of the package members 40a,40b,40c from the back surface differs in each region within the housing portions 32a,32b,32 c. Specifically, in the long side (housing long side) direction of the housing portions 32a,32b,32c, the height of the output side region 41a from the back side to the front side as the thickness direction of the semiconductor chips 25a,25b is higher than the height of the intermediate region 41 b. The heights of the package surfaces of the package members 40a,40b, and 40c in the output side region 41a, the intermediate region 41b, and the input side region 41c will be described in detail below with reference to fig. 10. In addition, in the short side (storage short side) direction of the storage sections 32a,32b,32c, the height of the middle region 42b from the back surface to the front surface as the thickness direction of the semiconductor chips 25a,25b is higher than the height of the storage long side regions 42a,42 c. The heights of the package surfaces of the package members 40a,40b,40c in the housing long-side region 42a, the intermediate region 42b, and the housing long-side region 42c will be described in detail below with reference to fig. 10.

In the case 30, an input terminal is disposed on the frame long side 31 a. Specifically, the input terminals are P terminals 33a,33b,33c and N terminals 34a,34b,34c provided along the frame long side 31 a. In case 30, an output terminal is disposed on frame long side 31b, and frame long side 31b is the opposite side of the front surface of case 30 on which the input terminal is disposed. Specifically, the output terminals are a U terminal 35a, a V terminal 35b, and a W terminal 35c provided along the frame long side 31 b. The P terminal 33a, the N terminal 34a, and the U terminal 35a are provided so as to sandwich the housing portion 32 a. The housing 30 is provided with a control terminal 36a on the U terminal 35a side of the housing 32 a. The P terminal 33b, the N terminal 34b, and the V terminal 35b are provided so as to sandwich the housing portion 32 b. The housing 30 is provided with a control terminal 36b on the V terminal 35b side of the housing 32 b. The P terminal 33c, the N terminal 34c, and the W terminal 35c are provided so as to sandwich the housing portion 32 c. The housing 30 is provided with a control terminal 36c on the W terminal 35c side of the housing portion 32 c. The other end portions of the terminals are electrically connected to the semiconductor chips of the semiconductor units housed in the housing portions 32a,32b, and 32 c. For example, the other end portions of the control terminals 36a,36b, and 36c are electrically connected to control electrodes such as gate electrodes of the semiconductor chips, respectively. The other end portions of the P terminals 33a,33b,33c, the N terminals 34a,34b,34c, the U terminal 35a, the V terminal 35b, and the W terminal 35c are electrically connected to main electrodes such as an emitter electrode (or a source electrode) and a collector electrode (or a drain electrode) of the semiconductor chip, respectively.

The heat sink 28 is flat and rectangular in plan view. The heat sink 28 may cover the housing portions 32a,32b, and 32c of the case 30 from the back surface in a plan view (see fig. 11). The heat sink 28 is made of a metal having excellent thermal conductivity. Such materials are, for example, aluminum, iron, silver, copper or alloys comprising at least one of these. Examples of such an alloy include metal composite materials such as aluminum-silicon carbide (Al-SiC) and magnesium-silicon carbide (Mg-SiC). In order to improve corrosion resistance, a material such as nickel may be formed on the surface of the heat sink 28 by plating or the like.

A cooling unit (not shown) may be attached to the rear surface of the case 30 to which the heat dissipation plate 28 is attached. The cooling means in this case is made of, for example, a metal having excellent thermal conductivity. The metal is aluminum, iron, silver, copper, or an alloy including at least one of them, or the like. The cooling unit is a radiator or a water jacket having 1 or more fins. The heat radiation plate 28 may be integrated with such a cooling unit.

Such a semiconductor device 10 includes an equivalent circuit as a three-phase inverter circuit as shown in fig. 2. Fig. 2 shows a case where an RC (reverse connection) -IGBT is used, which is a semiconductor chip provided in a semiconductor unit. In addition, the symbols denoted by RC-IGBTs in fig. 2 correspond to the semiconductor chips 25a,25b included in the semiconductor unit 20 shown in fig. 4. Each arm portion includes two semiconductor chips 25a and 25b connected in parallel. Each of the semiconductor units 20 constituting each phase includes four semiconductor chips 25a and 25 b.

In the semiconductor device 10, the P terminals 33a,33b,33c are electrically connected to the collector electrodes of the semiconductor chips 25b in the upper arm portions of the respective semiconductor units in the housing portions 32a,32b,32c, respectively. The U terminal 35a, the V terminal 35b, and the W terminal 35c are electrically connected to the emitter electrode of the semiconductor chip 25b of the upper arm portion and the collector electrode of the semiconductor chip 25a of the lower arm portion of each semiconductor unit in the housing portions 32a,32b,32 c. In addition, N terminals 34a,34b,34c are electrically connected to emitter electrodes of the semiconductor chip 25a of the lower arm portion of each semiconductor unit in the housing portions 32a,32b,32c, respectively. Thereby, the semiconductor device 10 functions as an inverter.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to fig. 3. Fig. 3 is a flowchart illustrating a method of manufacturing the semiconductor device of the first embodiment. First, a preparation process for preparing components necessary for the semiconductor device 10 is performed (step S10 in fig. 3). As an example of necessary components, a semiconductor chip, a ceramic circuit board, a case 30, a package member, a lead frame, a heat sink 28, and the like are prepared. Then, the semiconductor chip and the lead frame are bonded to a predetermined portion of the ceramic circuit board by a bonding member. The semiconductor unit 20 thus prepared will be described with reference to fig. 4. Fig. 4 is a perspective view of a semiconductor unit included in the semiconductor device of the first embodiment. The semiconductor unit 20 includes a ceramic circuit board 21, and semiconductor chips 25a and 25b and lead frames 26a and 26b arranged on the front surface of the ceramic circuit board 21 via a bonding member 27 (see fig. 11).

The ceramic circuit substrate 21 includes an insulating plate 22, a plurality of circuit patterns 23a,23b,23c,23d,23e,23f,23g disposed on the front surface of the insulating plate 22, and a metal plate 24 disposed on the rear surface of the insulating plate 22. The corners of the insulating plate 22 and the metal plate 24 may also be chamfered. The plurality of circuit patterns 23a,23b,23c,23d,23e,23f,23g and the metal plate 24 have an outer shape smaller than that of the insulating plate 22 in a plan view, and are formed inside the insulating plate 22. The insulating plate 22 is made of a material having insulation properties, low thermal resistance, and excellent thermal conductivity. Such an insulating plate 22 is made of ceramic. The ceramic is alumina, aluminum nitride, silicon nitride, etc. The thickness of the insulating plate 22 is 0.2mm to 2.5 mm.

The plurality of circuit patterns 23a,23b,23c,23d,23e,23f, and 23g are made of a material having excellent conductivity. Such a material is, for example, copper, aluminum, or an alloy including at least one of these. The thickness of the circuit patterns 23a,23b,23c,23d,23e,23f,23g is preferably 0.10mm or more and 2.00mm or less, and more preferably 0.20mm or more and 1.00mm or less. The circuit patterns 23a,23b,23c,23d,23e,23f, and 23g may be plated with a material having excellent corrosion resistance. Such a material is, for example, nickel or an alloy containing nickel. The number, arrangement position, and shape of the circuit patterns 23a,23b,23c,23d,23e,23f, and 23g shown in fig. 4 are merely examples, and may be selected by appropriate design without being limited to this.

The metal plate 24 is made of a metal having excellent thermal conductivity. Such a material is, for example, copper, aluminum, or an alloy including at least one of these. The thickness of the metal plate 24 is preferably 0.10mm or more and 2.00mm or less, and more preferably 0.20mm or more and 1.00mm or less. In order to improve corrosion resistance, a material such as nickel may be formed on the surface of the metal plate 24 by plating or the like, for example.

The semiconductor chips 25a,25b are power devices made of silicon, silicon carbide, or gallium nitride. As described earlier, the semiconductor chips 25a,25b are RC-IGBTs. The RC-IGBT is formed by arranging an IGBT (insulated gate bipolar transistor) as a switching element and a FWD (Free Wheeling Diode) as a Diode element in one chip. Such semiconductor chips 25a and 25b include, for example, a collector electrode (positive electrode) and an anode electrode as main electrodes on the back surface, and a gate electrode as a control electrode and an emitter electrode (negative electrode) and a cathode electrode as main electrodes on the front surface. Alternatively, the semiconductor chip 25a (or the semiconductor chip 25b) may have a switching element and a diode element as different chips. In this case, the switching element is a power MOSFET, an IGBT, or the like. The semiconductor chip 25a (or the semiconductor chip 25b) includes, for example, a drain electrode (a positive electrode, a collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode as a control electrode and a source electrode (a negative electrode, an emitter electrode in an IGBT) as main electrodes on the front surface. The Diode element is a FWD such as an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) Diode. Such a semiconductor chip 25a (or semiconductor chip 25b) has a cathode electrode as a main electrode on the back surface and an anode electrode as a main electrode on the front surface. The thickness of the semiconductor chips 25a,25b is 80 μm or more and 500 μm or less, for example, 200 μm. Fig. 4 shows a case where two semiconductor chips 25a constituting the lower arm portion and two semiconductor chips 25b constituting the upper arm portion are arranged on the ceramic circuit board 21, respectively. Not limited to this example, a plurality of sets may be configured by appropriate design.

The back surfaces of the semiconductor chips 25a,25b are bonded to the predetermined circuit patterns 23a,23c by bonding members 27. The joining member 27 is made of solder or a sintered body. The solder is composed of a lead-free solder containing a predetermined alloy as a main component. The sintering material used in the bonding by sintering is, for example, a powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum.

The lead frames 26a,26b are made of a material having excellent conductivity. Such a material is, for example, copper, aluminum, or an alloy including at least one of these. The thickness of the lead frames 26a,26b is preferably 0.2mm or more and 4.0mm or less, and more preferably 0.5mm or more and 1.5mm or less. In order to improve corrosion resistance, a material such as nickel may be formed on the surfaces of the lead frames 26a and 26b by plating or the like, for example. Such lead frames 26a,26b include bonding portions 26a1,26b1, wiring portions 26a3,26b3, and bonding portions 26a2,26b2 in an integrally bonded manner. The bonding portions 26a1,26b1 are bonded to the negative electrodes on the front surfaces of the semiconductor chips 25a,25b by bonding members 27. The bonding portions 26a2,26b2 are bonded to the circuit patterns 23a,23b by bonding members 27. The wiring portions 26a3,26b3 electrically connect such joining portions 26a1,26a2,26b1,26b 2. The wiring portions 26a3,26b3 are positioned parallel to the front surface of the ceramic circuit board 21.

Next, the case 30 prepared in the preparation step will be described with reference to fig. 5 and 6. Fig. 5 is a plan view of the front surface side of the case included in the semiconductor device of the first embodiment, and fig. 6 is a plan view of the back surface side of the case included in the semiconductor device of the first embodiment.

The housing 30 is rectangular in plan view, and includes a frame portion 31 surrounding an opening penetrating from the front surface to the rear surface of the housing 30, P terminals 33a,33b,33c, N terminals 34a,34b,34c, U terminals 35a, V terminals 35b, W terminals 35c, control terminals 36a,36b,36c, and printed circuit boards 37a,37b,37c attached to the frame portion 31. The frame 31 has a flat plate-like outer shape and includes a pair of frame long sides 31a,31b facing each other and a pair of frame short sides 31c,31d orthogonal to and facing the frame long sides 31a,31 b. The frame 31 is open along the frame long sides 31a,31b and the frame short sides 31c,31d between the inner wall surfaces of the frame long sides 31a,31b and the inner wall surfaces of the frame short sides 31c,31 d. That is, the opening has a rectangular shape parallel to the frame 31 at right angles in a plan view. The frame portion 31 includes three receiving portions 32a,32b, and 32c partitioned by partitions 32d and 32e through the openings along the frame long sides 31a and 31 b. The housing portion 32a further includes: a pair of opposed inner wall surfaces 32f,32g (see fig. 5) on the long side of the storage and a pair of opposed inner wall surfaces 32h,32i (see fig. 6) on the short side of the storage, which are orthogonal to the inner wall surfaces 32f,32 g. Although only the housing portion 32a is denoted by a reference numeral, the housing portions 32b and 32c similarly include inner wall surfaces 32f and 32g on the long sides and inner wall surfaces 32h and 32i on the short sides. The shapes of the housing portions 32a,32b, and 32c in plan view correspond to the shapes of the ceramic circuit boards 21 of the semiconductor units 20. The receiving portions 32a,32b, and 32c of the present embodiment are chamfered at their corners in a plan view. The chamfer of one inner wall surface 32i on which the P-junctions 33a1,33b1,33c1 and the N-junctions 34a1,34b1,34c1, which will be described later, are arranged, is larger than the chamfer of the other inner wall surface 32h on which the printed circuit boards 37a,37b,37c are arranged. That is, the length of the other inner wall surface 32h is larger than the length of the one inner wall surface 32 i. Not limited to this case, but may be rectangular in shape.

The frame portion 31 is formed by injection molding in which a thermoplastic resin containing a filler is injected after the P terminals 33a,33b,33c, the N terminals 34a,34b,34c, the U terminals 35a, the V terminals 35b, the W terminals 35c, the control terminals 36a,36b,36c, and the printed circuit boards 37a,37b,37c are provided in a predetermined mold. Examples of such resins include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, Polyamide (PA) resin, and acrylonitrile-butadiene-styrene (ABS) resin. The filler is silicon oxide, aluminum oxide, boron nitride or aluminum nitride. Specifically, a PPS resin containing an arbitrary filler is used for the frame portion 31.

The P terminals 33a,33b, and 33c are integrally formed along the frame long side 31a of the frame 31 in correspondence with the receiving portions 32a,32b, and 32c (inner wall surface 32 i). The P terminals 33a,33b,33c have P connections 33a1,33b1,33c1 at the ends. The P-connecting portions 33a1,33b1, and 33c1 are flat plate-shaped and project perpendicularly from the inner wall surface 32i into the accommodating portions 32a,32b, and 32c, respectively.

The N terminals 34a,34b, and 34c are integrally formed along the frame long side 31a of the frame 31 in correspondence with the receiving portions 32a,32b, and 32c (inner wall surface 32 i). The N terminals 34a,34b,34c are adjacent to the P terminals 33a,33b,33c, respectively. In addition, the N terminals 34a,34b, and 34c protrude further outward than the P terminals 33a,33b, and 33 c. The N terminals 34a,34b, and 34c include N connection portions 34a1,34b1, and 34c1 at the ends thereof. The N-connecting portions 34a1,34b1, and 34c1 are flat plate-shaped and project perpendicularly from the inner wall surface 32i into the housing portions 32a,32b, and 32 c. In addition, N-junctions 34a1,34b1,34c1 are also adjacent to P-junctions 33a1,33b1,33c1, respectively.

The U terminal 35a, the V terminal 35b, and the W terminal 35c are integrally formed on the front surface of the frame 31 along the frame long side 31b in correspondence with the receiving portions 32a,32b, and 32c (inner wall surface 32h), respectively. The U terminal 35a, the V terminal 35b, and the W terminal 35c include a U link 35a1, a V link 35b1, and a W link 35c1 at their ends. The U-link 35a1, the V-link 35b1, and the W-link 35c1 are flat plate-shaped and protrude into the housing portions 32a,32b, and 32c from substantially the center portion of the inner wall surface 32h, perpendicularly to the inner wall surface 32 h. The U terminal 35a, the V terminal 35b, and the W terminal 35c face the P-links 33a1,33b1,33c1 and the N-links 34a1,34b1,34c1 through the receiving portions 32a,32b, and 32c, respectively.

The control terminals 36a,36b, and 36c are respectively rod-shaped and have a circular or rectangular cross section. One end of each of the control terminals 36a,36b, and 36c is formed in plurality along the inner wall surface 32h of the housing portions 32a,32b, and 32c on the front surface of the frame portion 31 so as to extend upward in the vicinity of the inner wall surface 32 h. The other ends of the control terminals 36a,36b,36c are buried in the housing and electrically connected to the printed circuit boards 37a,37b,37c in the housing.

The P terminals 33a,33b, and 33c, the N terminals 34a,34b, and 34c, the U terminal 35a, the V terminal 35b, the W terminal 35c, and the control terminals 36a,36b, and 36c are made of a material having excellent conductivity. Such a material is, for example, copper, aluminum, or an alloy including at least one of these. The thicknesses of the P terminals 33a,33b,33c, the N terminals 34a,34b,34c, and the U terminals 35a, the V terminals 35b, and the W terminals 35c are preferably 0.2mm or more and 4.0mm or less, and more preferably 0.5mm or more and 1.5mm or less. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surfaces of the P terminals 33a,33b,33c, the N terminals 34a,34b,34c, the U terminal 35a, the V terminal 35b, the W terminal 35c, and the control terminals 36a,36b,36c by plating or the like.

The printed circuit boards 37a,37b, and 37c are flat plates, and are disposed on the inner wall surfaces 32h of the housing portions 32a,32b, and 32c on the side of the U-connection portion 35a1, the V-connection portion 35b1, and the W-connection portion 35c1, which are output terminals. The printed circuit boards 37a,37b, and 37c are provided on the inner wall surfaces 32h at the corners of the inner wall surfaces 32h and the accommodating portions 32a,32b, and 32c on both sides of the U-joint portion 35a1, the V-joint portion 35b1, and the W-joint portion 35c1, which are output terminals. The printed circuit boards 37a,37b,37c protrude from the inner wall surface 32h toward the accommodating portions 32a,32b,32c perpendicularly to the inner wall surface 32h so that the back surfaces of the printed circuit boards 37a,37b,37c face the openings of the accommodating portions 32a,32b,32 c. In addition, the height of the printed circuit boards 37a,37b,37c from the rear surface of the housing 30 (the package members 40a,40b,40c) is lower than the height of the U-connection portion 35a1, the V-connection portion 35b1, and the W-connection portion 35c1 from the rear surface of the housing 30 (the package members 40a,40b,40 c). Specifically, the heights of the printed circuit boards 37a,37b, and 37c from the back surface to the front surface in the thickness direction of the semiconductor chips 25a and 25b are lower than the heights of the U-connection portion 35a1, the V-connection portion 35b1, and the W-connection portion 35c 1.

The printed circuit boards 37a,37b, and 37c have a multilayer structure in which an insulating layer and a circuit layer made of a conductive material are laminated on the insulating layer. The insulating layer contains a glass epoxy resin or a phenol resin as a main component. The conductive material of the circuit layer contains, for example, copper as a main component. In order to improve corrosion resistance, the surfaces of the printed circuit boards 37a,37b, and 37c are also covered with a resist film, and a plurality of electrodes electrically connected to the circuit layers are arranged on the front surface. In addition, the printed circuit boards 37a,37b, and 37c have a plurality of through holes formed therein. The other ends of the control terminals 36a,36b,36c are inserted into the through-holes, respectively. At this time, the control terminals 36a,36b, and 36c are electrically connected to the printed circuit boards 37a,37b, and 37c by being bonded to the through holes by solder. Alternatively, the control terminals 36a,36b, and 36c may be press-fitted into the through-holes. The control terminals 36a,36b, and 36c are inserted into through holes in the frame 31. Such printed circuit boards 37a,37b, and 37c are also integrally formed with the frame 31.

Next, a housing step of housing the semiconductor unit 20 in the housing portions 32a,32b, and 32c of the case 30 and electrically connecting the terminals to the semiconductor unit 20 is performed (step S11 in fig. 3). The semiconductor units 20 are arranged on the heat dissipation plate 28 so as to correspond to the housing portions 32a,32b, and 32c, respectively, via the bonding members 27. On the heat sink 28 on which the semiconductor unit 20 is disposed, the case 30 is disposed so that the semiconductor unit 20 is housed in the housing portions 32a,32b,32 c. The case 30 is joined to the heat sink 28 by an adhesive 39 (see fig. 11).

In the semiconductor unit 20 thus housed in the housing portion 32a, the semiconductor chips 25a,25b are separated from the respective inner wall surfaces constituting the housing portion 32a toward the central portion side of the housing portion 32 a. The semiconductor chips 25a and 25b are separated from the inner wall surface 32h provided with the printed circuit board 37a toward the center portion of the housing portion 32 a. In the semiconductor unit 20 housed in the housing portions 32b,32c, similarly, the semiconductor chips 25a,25b are separated from the respective inner wall surfaces constituting the housing portions 32b,32c toward the central portion side.

The N connection portion 34a1 of the semiconductor unit 20 housed in the housing portion 32a is electrically connected to the circuit pattern 23b via the block portion 29 (see fig. 8 and 11). The P connection portion 33a1 is electrically connected to the circuit pattern 23c through the block portion 29. Further, the U-connection portion 35a1 is electrically connected to the circuit pattern 23a through the block portion 29. Similarly, the N connection portion 34b1 of the semiconductor unit 20 housed in the housing portion 32b is electrically connected to the circuit pattern 23b through the block portion 29. The P connection portion 33b1 is electrically connected to the circuit pattern 23c through the block portion 29. Further, the V-connection portion 35b1 is electrically connected to the circuit pattern 23a through the block portion 29. Similarly, the N connection portion 34c1 of the semiconductor unit 20 housed in the housing portion 32c is electrically connected to the circuit pattern 23b via the block portion 29. The P connection portion 33c1 is electrically connected to the circuit pattern 23c through the block portion 29. Further, the W connection portion 35c1 is electrically connected to the circuit pattern 23a through the block portion 29. The back surface side of each block portion 29 may be bonded to the predetermined circuit patterns 23a,23c by a bonding member such as solder or sintered metal in advance. Further, each block portion 29 may be joined to the P-connecting portions 33a1,33b1,33c1, the N-connecting portions 34a1,34b1,34c1, the U-connecting portions 35a1, the V-connecting portions 35b1, and the W-connecting portions 35c1 of each terminal by a joining member such as solder and/or sintered metal. Alternatively, each block 29 may be directly bonded to the P-link 33a1,33b1,33c1, the N-link 34a1,34b1,34c1, the U-link 35a1, the V-link 35b1, and the W-link 35c1 of each terminal by laser or the like. The block 29 is made of a material having excellent conductivity. Such a material is, for example, copper, aluminum, or an alloy including at least one of these. The thickness of the block 29 corresponds to the gap between each connection portion and each circuit pattern. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surface of the block portion 29 by plating or the like.

Next, a wiring step of wiring the semiconductor unit 20 housed in the case 30 and the printed circuit boards 37a,37b, and 37c via bonding wires is performed (step S12 in fig. 3). This wiring step will be described with reference to fig. 7. Fig. 7 is a diagram for explaining a wiring process included in the method for manufacturing a semiconductor device according to the first embodiment. In step S11, the printed circuit board 37a and the gate electrodes of the semiconductor chips 25a are electrically connected to each other by the bonding wires 38 in the housing portion 32a of the case 30 housing the semiconductor unit 20. The printed circuit board 37a is electrically connected to the gate electrode of each semiconductor chip 25b by a bonding wire 38. Similarly, the housing portions 32b and 32c of the case 30 housing the semiconductor unit 20 are electrically connected to the printed circuit boards 37b and 37c and the gate electrode of the semiconductor chip 25a by the bonding wire 38. The green sheets 37b and 37c are electrically connected to the gate electrode of the semiconductor chip 25b by bonding wires 38.

Next, a sealing process of sealing the housing portions 32a,32b,32c of the case 30 with a sealing member is performed (step S13 in fig. 3). This sealing process will be described with reference to fig. 8 and 7. Fig. 8 is a diagram for explaining a packaging process included in the method for manufacturing a semiconductor device according to the first embodiment. Fig. 8 is a cross-sectional view of the one-dot chain line X-X of fig. 7. But illustration of the lead frames 26a,26b and the bonding wires 38 is omitted. Although fig. 8 shows the case of the housing portion 32b, the same applies to the housing portions 32a and 32 c.

A sealing device is used for sealing the housing portions 32a,32b,32c of the case 30. The sealing device includes, for example, a dispenser that ejects the sealing member from the ejection port, and a control device (e.g., a CPU (Central Processing Unit)) that controls the moving speed of the dispenser, the ejection amount of the sealing member per Unit time, and the like. The sealing member can use a liquid thermosetting resin. The viscosity of such a material is 1000 mPas or more and 70000 mPas or less. In addition, a two-component resin including a main agent and a curing agent may also be used as the encapsulating member. For example, the epoxy resin base compound and curing agents such as polyamine curing agents, acid anhydride curing agents, phenolic curing agents, and thiol curing agents can be used. For example, the dispenser supplies the main agent and the curing agent from different tubes into the same syringe, mixes them, and ejects them. For example, in the case of the package housing portion 32b, the dispenser 50 is caused to reciprocate between the start position ("S") and the folded position ("T") shown in fig. 7 and 8 and to eject the molten package member from the ejection port 51. Note that the scanning position of the dispenser 50 is reciprocated at the same position between "S" to "T" along the arrow of the dotted line shown in fig. 7 and 8. "S" is above the V-connecting portion 35b1 of the V terminal 35 b. Similarly, "S" is above the U-connection portion 35a1 of the U terminal 35a and the W-connection portion 35c1 of the W terminal 35c in the case of the housing portions 32a,32 c. "T" is a position facing "S" through the receiving portions 32a,32b, and 32 c.

At this time, in the sealing device, the sealing member can be discharged from the discharge port 51 so that the discharge amount per unit time of the discharged sealing member is changed. Alternatively, the scanning (moving) speed of the dispenser 50 can be controlled at will. After the wiring step of step S12, if the case 30 containing the semiconductor unit 20 is provided in the packaging device, the packaged components are discharged from the discharge port 51 to the containing portions 32a,32b, and 32c by the dispenser 50. The encapsulating members thus filled in the housing portions 32a,32b,32c are cured by the reaction of the main agent and the curing agent, whereby the housing portions 32a,32b,32c are encapsulated by the encapsulating members 40a,40b,40c, and the semiconductor device 10 shown in fig. 1 is obtained. Further, if necessary, heat may be applied to promote curing.

Here, details of the packaging process in step S13 in fig. 3 will be described with reference to fig. 9 to 11 and fig. 7 and 8. Fig. 9 is a flowchart showing a packaging process included in the method for manufacturing a semiconductor device according to the first embodiment. Fig. 10 and 11 are diagrams for explaining a package member included in the semiconductor device according to the first embodiment. Although the sealing process for the housing portion 32b is described in fig. 9, the sealing process is similarly performed for the housing portions 32a and 32 c. Fig. 10 and 11 are views for explaining the shape of the sealing member 40b with respect to the housing portion 32 b. Therefore, in fig. 10 and 11, only the components necessary for determining the shape of the package component 40b are described for the semiconductor unit 20. Fig. 10 (a) is a cross-sectional view taken along a dashed line Y-Y in fig. 7 when packaged, and fig. 10 (B) is a cross-sectional view taken along a dashed line X-X in fig. 7 when packaged. In fig. 10, only the sealing member 40b is shown, and the sealing members 40a and 40c are also similar. Fig. 10 (a) corresponds to the accommodation long-side regions 42a and 42c and the intermediate region 42b shown in fig. 1. Fig. 10 (B) and 11 correspond to the output side region 41a, the intermediate region 41B, and the input side region 41c shown in fig. 1. Fig. 11 is an enlarged view of the right side of fig. 10 (B).

As shown in fig. 7 and 8, first, the dispenser 50 is set at a start position ("S") on the inner wall surface 32h side of the storage section 32b (step S13a of fig. 9). For example, the start position ("S") may be, as shown in fig. 8, above the printed circuit board 37b (and the V-connection portion 35b1) when viewed from the side of the inner wall surface 32g (the storage long side) parallel to the moving direction of the dispenser 50. At this time, the ejection port 51 of the dispenser 50 is directed toward the semiconductor unit 20. Then, in the state set to "S", the dispenser 50 starts ejecting the sealing member in a molten state from the ejection port 51 (step S13b of fig. 9). The discharge amount of the sealing member discharged from the discharge port 51 per unit time is, for example, 0.5m1/sec or more and 4.0m1/sec or less. Then, the dispenser 50 moves from "S" to the folded position ("T") at a predetermined speed while ejecting the package (step S13c of fig. 9). For example, the folded position ("T") may be, as shown in fig. 8, above the N-connection portion 34b1 (and the P-connection portion 33b1) extending from the side surface opposite to the printed circuit board 37b when viewed from the storage long side. The predetermined speed at this time is, for example, 0.5 cm/sec or more and 4.0 cm/sec or less. Then, if the dispenser 50 reaches "T", the moving direction is converted into a direction toward the "S" side (step S13d of fig. 9). At this time, the control device of the packing device increases the number of times of movement of the dispenser 50 between "S" and "T" once. Note that the number of times of movement between "S" and "T" is calculated as the number of times of movement that increases once every movement from "S" to "T" or from "T" to "S". Then, the dispenser 50 moves from "T" to "S" at a predetermined speed while ejecting the package (step S13e of fig. 9). The predetermined speed at this time may be 0.5 cm/sec or more and 4.0 cm/sec or less, as the speed of movement from "S" to "T".

Then, if the dispenser 50 reaches "S", the moving direction is converted to a direction toward "T" side, and stays for a predetermined time. (step S13f of FIG. 9). At this time, the control device of the packing device increases the number of times of movement of the dispenser 50 between "S" and "T" once. The dispenser 50 also ejects the sealing member from the ejection port 51 during the stay predetermined time. The predetermined time in this case is 0.5 seconds to 2.0 seconds. Therefore, the filling amount of the sealing member becomes larger in the vicinity of "S" including "S" of the housing portion 32b than in other portions. Then, the dispenser 50 moves from "S" toward "T" at a predetermined speed while ejecting the package components (step S13g of fig. 9).

Then, if the dispenser 50 reaches "T", the moving direction is converted into a direction toward the "S" side (step S13h of fig. 9). At this time, the control device of the packing device increases the number of times of movement between "S" and "T" of the dispenser 50 once. Then, the control device determines whether or not the total number of times of movement up to this point exceeds a predetermined number of times (step S13i in fig. 9). When the total number of moves is equal to or less than the predetermined number of times (in the case of not exceeding), step S13e is executed again. In this manner, the dispenser 50 reciprocates between "S" and "T". When the total number of moves exceeds the predetermined number, step S13j is executed. The total number of movements is set to four or more and ten or less, and two or more and five or less reciprocations are set between "S" and "T".

Then, the dispenser 50 moves from "T" to "S" at a predetermined speed while ejecting the package (step S13j of fig. 9). Then, if the dispenser 50 reaches an arbitrary stop position, the ejection and movement are stopped (step S13k of fig. 9). The stop position may be "S", but may be between "S" and "T", and is not necessarily "S". And, if the sealing member is solidified, the housing portion 32b is sealed by the sealing member 40 b. In addition, as described above, the housing portions 32a,32c are also sealed by the sealing members 40a,40 c.

When viewed from the side of the inner wall surface 32i or the inner wall surface 32h (the frame short sides 31c,31d side) perpendicular to the moving direction of the dispenser 50, as shown in fig. 10 a, the height of the package member 40b of the package storage portion 32b from the bottom surface of the package member 40b of the intermediate region 42b is higher than the height of the package member 40b of the storage long side regions 42a,42c from the bottom surface thereof. Specifically, the height of the intermediate region 42b from the back surface to the front surface in the thickness direction of the semiconductor chips 25a and 25b is higher than the height of the housing long-side regions 42a and 42 c. When the housing portion 32b is filled with the sealing member 40b, the dispenser 50 is reciprocated along the inner wall surfaces 32f,32g above the intermediate section 42b, and the sealing member is discharged to the intermediate section 42 b. Therefore, the package components discharged to the intermediate section 42b flow to the housing long-side regions 42a and 42c on both sides of the intermediate section 42 b. By repeating this operation, the amount of the package members in the intermediate section 42b becomes larger than the amount of the package members in the accommodation long-side regions 42a and 42 c. In the solidified package member 40b, the thickness of the intermediate region 42b is larger than the thickness of the receiving long-side regions 42a and 42c, and is monotonically inclined so as to decrease from the intermediate region 42b to the receiving long-side regions 42a and 42 c.

Further, when viewed from the side of the inner wall surface 32f or the inner wall surface 32g (the storage long side) parallel to the moving direction of the dispenser 50, as shown in fig. 10 (B), the height of the package member 40B of the package storage portion 32B from the bottom surface of the package member 40B of the output side region 41a is higher than the height from the bottom surface of the package member 40B of the intermediate region 41B. Specifically, the height of the output side region 41a from the back surface to the front surface as the thickness direction of the semiconductor chips 25a,25b is higher than the height of the intermediate region 41 b. In addition, the height from the bottom surface of the package part 40b of the intermediate region 41b is equal to or higher than the height from the bottom surface of the package part 40b of the input side region 41 c. Specifically, the height of the intermediate region 41b from the back surface to the front surface in the thickness direction of the semiconductor chips 25a,25b is the same as or higher than the height of the input side region 41 c. As described above, when the package member 40b is filled in the housing portion 32b, the dispenser 50 is reciprocated along the inner wall surfaces 32f,32g above the intermediate section 42b (fig. 10 a) and the package member is discharged to the intermediate section 42 b. In this case, the dispenser 50 stays at the position for a predetermined time when the direction is switched in the output side region 41a including the start position ("S"). On the other hand, the dispenser 50 does not stay at the time of switching the direction in the input side region 41c including the switchback position ("T"), but moves to the "S" side. By repeating this, the amount of the package components of the output side region 41a is larger than that of the intermediate region 41 b. In addition, the amount of the packing components of the intermediate region 41b is equal to or more than that of the input side region 41 c. In the solidified encapsulating member 40b, the thickness (volume) decreases from the output side region 41a to the input side region 41c, and is monotonically inclined so as to decrease from the output side region 41a to the intermediate region 41 b. In addition, the center region 41b is equal to or monotonically inclined in a decreasing manner toward the input side region 41c side.

Note that it is possible to change the thickness of the enclosing member 40b according to the position thereof by changing the ejection amount of the dispenser 50 per unit time. For example, when the dispenser 50 is reciprocated at a constant speed along the inner wall surfaces 32f,32g above the intermediate area 42b ((a) of fig. 10), the ejection amount per unit time is increased in the output side area 41a, and the ejection amount is decreased as it is decreased in the intermediate area 41b and the input side area 41 c. This results in the package member 40B shown in fig. 10 (B). Alternatively, it is also possible to vary the thickness of the enclosing member 40b depending on its position by varying the speed of movement of the dispenser 50. For example, when the dispenser 50 is reciprocated along the inner wall surfaces 32f,32g above the intermediate area 42b ((a) of fig. 10), the moving speed of the dispenser 50 is slowed down in the output side area 41a, and the moving speed is increased as it is increased in the intermediate area 41b, the input side area 41 c. Note that the discharge amount per unit time is constant. In this case, a package member 40B as shown in fig. 10 (B) can also be obtained.

In addition, the housing portions 32a,32b, and 32c of the present embodiment are provided with printed circuit boards 37a,37b, and 37c in a plan view. The receiving portions 32a,32b, and 32c are chamfered at the corner of the inner wall surface 32h on the other side. Therefore, the package member 40b of the output side region 41a can be made thicker than in the case of a rectangular shape without chamfering. For example, the length of the inner wall surface 32h on the other side may be 80% or more and 99% or less of the length in the case of a rectangular shape that is not chamfered. Therefore, in the present embodiment, the length of the inner wall surface 32h on the other side can be made thicker in the output side region 41a than in the case of the rectangular shape without chamfering.

In the vicinity of the output side region 41a of the thus obtained package member 40b, as shown in fig. 11, the package member 40b packages the upper inner wall surface 32h1 included in the inner wall surface 32h of the case 30, the front surface of the V-connecting portion 35b1, and the front surface of the printed circuit board 37b of the stepped portion 32h2 included in the inner wall surface 32h of the case 30. The sealing member 40b also penetrates the side of the ceramic circuit board 21. The sealing member 40b penetrates without any gap between the lower portions of the V-connecting portion 35b1 and the printed circuit board 37b and the lower inner wall surface 32h3 included in the inner wall surface 32h of the case 30.

When the semiconductor unit 20 housed in the housing portion 32b of the case 30 is packaged with the package member, the package member is less likely to penetrate between the back surface of the printed circuit board 37b and the lower inner wall surface 32h3, and a gap is likely to be generated. In this way, if the sealing member is discharged to the inner wall surface 32h side of the housing portion 32b, the V-shaped connecting portion 35b1 disposed at the center portion of the inner wall surface 32h is first sealed. On the other hand, the printed circuit board 37b is disposed on both sides of the V-link 35b1 and below the V-link 35b 1. Therefore, the space between the back surface of the printed circuit board 37b and the lower inner wall surface 32h3 is the position where the sealing resin reaches the end, and a gap is likely to be generated. As described above, in the sealing process, the sealing member is ejected more in the vicinity of the start position ("S") than in other positions. Therefore, the penetration is difficult, and the penetration can be sufficiently made between the back surface of the printed circuit board 37b and the lower inner wall surface 32h 3.

In the intermediate region 41b of the package member 40b, the lead frame 26a, the semiconductor chip 25a, and the like on the front surface of the ceramic circuit board 21 are packaged. In the intermediate region 41b of the sealing member 40b, the distance H1 from the front surface of the wiring portion 26a3 of the lead frame 26a to the sealing surface of the sealing member 40b is 0.5mm or more and 4.0mm or less. Further, the package surface of the output side region 41a of the package member 40b is a surface further upward by a distance H2 from the distance H1. The distance H2 is 0.5mm to 4.0 mm. The semiconductor unit 20 accommodated in the accommodation portion 32b is thus reliably packaged from the front side. Note that the input side region 41c of the package member 40b, which is not shown, is also packaged in the same manner.

The semiconductor device 10 includes semiconductor chips 25a and 25b and a ceramic circuit board 21, the semiconductor chips 25a and 25b having main electrodes on the front surface, the ceramic circuit board 21 having an insulating plate and circuit patterns 23a and 23c, the circuit patterns 23a and 23c being formed on the front surface of the insulating plate 22 and provided on the back surface side of the semiconductor chips 25a and 25 b. The semiconductor device 10 includes a case 30, the case 30 includes a frame portion 31 and printed circuit boards 37a,37b,37c, the frame portion 31 includes housing portions 32a,32b,32c, the housing portions 32a,32b,32c have a rectangular opening in a plan view, are surrounded on all sides by inner wall surfaces, and house the ceramic circuit board 21, and the printed circuit boards 37a,37b,37c are provided in a flat plate shape, and protrude from the inner wall surfaces 32h toward the housing portions 32a,32b,32 c. The semiconductor device 10 further includes package members 40a,40b, and 40c which fill the housing portions 32a,32b, and 32c and package the semiconductor chips 25a and 25b and the printed circuit boards 37a,37b, and 37 c. In this case, the height of the front surface of the package member 40a,40b,40c from the rear surface of the package member 40a,40b,40c is higher on the printed circuit board 37a,37b,37c side than on the semiconductor chip 25a,25b side. Specifically, the height of the package members 40a,40b,40c from the back surface to the front surface as the thickness direction of the semiconductor chips 25a,25b is higher on the printed circuit boards 37a,37b,37c side than on the semiconductor chips 25a,25b side. Thus, the sealing members 40a,40b,40c can penetrate into the receiving portions 32a,32b,32c, and appropriately seal the semiconductor chips 25a,25b and the printed circuit boards 37a,37b,37 c. Therefore, generation of voids and the like in the package members 40a,40b,40c is prevented. In order to realize such a package, the thickness of the package members 40a,40b,40c is increased only on the printed circuit boards 37a,37b,37c side, instead of increasing the thickness of the entire package members 40a,40b,40 c. Therefore, an increase in thermal stress generated in the entire semiconductor device 10 due to thermal deformation of the semiconductor device 10 can be suppressed to some extent. This can suppress a decrease in reliability of the semiconductor device 10.

[ second embodiment ]

In the second embodiment, a packaging process different from the first embodiment is performed. This sealing process will be described with reference to fig. 12 and 13. The semiconductor device 10 (not shown) of the second embodiment has the same configuration as the semiconductor device 10 of the first embodiment. However, the shapes of the encapsulating members 40a,40b,40c are different. Fig. 12 is a flowchart showing a packaging process included in the method for manufacturing a semiconductor device according to the second embodiment. Fig. 13 is a diagram for explaining a packaging process included in the method for manufacturing a semiconductor device according to the second embodiment. Fig. 13 corresponds to fig. 10 (B). That is, the package member 40b of the package storage portion 32b is viewed from the inner wall surface 32f or the inner wall surface 32g (storage long side) parallel to the moving direction of the dispenser 50.

Step S13h1 is performed in the flowchart shown in fig. 12 instead of step S13h of the flowchart of fig. 9. That is, in step S13g, if the dispenser 50 moving at a predetermined speed from "S" to "T" while ejecting the package parts reaches "T", the moving direction is switched to a direction toward the "S" side and stays for a predetermined time (step S13h1 of fig. 12). In the second embodiment, the dispenser 50 stays for a predetermined time after the "S" switching direction, as well as after the "T" switching direction. For example, the start position ("S") or the return position ("T") may be either above the printed circuit board 37b (and the V-connection portion 35b1) or above the N-connection portion 34b1 (and the P-connection portion 33b1) extending from the side surface opposite to the printed circuit board 37b when viewed from the inner wall surface 32g (the storage long side) parallel to the moving direction of the dispenser 50 corresponding to fig. 8. The dwell time after the direction change between "S" and "T" may be longer at the folded position corresponding to the upper side of the printed circuit board 37b (and the V-connection portion 35b1) than at the folded position on the opposite side. The other steps are performed in the same manner as in the first embodiment. After the sealing process, as shown in fig. 13, the height of the sealing member 40b of the sealing housing portion 32b from the bottom surface of the sealing member 40b in the output side region 41a is higher than the height of the sealing member 40b in the intermediate region 41 b. Specifically, the height of the output side region 41a from the back surface to the front surface as the thickness direction of the semiconductor chips 25a,25b is higher than the height of the intermediate region 41 b.

In addition, the height from the bottom surface of the package member 40b of the input side region 41c also becomes higher than the height from the bottom surface of the package member 40b of the intermediate region 41 b.

As described above, when the package member 40b is filled in the housing portion 32b, the dispenser 50 is reciprocated along the inner wall surfaces 32f and 32g above the intermediate section 42b (see fig. 10 a), and the package member is discharged to the intermediate section 42 b. In this case, the dispenser 50 stays at the position for a predetermined time when the direction is switched in the output side region 41a including "S". Also, in the second embodiment, the dispenser 50 stays at the position for a predetermined time after the direction is switched in the input side region 41c including "T". By repeating this, the amount of the package components of the output side region 41a becomes larger than that of the middle region 41b, and the amount of the package components of the input side region 41c becomes larger than that of the middle region 41 b. In the solidified package member 40b, the thickness (volume) decreases from the output-side region 41a to the intermediate region 41b, and monotonically inclines such that the thickness decreases from the output-side region 41a to the intermediate region 41 b. On the other hand, the thickness (volume) monotonically inclines so as to become lower from the input-side region 41c to the intermediate region 41b as it decreases from the input-side region 41c to the intermediate region 41 b. Therefore, the encapsulating member 40b has a concave shape as a whole.

As described above, by changing the discharge amount of the dispenser 50 per unit time, the thickness of the sealing member 40b can be changed according to the position thereof. For example, when the dispenser 50 is reciprocated along the inner wall surfaces 32f,32g above the middle area 42b ((a) of fig. 10), the discharge amount per unit time is increased in the output side area 41a, decreased in the middle area 41b, and increased in the input side area 41 c. Thereby, the package member 40b shown in fig. 13 is obtained. Alternatively, as described above, the thickness of the packing member 40b may be varied according to the position thereof by changing the moving speed of the dispenser 50. For example, when the dispenser 50 is reciprocated along the inner wall surfaces 32f,32g above the intermediate area 42b ((a) of fig. 10), the moving speed is reduced in the output side area 41a, and the moving speed is reduced again as the moving speed is increased in the intermediate area 41b and the moving speed is reduced again as the moving speed is increased in the input side area 41 c. In this case, the package member 40b shown in fig. 11 can be obtained.

Further, corners of the inner wall surface 32i on the side where the P-junctions 33a1,33b1,33c1 and the N-junctions 34a1,34b1,34c1 are arranged may be chamfered. By doing so, the thickness of the package member 40b in the input side region 41c can be increased as compared with the case where the package member is not chamfered. At this time, in the solidified package member 40b, it is monotonously inclined so as to become higher from the intermediate region 41b to the input side region 41c side. In addition, the chamfer of the inner wall surface 32i on one side may be larger than the chamfer of the inner wall surface 32h on the other side. That is, the length of the other inner wall surface 32i is shorter than the length of the one inner wall surface 32 h. For example, the length of the inner wall surface 32h on the other side may be 80% or more and 99% or less of the length in the case of an un-chamfered rectangle, and the length of the inner wall surface 32i on the one side may be 40% or more and less than 80% of the length in the case of an un-chamfered rectangle. By doing so, as shown in fig. 13, the height from the bottom surface of the package part 40b of the output-side region 41a and the input-side region 41c is higher than the height from the bottom surface of the package part 40b of the intermediate region 41 b. Specifically, the height of the output-side region 41a and the input-side region 41c from the back surface to the front surface in the thickness direction of the semiconductor chips 25a and 25b is higher than the height of the intermediate region 41 b.

In the first embodiment, corners of the inner wall surface 32i on the side where the P-connection portions 33a1,33b1,33c1 and the N-connection portions 34a1,34b1,34c1 are arranged may be chamfered. In the first embodiment, as shown in fig. 10, the thickness of the package member 40b in the output side region 41a is further increased. In the first embodiment in this case, the amount of the encapsulating member 40b corresponding to the input side region 41c can be reduced as compared with the case where the corner portion is not chamfered. As described above, in order to reduce the amount of the enclosing component, it is possible to make the moving speed of the dispenser 50 at the input side region 41c faster, or to reduce the ejection amount from the ejection port 51 of the dispenser 50 at the input side region 41 c.

In the semiconductor device 10, the height of the front surface of the package member 40a,40b,40c from the back surface of the package member 40a,40b,40c is higher on the printed circuit board 37a,37b,37c side and on the side facing the printed circuit board 37a,37b,37c via the housing portion 32a,32b,32c than on the semiconductor chip 25a,25b side. Specifically, the height of the package members 40a,40b,40c from the back surface to the front surface in the thickness direction of the semiconductor chips 25a,25b is higher on the printed circuit boards 37a,37b,37c side and on the side facing the printed circuit boards 37a,37b,37c via the receiving portions 32a,32b,32c than on the semiconductor chips 25a,25b side. Thus, the sealing members 40a,40b,40c can penetrate into the receiving portions 32a,32b,32c, and appropriately seal the semiconductor chips 25a,25b, the green sheets 37a,37b,37c, and the regions facing the green sheets 37a,37b,37 c. Therefore, generation of voids and the like in the package members 40a,40b,40c is prevented. In order to realize such a package, the thickness of the package members 40a,40b, and 40c is increased only on the printed circuit boards 37a,37b, and 37c and the regions facing the printed circuit boards 37a,37b, and 37c, and the thickness of the entire package members 40a,40b, and 40c is not increased. Therefore, an increase in thermal stress generated in the entire semiconductor device 10 due to thermal deformation of the semiconductor device 10 can be suppressed to some extent. This can suppress a decrease in reliability of the semiconductor device 10.

[ third embodiment ]

In the third embodiment, a case where the area of the ceramic circuit board 21 stored in the storage portions 32a,32b, and 32c of the case 30 in a plan view is smaller than the area of the ceramic circuit board 21 of the first embodiment in a plan view will be described with reference to fig. 14 and 15. Fig. 14 is a plan view of the semiconductor device according to the third embodiment, and fig. 15 is a plan view of a main portion of the semiconductor device according to the third embodiment. Note that fig. 14 and 15 omit illustration of the package member. Fig. 15 shows an enlarged view of the vicinity of the housing portion 32b surrounded by the broken line in fig. 14. The case 30 of fig. 14 and 15 is the same as the case 30 (fig. 5 and 6) of the first embodiment. The size of the semiconductor unit 20a of fig. 14 and 15 is different from that of the semiconductor unit formed in the same configuration as the semiconductor unit 20 (fig. 4) of the first embodiment. In fig. 14 and 15, the components used in the description are denoted by reference numerals. The frame long side 31a of the case 30 shown in fig. 14 differs from the frame long side 31a of the case 30 of the first embodiment only in that the frame long side 31a of fig. 14 is flat. Other points of the frame long side 31a of the case 30 shown in fig. 14 are the same as the frame long side 31a of the case 30 of the first embodiment.

In the semiconductor device 10 of the third embodiment, as shown in fig. 14, the semiconductor units 20a are housed in the housing portions 32a,32b,32c of the case 30, respectively. At this time, the semiconductor unit 20a is housed in the housing portions 32a,32b,32c with a space therebetween, as compared with the case of the first embodiment.

Although the semiconductor unit 20a is formed to have the same configuration as the semiconductor unit 20, the ceramic circuit substrate 21 includes the insulating plate 22 having a smaller size than the insulating plate 22 included in the semiconductor unit 20. The dimensions of the insulating plate 22 will be described later. As shown in fig. 15, the insulating plate 22 is surrounded by a pair of opposing long sides 22a1,22a2, short sides 22a3,22a4, and corner sides 22a5,22a 6. The short side 22a3 is orthogonal to the pair of long sides 22a1,22a 2. The short edge 22a4 is opposite the short edge 22a 3. The length (± X direction) of short side 22a4 is less than the length (± X direction) of short side 22a 3. The corner edges 22a5,22a6 connect a pair of long edges 22a1,22a2 and short edges 22a 4.

In addition, a plurality of circuit patterns 23a,23b,23c,23d,23e,23f,23g are formed on the front surface of the insulating plate 22 as described above. The circuit patterns 23a,23c are formed on the front surface of the insulating plate 22 on the sides of the long sides 22a1,22a2 along the long sides 22a1,22a2 in the direction (± Y direction) from the short side 22a3 to the short side 22a 4. The circuit patterns 23a and 23c have recesses formed near the middle thereof and opened to the long sides 22a1 and 22a 2. The semiconductor chips 25a,25b are bonded to the circuit patterns 23a,23c via the concave portions, respectively.

The circuit patterns 23e,23d are formed along the long side 22a1 on the long side 22a1 side in the concave portion of the circuit pattern 23 a. The circuit patterns 23f,23g are formed along the long side 22a2 on the long side 22a2 side in the concave portion of the circuit pattern 23 b. The circuit patterns 23b and 23h are also formed on the front surface of the insulating plate 22 along the long sides 22a1 and 22a2 in a direction (± Y direction) from the short side 22a3 toward the short side 22a 4.

Such a semiconductor unit 20a is housed so as to be separated from the inner wall surfaces of the housing portions 32a,32b, and 32c by a predetermined distance. Hereinafter, a case where the semiconductor unit 20a is accommodated in the accommodation portion 32b will be described as an example with reference to fig. 15. The housing portions 32a,32c are also the same as the housing portion 32 b.

The housing portion 32b is a region surrounded by a pair of opposing inner wall surfaces 32b1,32b2 (long-side inner wall surfaces), an inner wall surface 32h (one inner wall surface), an inner wall surface 32i (the other inner wall surface), and inner wall surfaces 32b3,32b4 (corner-side inner wall surfaces). The storage portion 32b is formed in a shape substantially similar to the shape of the insulating plate 22 of the ceramic circuit board 21 in plan view.

The inner wall surfaces 32b1,32b2 correspond to the inner wall surfaces 32f,32g of the first embodiment. Unlike the inner wall surfaces 32f and 32g, the inner wall surfaces 32b1 and 32b2 are flat and have no irregularities 32b1 and 32b 2. The inner wall surfaces 32b1,32b2 are parallel to the long sides 22a1,22a2 of the insulating plate 22 included in the ceramic circuit board 21. The inner wall surfaces 32b1,32b2 are separated from the long sides 22a1,22a2 of the insulating plate 22 by a distance W2 (in the ± X direction), respectively.

As described above, the inner wall surface 32h is orthogonal to the pair of inner wall surfaces 32b1,32b2, and the printed circuit board 37b is provided so as to be perpendicular to the housing portion 32 b. The inner wall surface 32i faces the inner wall surface 32 h. The length (± X direction) of inner wall surface 32h is greater than the length (± X direction) of inner wall surface 32 i. The inner wall surface 32h is parallel to the short side 22a3 of the insulating plate 22 included in the ceramic circuit board 21. The inner wall surface 32h is separated from the short side 22a3 of the insulating plate 22 by a distance W1 (± Y direction). In the housing portion 32b, the length from the inner wall surface 32h to the inner wall surface 32i is (± Y direction) L.

The inner wall surfaces 32b3,32b4 are connected to the pair of inner wall surfaces 32b1,32b2, extend toward the inner wall surface 32i, and are located at the corners of the housing portion 32 b. In addition, the inner wall surfaces 32b3,32b4 are parallel to the corner edges 22a5,22a6 of the insulating plate 22 included in the ceramic circuit substrate 21 and are separated from the corner edges 22a5,22a 6. The inner wall surfaces 32b3,32b4 and the inner wall surface 32i form a step in a plan view.

As in the first and second embodiments, the housing portions 32a,32b, and 32c of the case 30 housing the semiconductor unit 20a are sealed with a sealing member, thereby obtaining a semiconductor device.

A center line CL passing through the center of the housing portion 32b is set, and the center line CL is parallel to the inner wall surfaces 32h and 32i with respect to the housing portion 32b housing the semiconductor unit 20 a. In addition, in the ceramic circuit board 21 housed in the housing portion 32b, a first stress concentration region S1 is set as a region surrounded by lines of symmetry L1a, L1b that are substantially equidistant from the center line CL toward the inner wall surfaces 32h,32i (± Y direction).

In the ceramic circuit board 21 housed in the housing portion 32b, a second stress concentration region S2 is set as a region surrounded by lines of symmetry L2a, L2b that extend from the center line CL toward the wall surfaces 32h,32i and are located outside (on the ± Y direction side) the first stress concentration region S1 at substantially equal distances from each other. The center line CL, the first stress concentration region S1, and the second stress concentration region S2 are not limited to be set in the receiving portion 32b, and may be set in the entire housing 30 (semiconductor device).

In such a semiconductor device 10, if a temperature cycle test is performed, warpage occurs with temperature change due to a difference in the coefficient of thermal linear expansion of each constituent member. As shown in fig. 14 in particular, the housing 30 is warped so that the center line CL is convex upward. At this time, stress is generated between the symmetry lines L2a, L2b (second stress concentration region S2). And, a larger stress is generated between the symmetry lines L1a, L1b (first stress concentration region S1). At this time, the maximum stress is generated in the vicinity of the respective pressure regions S of the frame short sides 31c,31d and the partition portions 32d,32e of the casing 30 in the second stress concentration region S2. For example, in the first embodiment, in the case where a portion included in the ceramic circuit substrate 21 exists within such a pressure region S, the solder under the portion of the ceramic circuit substrate 21 may be damaged. In addition, if the case 30 is warped, the solder under the vicinity of the corner of the ceramic circuit board 21 is also easily damaged.

If the solder is damaged and deteriorated, the thermal conductivity of the portion is lowered, resulting in a reduction in the heat dissipation property of the semiconductor device 10. Note that, in the accommodating portion 32b, the symmetry lines L1a, L1b of the first stress concentration region S1 may be parallel to the inner wall surfaces 32h,32i and the center line CL. In addition, the symmetry lines L1a, L1b may be separated from the center line CL by the first object distance in the direction (± Y direction) of the respective inner wall surfaces 32h,32 i. For example, the first target distance is 2% or more and 6% or less of the length L of the housing portion 32 b. Preferably 4%. In addition, the symmetry lines L2a, L2b of the second stress concentration region S2 may be parallel to the inner wall surfaces 32h,32i and the center line CL. In addition, the symmetry lines L2a, L2b may be spaced apart from the center line CL by the second object distance in the direction (± Y direction) of the respective inner wall surfaces 32h,32 i. For example, the second target distance is 10% or more and 15% or less of the length L of the housing portion 32 b. Preferably 12.5%. The same applies to the storage portions 32a,32 c.

Therefore, in the third embodiment, as shown in fig. 15, the ceramic circuit board 21 of the semiconductor unit 20a is spaced apart from the inner wall surface 32h and the inner wall surfaces 32b1,32b2 of the housing portion 32b by distances W1, W2. Thus, by avoiding the pressure region S where stress is likely to occur in the ceramic circuit board 21, stress to the solder under the ceramic circuit board 21 can be reduced. Further, by spacing the ceramic circuit board 21 by the distance W1 from the inner wall surface 32h of the housing portion 32b, the back surface side of the printed circuit board 37b can be reliably sealed with the sealing member 40 b. Similarly, the ceramic circuit board 21 is separated from the inner wall surfaces 32b3,32b4 and the inner wall surface 32i of the housing portion 32b by a distance W2 from the inner wall surfaces 32b1,32b2 of the housing portion 32 b. This can reduce stress on the solder under the ceramic circuit board 21. Moreover, the encapsulating resin is easily caused to enter each void. Therefore, the ceramic circuit board 21 can be more reliably housed in the housing portion 32 b.

In order to alleviate stress on the ceramic circuit board 21 in the housing portion 32b, the distance W1 from the ceramic circuit board 21 housed in the housing portion 32b is preferably 4% to 16% of the length L of the housing portion 32 b. The distance W2 is 4% to 16% of the length L of the housing portion 32 b. In order to relax the stress on the ceramic circuit board 21 in the housing 32b, at least one of the distances W1 and W2 may be provided, and in order to reliably relax the stress, both the distances W1 and W2 are preferably provided.

In addition, the corner sides 22a5,22a6 and the short side 22a4 of the ceramic circuit substrate 21 of the semiconductor unit 20a are parallel to the inner wall surfaces 32b3,32b4 and the inner wall surface 32i of the accommodation portion 32b and are spaced apart by a predetermined distance. In addition, the ceramic circuit board 21 has no corner. Therefore, even if stress is applied to the ceramic circuit board 21, stress applied to the solder under the corner portion where stress is likely to be applied can be relaxed.

As described above, the shape of the housing portion 32b is substantially similar to the shape of the insulating plate 22 of the ceramic circuit board 21 in a plan view. Therefore, the stress on the ceramic circuit board 21 can be relaxed.

In addition, the inner wall surfaces 32b1,32b2 of the storage section 32b are not formed with irregularities but are flat, unlike the inner wall surfaces 32f,32g of the storage section 32b of the first embodiment. If stress is generated when the convex portions are formed as in the inner wall surfaces 32f,32g of the housing portion 32b of the first embodiment, the stress is concentrated in the convex portions, and the inner wall surfaces 32f,32g may be damaged from the convex portions. In the third embodiment, since the inner wall surfaces 32b1,32b2 of the housing portion 32b are flat, it is possible to suppress stress concentration and prevent damage to the inner wall surfaces 32b1,32b 2.

In addition, the semiconductor chips 25a,25b are formed with the circuit patterns 23a,23c from the first stress concentration region S1 toward the inner wall surfaces 32h,32i side (± Y direction side), respectively, in the region other than the first stress concentration region S1. Therefore, stress to the semiconductor chips 25a,25b can be avoided, thereby preventing damage.

The circuit patterns 23a and 23c are formed on the long sides 22a1 and 22a2, respectively, from the short side 22a3 toward the short side 22a4(± Y direction) and along the long sides 22a1 and 22a2 with respect to the front surface of the insulating plate 22. Even if the case 30 is warped about the center line CL, the circuit patterns 23a and 23c follow the warp, and the stress can be relaxed to prevent damage.

In addition, the semiconductor unit 20a and the printed circuit board 37b are electrically and mechanically connected by a plurality of bonding wires. The outermost (near inner wall surfaces 32b1,32b2) bonding wires 38a,38b of the plurality of bonding wires are connected to the circuit patterns 23e,23f of the ceramic circuit substrate 21. At this time, the outermost bonding wires 38a,38b are routed toward the inside of the ceramic circuit substrate 21. That is, the outermost bonding wires 38a and 38b connect the printed circuit board 37b and the circuit patterns 23e and 23f across the long sides 22a1 and 22a2 of the insulating plate 22 of the ceramic circuit board 21. Also, at this time, connection portions (the other end portions) of the outermost bonding wires 38a,38b with the circuit patterns 23e,23f may be within the second stress concentration region S2. Accordingly, at least a portion of the circuit patterns 23e,23f may be contained within the second stress concentration region S2. Assuming that the connection portion of the bonding wire 38a,38b with the circuit pattern 23e,23f is at the first stress concentration region S1, the connection portion may be subject to stress and be peeled off from the circuit pattern 23e,23 f. Such peeling is suppressed by connecting the bonding wires 38a,38b to the circuit patterns 23e,23f avoiding the first stress concentration region S1.