阅读说明：本技术 内埋组件的基板结构及其制造方法 (Substrate structure of embedded component and manufacturing method thereof ) 是由 林建辰 于 2020-07-20 设计创作，主要内容包括：一种内埋组件的基板结构及其制造方法,于载板结构的顶部上形成凹槽,并于凹槽内设置预设有多个导线件的芯片结构,而后于载板结构的顶部及底部上分设介电层,且使载板结构内的多个线路的相对二端部分别暴露分设于载板结构的顶部及底部的介电层,接着分别于载板结构的顶部及底部的介电层上分设线路增层结构,并且分别与暴露于介电层的载板结构的线路的端部电连接。由于不需通过雷射钻孔于载板结构的顶部的介电层上制作对应的雷射穿孔,故可改善因雷射钻孔的精度及热扩孔的限制,使相邻导线件连接而短路或导线件空接的问题,借此达到提升基板结构的使用可靠性以及稳定性的目的。(A substrate structure of embedded module is prepared as forming recess on top of carrier plate structure, setting chip structure with multiple conducting elements in recess, setting dielectric layers on top and bottom of carrier plate structure separately exposing two opposite ends of multiple lines in carrier plate structure to dielectric layers on top and bottom of carrier plate structure separately, setting line layer-adding structure on dielectric layers on top and bottom of carrier plate structure separately and connecting line end exposed to dielectric layer separately. Because the corresponding laser perforation is not needed to be made on the dielectric layer on the top of the carrier plate structure by laser drilling, the problem of short circuit or empty connection of the adjacent conducting wire parts due to the connection of the adjacent conducting wire parts caused by the precision of the laser drilling and the limitation of thermal reaming can be solved, thereby achieving the purpose of improving the use reliability and the stability of the substrate structure.)

1. A substrate structure of an embedded component, comprising:

the carrier structure is provided with a top and a bottom which are opposite to each other, and a plurality of first circuits and a plurality of second circuits, wherein the top of the carrier structure is concave inwards to form a containing groove, the first circuits and the second circuits are arranged in the carrier structure, the second circuits are respectively provided with a first end part and a second end part which are opposite to each other, the first end parts of the second circuits are exposed out of the top of the carrier structure, and the second end parts of the second circuits are exposed out of the bottom of the carrier structure;

a first dielectric layer disposed on the bottom of the carrier structure and exposing a second end of the second line of the carrier structure to the first dielectric layer;

a chip structure with a plurality of lead pieces is preset and is arranged in the accommodating groove;

a second dielectric layer disposed on the top of the chip structure and the carrier structure, and exposing the wire guide of the chip structure and the first end of the second circuit out of the second dielectric layer;

the first circuit layer-adding structure is arranged on the second dielectric layer, the conducting wire piece of the chip structure and the second end part of the second circuit and is respectively and electrically connected with the corresponding conducting wire piece on the chip structure and the first end part of the corresponding second circuit on the carrier plate structure;

and the second circuit layer adding structure is arranged at the bottom of the carrier plate structure and is respectively and electrically connected with the second end part of the corresponding second circuit on the carrier plate structure.

2. The substrate structure of an embedded component according to claim 1, wherein the chip structure comprises:

the bridge chip is provided with a top part, a bottom part, a plurality of circuits and a plurality of joints, wherein the top part and the bottom part are opposite to each other;

the wire guide structure is provided with a fixing layer and the wire guide, the fixing layer is provided with a top and a bottom which are opposite, the wire guide is respectively provided with a first end part and a second end part which are opposite and are respectively exposed out of the top and the bottom of the fixing layer, the bottom of the wire guide structure is arranged on the top of the bridging chip, and the second end part of the wire guide is respectively and electrically connected with a corresponding contact on the bridging chip.

3. The substrate structure of an embedded device according to claim 1, further comprising:

and the adhesion layer is arranged in the containing groove and is positioned between the chip structure and the carrier plate structure.

4. The substrate structure of an embedded device according to claim 1, further comprising:

and the electric connection layer is arranged on the first circuit layer-adding structure and is respectively and electrically connected with the corresponding first end part on the second circuit and the corresponding wire guide part on the chip structure through the first circuit layer-adding structure.

5. The substrate structure of claim 4, further comprising at least one chip disposed on a top of the carrier structure of the substrate structure, wherein the chip has a plurality of contacts, and the contacts of the chip are electrically connected to the corresponding second traces and the corresponding conductive traces on the chip structure via the electrical connection layer.

6. A method for manufacturing a substrate structure of an embedded component is characterized by comprising the following steps:

forming a containing groove in a concave manner on the top of the carrier plate structure, wherein the carrier plate structure is internally provided with a plurality of first circuits and a plurality of second circuits, so that first ends of the second circuits are exposed out of the top of the carrier plate structure, and second ends of the second circuits are exposed out of the bottom of the carrier plate structure;

arranging a first dielectric layer at the bottom of the carrier plate structure;

a chip structure with a plurality of lead pieces is arranged in the containing groove of the carrier plate structure in advance;

arranging a second dielectric layer on the top of the carrier plate structure and the chip structure;

exposing the wire members of the chip structure and the first end portions of the second lines of the carrier plate structure to the second dielectric layer, and arranging first line layer-adding structures on the second dielectric layer, the wire members of the chip structure and the first end portions of the second lines of the carrier plate structure, and electrically connecting the first line layer-adding structures with the corresponding wire members of the chip structure and the first end portions of the corresponding second lines of the carrier plate structure;

and arranging a second circuit layer-adding structure on the first dielectric layer and the second end part of the second circuit of the carrier plate structure, and electrically connecting the second end part of the second circuit corresponding to the carrier plate structure.

7. The method of claim 6, wherein the chip structure comprises a bridge chip having opposing top and bottom portions and a plurality of traces and contacts disposed within the bridge chip, and a wire guide structure having a mounting layer and the wire guide, the step of forming the chip structure comprising:

arranging the fixed layer on the carrier, and forming a plurality of through holes penetrating through the top and the bottom of the fixed layer;

arranging the wire guiding members in the through holes of the fixing layer, wherein the first end parts of the wire guiding members are respectively contacted with the carrying member, and the second end parts of the wire guiding members are respectively exposed out of the bottom of the fixing layer;

arranging the top of the bridging chip on the bottom of the fixed layer, and electrically connecting the second end of the wire guide with corresponding contacts on the bridging chip respectively;

removing the carrier;

removing the top of the fixing layer to expose the first end of the wire guide.

8. The method as claimed in claim 6, wherein before the chip structure is disposed in the receiving cavity of the carrier structure, an adhesive layer is disposed in the receiving cavity and then the chip structure is disposed on the adhesive layer in the receiving cavity.

9. The method as claimed in claim 6, further comprising providing an electrical connection layer on the first build-up structure.

10. The method of claim 9, further comprising disposing at least one die on top of the carrier structure of the substrate structure, the die having a plurality of contacts, the disposing the die comprising:

and arranging the chip on the top of the carrier plate structure, and enabling the contact points of the chip to be respectively and electrically connected with the first end part of the corresponding second circuit on the carrier plate structure and the corresponding conducting wire piece on the chip structure through the electric connection layer.

Technical Field

The present invention relates to a substrate structure and a method for fabricating the same, and more particularly, to a substrate structure with embedded components and a method for fabricating the same.

Background

Due to the rapid development and change of social modalities, not only the lifestyle of the public is changed, but also the application in different fields such as Internet of Things (IoT), 5G mobile communication (5th generation wireless systems,5G), biotechnology, Artificial intelligence chip (AI chip) and other electronic industries is rapidly growing. These rapidly growing electronic industries create many electronic products with more advanced functions and better quality of use by the performance enhancement brought by the inter-operation of many components installed inside, so as to improve the quality of life, convenience or connect related service networks in series.

The components in an electronic product are usually assembled from one or more chips, in which one or more electronic components or one or more processors are disposed, and then electrically connected to each other and assembled to complete the electronic product. In the manufacturing of the present component, a chip is generally disposed on a top surface of a carrier structure, a protective layer is disposed on the carrier structure and the chip to cover the chip and the top surface of the carrier structure, a plurality of laser through holes corresponding to a plurality of contacts of the chip are drilled on the protective layer by a laser drilling device, and a plurality of pins connecting the chip and exposing the protective layer are formed in the laser through holes and electrically connected to pins of other chips or circuits on the component through the pins to complete the manufacturing of the component.

In order to improve the performance of a chip, more electronic components or processors are required to be disposed in a limited size to improve the performance of the chip. However, the exposed contacts are very close in arrangement due to the limited size of the chip, and furthermore, are limited by the accuracy limitations of the laser drilling equipment and the effects of thermal reaming, so that the apertures and positions of the laser via holes are unstable and susceptible to interaction with neighboring laser via holes. Therefore, not only the problem of short circuit caused by the interconnection of adjacent pins may occur in the process of setting the pins, but also the problem of empty connection caused by the incomplete connection of the pins with the contacts may occur, which results in the reduction of the reliability of use.

For example, as disclosed in taiwan patent publication No. TWI545997 (hereinafter referred to as document 1), an interposer substrate and a method for manufacturing the interposer substrate are disclosed, in which an insulating layer is formed on a carrier board having a circuit layer, then a circuit build-up structure electrically connected to the insulating layer and the circuit layer is formed, and then an external post is formed on the circuit build-up structure and electrically connected to the circuit build-up structure. However, document 1 does not disclose how to make corresponding contacts for connecting to other chips on the chip mounted on the carrier structure.

Also, for example, a package structure disclosed in taiwan patent publication No. TWI418265 (hereinafter referred to as document 2) includes a carrier having a through opening and a metal layer covering one side of the opening, a semiconductor chip received in the opening and disposed on the metal layer, a stud bump disposed on the semiconductor chip, a dielectric layer covering the carrier and the semiconductor chip and covering the stud bump, a circuit layer disposed on the dielectric layer and electrically connected to the stud bump, and a protective layer disposed on the dielectric layer and the circuit layer and serving as a signal transmission component through the stud bump. However, document 2 does not disclose how to make corresponding contacts for connecting to other chips on the chip mounted on the carrier structure.

Disclosure of Invention

In view of the above-mentioned problems of the prior art, a primary objective of the present invention is to provide a substrate structure of an embedded device and a method for manufacturing the same, in which a chip with a pre-fabricated conductive element is disposed on a carrier structure, so that after a dielectric layer is covered, the conductive element can be connected to other chips by only exposing the dielectric layer. Because the laser perforation of the wire guide is arranged without additional reproduction of laser drilling on the dielectric layer, the problems of short circuit or idle connection of the wire guide caused by the mutual connection of adjacent wire guides due to the precision limitation of the laser drilling and the influence of thermal reaming can be solved, thereby achieving the purpose of improving the use reliability and stability of the substrate structure.

The main technical means adopted to achieve the above object is to make the substrate structure of the embedded component include the following structures.

The carrier plate structure is provided with a top and a bottom which are opposite to each other, a plurality of first circuits and a plurality of second circuits, the top of the carrier plate structure is concave inwards to form a containing groove, the first circuits and the second circuits are arranged in the carrier plate structure, the second circuits are respectively provided with a first end portion and a second end portion which are opposite to each other, the first end portions of the second circuits are exposed out of the top of the carrier plate structure, and the second end portions of the second circuits are exposed out of the bottom of the carrier plate structure.

The first dielectric layer is disposed on the bottom of the carrier structure, and a second end of the second line of the carrier structure is exposed out of the first dielectric layer.

And the chip structure with a plurality of wire guiding members is arranged in the accommodating groove.

The second dielectric layer is arranged on the tops of the chip structure and the carrier plate structure, and leads of the chip structure and the first end part of the second circuit are exposed out of the second dielectric layer.

And the first circuit layer-adding structure is arranged on the second dielectric layer, the conducting wire piece of the chip structure and the second end part of the second circuit and is respectively and electrically connected with the corresponding conducting wire piece on the chip structure and the first end part of the corresponding second circuit on the carrier plate structure.

And the second circuit layer adding structure is arranged at the bottom of the carrier plate structure and is respectively and electrically connected with the second end part of the corresponding second circuit on the carrier plate structure.

Optionally, the chip structure includes a bridge chip and a wire guide structure. The bridging chip is provided with a top and a bottom which are opposite to each other, a plurality of lines and a plurality of joints, the lines are arranged in the bridging chip, and the joints are arranged on the top of the bridging chip at intervals. The wire guide structure is provided with a fixed layer and the wire guide, the fixed layer is provided with a top and a bottom which are opposite, the wire guide is respectively provided with a first end part and a second end part which are opposite and are respectively exposed out of the top and the bottom of the fixed layer, the bottom of the wire guide structure is arranged on the top of the bridging chip, and the second end part of the wire guide is respectively and electrically connected with a corresponding contact on the bridging chip.

Optionally, the package structure further includes an adhesive layer disposed in the accommodating groove and located between the chip structure and the carrier structure.

Optionally, the chip structure further includes an electrical connection layer disposed on the first circuit build-up structure and electrically connected to the corresponding first end portion of the second circuit and the corresponding wire guide of the chip structure through the first circuit build-up structure.

Optionally, at least one chip is further disposed on the top of the carrier structure of the substrate structure, the chip has a plurality of contacts and is disposed on the top of the carrier structure, and the contacts of the chip are electrically connected to the corresponding second lines and the corresponding wire guides of the chip structure via the electrical connection layer, respectively.

According to the structure, the chip structure which is preset and manufactured by the semiconductor manufacturing process and is provided with the wire guide in advance is fixedly arranged in the accommodating groove of the carrier plate structure, the second dielectric layer is arranged on the top of the carrier plate structure to protect the chip structure, and the wire guide of the chip structure is exposed to the second dielectric layer. Because the corresponding laser through hole is not needed to be manufactured on the dielectric layer on the top of the carrier plate structure through laser drilling, the problems of short circuit or empty connection of adjacent conducting wire parts due to the connection of the adjacent conducting wire parts caused by the precision limitation of the laser drilling and the influence of thermal hole expanding can be solved, and the purposes of improving the use reliability and the stability of the substrate structure are achieved.

Another main technical means adopted to achieve the above object is a method for manufacturing the substrate structure of the embedded component, comprising the following steps.

The top of the carrier structure is recessed to form a containing groove, and the carrier structure is provided with a plurality of first circuits and a plurality of second circuits, so that the first ends of the second circuits are exposed out of the top of the carrier structure, and the second ends of the second circuits are exposed out of the bottom of the carrier structure.

A first dielectric layer is arranged at the bottom of the carrier plate structure.

And a chip structure with a plurality of lead members is arranged in the containing groove of the carrier plate structure in advance.

And arranging a second dielectric layer on the top of the carrier plate structure and the chip structure.

And arranging a first circuit layer-adding structure on the second dielectric layer, the conducting wire of the chip structure and the first end part of the second circuit of the carrier plate structure, and electrically connecting the first circuit layer-adding structure with the corresponding conducting wire of the chip structure and the first end part of the corresponding second circuit of the carrier plate structure.

And arranging a second circuit layer-adding structure on the first dielectric layer and the second end part of the second circuit of the carrier plate structure, and electrically connecting the second end part of the second circuit corresponding to the carrier plate structure.

Optionally, the chip structure includes a bridge chip and a wire guide structure, the bridge chip has a top and a bottom opposite to each other, a plurality of lines and a plurality of contacts, the lines are disposed in the bridge chip, the contacts are disposed on the top of the bridge chip at intervals, and the wire guide structure has a fixing layer and the wire guide. The step of forming the chip structure comprises: arranging the fixed layer on the carrier, and forming a plurality of through holes penetrating through the top and the bottom of the fixed layer; arranging the wire guiding members in the through holes of the fixing layer, wherein the first end parts of the wire guiding members are respectively contacted with the carrying member, and the second end parts of the wire guiding members are respectively exposed out of the bottom of the fixing layer; arranging the top of the bridging chip on the bottom of the fixed layer, and electrically connecting the second end of the wire guide with corresponding contacts on the bridging chip respectively; removing the carrier; removing the top of the fixing layer to expose the first end of the wire guide.

Optionally, before the chip structure is disposed in the accommodating groove of the carrier structure, an adhesive layer is disposed in the accommodating groove, and then the chip structure is disposed on the adhesive layer in the accommodating groove.

Optionally, an electrical connection layer is further disposed on the first line build-up structure.

Optionally, at least one chip is further disposed on the top of the carrier structure of the substrate structure, the chip having a plurality of contacts, and the step of disposing the chip includes: and arranging the chip on the top of the carrier plate structure, and enabling the contact points of the chip to be respectively and electrically connected with the first end part of the corresponding second circuit on the carrier plate structure and the corresponding conducting wire piece on the chip structure through the electric connection layer.

According to the method, the chip structure which is preset and manufactured by the semiconductor manufacturing process and is provided with the conducting wire member in advance is fixedly arranged in the accommodating groove of the carrier plate structure, the second dielectric layer is arranged on the top of the carrier plate structure to protect the chip structure, and the conducting wire member of the chip structure is exposed out of the second dielectric layer. Because the corresponding laser perforation is not needed to be manufactured on the dielectric layer on the top of the carrier plate structure by laser drilling, the problems of short circuit or empty connection of adjacent conducting wire parts due to the connection of the adjacent conducting wire parts caused by the precision limitation of the laser drilling and the influence of thermal hole expanding can be reduced, thereby achieving the purpose of improving the use reliability and the stability of the substrate structure.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

FIG. 1 is a schematic diagram of a substrate structure of an embedded component according to the present invention;

FIG. 2 is a flow chart illustrating a method for fabricating a substrate structure of an embedded component according to the present invention;

FIG. 3 is a schematic diagram of a carrier structure according to the present invention;

FIG. 4 is a schematic view illustrating a chip structure and a first dielectric layer disposed on a carrier structure according to the present invention;

FIG. 5 is a schematic flow chart of the present invention for forming a chip structure;

FIG. 6 is a schematic diagram of a first fabrication process of the chip structure of the present invention;

FIG. 7 is a second process flow diagram of the chip structure of the present invention;

FIG. 8 is a third process flow diagram of the chip structure of the present invention;

FIG. 9 is a fourth process flow diagram of the chip structure of the present invention;

FIG. 10 is a schematic diagram of a fifth process flow of the chip structure of the present invention;

FIG. 11 is a sixth process flow diagram of the chip structure of the present invention;

FIG. 12 is a seventh fabrication flow diagram of the chip structure of the present invention;

FIG. 13 is a schematic view of an eighth process flow for fabricating a chip structure according to the present invention;

FIG. 14 is a ninth fabrication flow diagram of the chip architecture of the present invention;

FIG. 15 is a schematic view illustrating a second dielectric layer disposed on a carrier structure and a chip structure according to the present invention;

fig. 16 is a schematic view illustrating a first circuit build-up structure and a second circuit build-up structure disposed on a carrier structure according to the present invention.

Reference numerals

10 carrier plate structure

11 top of the container

12 bottom

13 first line

14 second line

15 containing groove

16 adhesive layer

141 first end part

142 second end portion

20 chip structure

21 wire guide

211 first end portion

212 second end portion

22 bridge chip

221 Top part

222 bottom part

223 line

224 contact

23 wire guide structure

231 anchoring layer

2311 top of the tower

2312 bottom

2313 perforating

24 carrier

25 photo-resist mask layer

26 conductive connection layer

261 electric connector

262 insulating protective layer

31 first dielectric layer

311 hole

32 second dielectric layer

321 top part

322 bottom

323 holes

41 first line layer-adding structure

42 second circuit layer-adding structure

51 electric connection layer

52 chip

521 contact

S61, S62, S63, S64, S65 and S66 steps

S71, S72, S73, S74 and S75 steps

Detailed Description

The drawings shown in the present application are all partial cross-sectional views of the carrier structure, and the number and the size of the relevant structures shown in the drawings are only for reference, and are not intended to limit the specific structure of the carrier structure of the present application. In addition, the directional relationships described herein are illustrative in terms of the directions shown in the drawings and are not intended to be limiting.

Referring to fig. 1, an embodiment of a substrate structure of an embedded component of the invention includes a carrier structure 10, a chip structure 20 pre-installed with a plurality of leads 21, a first dielectric layer 31, a second dielectric layer 32, a first circuit build-up structure 41, and a second circuit build-up structure 42. The carrier structure 10 has a top 11 and a bottom 12 opposite to each other, the chip structure 20, the second dielectric layer 32 and the first circuit build-up structure 41 are disposed on the top 11 of the carrier structure 10, and the first dielectric layer 31 and the second circuit build-up structure 42 are disposed on the bottom 12 of the carrier structure 10.

For a specific structure of the substrate structure of the embedded component and a corresponding manufacturing method of the present invention, please refer to the flowchart of the manufacturing method of the substrate structure of the embedded component shown in fig. 2. The relative relationship, the arrangement manner, and the connection relationship of the related structures will be described together by describing the method of manufacturing the substrate structure.

Referring to fig. 1 to 3, regarding the structure of the carrier structure 10, the carrier structure 10 has the top portion 11 and the bottom portion 12, and the carrier structure 10 further has a plurality of first lines 13 and a plurality of second lines 14. Wherein, part of the first wires 13 can be electrically connected with part of the second wires 14, and the first wires 13 and the second wires 14 are used for transmitting signals. The second wires 14 respectively have a first end 141 and a second end 142 opposite to each other, the first wires 13 and the second wires 14 are disposed in the carrier board structure 10, the first ends 141 of the second wires 14 of the carrier board structure 10 are respectively exposed at the top 11 of the carrier board structure 10, and the second ends 142 of the second wires 14 of the carrier board structure 10 are respectively exposed at the bottom 12 of the carrier board structure 10. In order to accommodate and dispose the chip structure 20 in the carrier structure 10, as shown in step S61, a recess 15 is formed in the top portion 11 of the carrier structure 10, wherein the position of the recess 15 may be, but is not limited to, an intermediate position disposed on the top portion 11 of the carrier structure 10. In this embodiment, the carrier structure 10 may be a printed circuit board or a substrate with a circuit fabricated in advance.

Referring to fig. 1, 2 and 4, in step S62, the first dielectric layer 31 is disposed on the bottom 12 of the carrier structure 10, and the first dielectric layer 31 covers the second end portion 142 of the second circuit 14. In the present embodiment, the first dielectric layer 31 may be a dielectric oxide film (such as silicon dioxide, etc.), an epoxy resin, etc., and is formed by a thin film forming method (such as sputtering, evaporation, or Coating). After the step S62 is completed, as shown in step S63, a chip structure 20 with a plurality of wire guides 21 pre-arranged therein is disposed in the accommodating slot 15 of the carrier structure 10, so that the chip structure 20 is disposed on the top 11 of the carrier structure 10. In order to enhance the bonding strength between the chip structure 20 and the carrier structure 10, before the chip structure 20 with a plurality of wires 21 is disposed in the receiving slot 15 of the carrier structure 10 in step S63, an adhesive layer 16 is disposed in the receiving slot 15, and then the chip structure 20 is disposed on the adhesive layer 16 in the receiving slot 15, so that the adhesive layer 16 achieves the effect of enhancing the bonding between the chip structure 20 and the carrier structure 10.

In order to explain how to form the specific manufacturing process of the chip structure 20 pre-installed with a plurality of wire guides 21 and the connection relationship of the related structures, please refer to fig. 1, 5, and 6. The chip structure 20 includes a bridge chip 22 and a wire guide structure 23. The bridge chip 22 has a top 221 and a bottom 222 opposite to each other, a plurality of traces 223 and a plurality of contacts 224, the traces 223 are disposed in the bridge chip 22, the contacts 224 are disposed on the top 221 of the bridge chip 22 at intervals, and the wire guide structure 23 has a fixing layer 231 and the wire guide 21.

In the present embodiment, referring to fig. 5 to 7, a carrier 24 is provided, and as shown in step S71, the fixing layer 231 is formed on the carrier 24, and a plurality of through holes 2313 are formed on the fixing layer 231 and are arranged at intervals and penetrate through the top 2311 and the bottom 2312 of the fixing layer 231. Wherein the top 2311 of the pinned layer 231 is in contact with the carrier 24. The fixing layer 231 may be a dielectric oxide film (such as silicon dioxide), epoxy resin, etc., and is formed by a thin film forming method (such as sputtering, evaporation, or Coating). The through hole 2313 may be formed by an etching method.

In this embodiment, referring to fig. 5, 8 and 9, as shown in step S72, a photoresist shielding layer 25 is disposed on the bottom 2312 of the fixing layer 231, and then the wire guide 21 is disposed in the through hole 2313 of the fixing layer 231, the first end 211 of the wire guide 21 contacts the carrier 24, and the second end 212 of the wire guide 21 is exposed to the bottom 2312 of the fixing layer 231. The wire guide 21 can be manufactured by a metal coating manufacturing method (such as sputtering, evaporation, or electroplating). The shape of the wire guide 21 is T-shaped in the direction of fig. 9, but is inverted T-shaped in the direction of fig. 1, and only changes the direction without affecting the actual function. After the wire guide 21 and the fixing layer 231 are completed, the wire guide structure 23 is completed, and the photoresist mask layer 25 is removed as shown in fig. 10.

Referring to fig. 5, 11 and 12, the bridge chip 22 is combined with the wire guide structure 23, wherein in step S73, the top 221 of the bridge chip 22 is disposed on the bottom 2312 of the fixing layer 231, so that the second end 212 of the wire guide 21 is electrically connected to the corresponding contact 224 on the bridge chip 22. In order to enhance the bonding strength between the bridge chip 22 and the wire guide structure 23 and provide sufficient support, a conductive connection layer 26 is further disposed between the bridge chip 22 and the wire guide structure 23, the conductive connection layer 26 includes a plurality of electrical connectors 261 and an insulating protection layer 262, the electrical connectors 261 are electrically connected to the corresponding second ends 212 of the wire guide 23 and the corresponding contacts 224 of the bridge chip 22, respectively, and the insulating protection layer 262 is supported between the bridge chip 22 and the wire guide structure 23.

Further, as shown in fig. 5 and 13, in step S74, the carrier 24 is removed, wherein the carrier 24 may be removed by, for example, lift off process (lift off) such as laser, etching, etc. Referring to fig. 5 and 14, after the carrier 24 is removed, in step S75, the top portion 2311 of the fixing layer 231 is removed to expose the first end portion 211 of the wire member 21, wherein the top portion 2311 of the fixing layer 231 can be removed by dry etching or wet etching. The manufacturing of the chip structure 20 is completed by the semiconductor manufacturing method shown in the above steps S71 to S75, so that the chip structure 20 with the wire guides 21 is manufactured in advance, and the manufacturing efficiency, accuracy and reliability of the substrate structure of the invention can be effectively improved.

According to the above description of the chip structure 20, in the present embodiment, referring to fig. 2 and 15, in step S64, the second dielectric layer 32 is disposed on the top 11 of the carrier structure 10 and on the chip structure 20, so as to cover the first end portion 141 of the second line 14 of the carrier structure 10 and the chip structure 20 through the second dielectric layer 32, thereby achieving the protection effect and enhancing the bonding strength between the chip structure 20 and the carrier structure 10.

In the present embodiment, the second dielectric layer 32 may be a dielectric oxide film (such as silicon dioxide, etc.), an epoxy resin, etc., and is formed by a thin film forming method (such as sputtering, evaporation, or Coating).

After the second dielectric layer 32 is disposed, in order to expose the first end portion 141 of the second circuit 14 of the carrier structure 10 and the wire guiding element 21 of the chip structure 20 for connection with other external components, please refer to fig. 2, 15 and 16. The second dielectric layer 32 has a top portion 321 and a bottom portion 322 opposite to each other, and referring to step S65, the top portion 321 of the second dielectric layer 32 is removed, and a plurality of holes 323 corresponding to the first end portions 141 of the second wires 14 of the carrier structure 10 are formed on the bottom portion 322 of the second dielectric layer 32, so that the wire guides 21 of the chip structure 20 are exposed to the second dielectric layer 32, and the first end portions 141 of the second wires 14 of the carrier structure 10 are exposed through the holes 323. The first circuit build-up structure 41 is disposed at the bottom 322 and the hole 323 of the second dielectric layer 32 and the wire guide 21 of the chip structure 20, and the first circuit build-up structure 41 is electrically connected to the wire guide 21 of the chip structure 20 and the first end portion 141 of the corresponding second circuit 14 on the carrier structure 10. In the present embodiment, the top portion 321 of the second dielectric layer 32 is removed by dry etching or wet etching, and then the hole 323 corresponding to the first end portion 141 of the second circuit 14 of the carrier structure 10 is formed on the bottom portion 322 of the second dielectric layer 32 by laser drilling.

After the fabrication of the first circuit build-up structure 41 is completed, referring to fig. 2 and 16, in step S66, a plurality of holes 311 corresponding to the second end portions 142 of the second circuits 14 of the carrier structure 10 are formed on the first dielectric layer 31, and the second end portions 142 of the second circuits 14 of the carrier structure 10 are exposed through the holes 311. Then, the second circuit build-up structure 42 is disposed in the hole 311, and the second circuit build-up structure 42 is electrically connected to the second end portion 142 of the corresponding second circuit 14 on the carrier structure 10. The second circuit build-up structure 42 is electrically connected to the first circuit build-up structure 41 via the second circuit 14 of the carrier board structure 10. The fabrication of the substrate structure of the present invention is completed according to the steps S61 to S66 of the fabrication method of the present invention described above.

In this embodiment, referring to fig. 1, an electrical connection layer 51 is further disposed on the carrier structure 10 and the chip structure 20, and the electrical connection layer 51 is electrically connected to the first end portion 141 of the corresponding second circuit 14 on the carrier structure 10 and the corresponding wire 21 on the chip structure 20 for subsequent electrical connection with other components. In this embodiment, the electrical connection layer 51 includes a plurality of pads.

After the substrate structure of the present invention is manufactured, if it is to be electrically connected to an external device, please refer to fig. 1, at least one chip 52 is further disposed on the top 11 of the carrier structure 10 of the substrate structure, and two chips 52 are disposed in the present embodiment for illustration and not limitation. The chips 52 respectively have a plurality of contacts 521, wherein a part of the contacts 521 in one chip 52 is electrically connected to the corresponding wire guide 21 on the chip structure 20 through the corresponding electrical connection layer 51, and the other part of the contacts 521 is electrically connected to the first end 141 of the corresponding second wire 14 on the carrier board structure 10 through the corresponding electrical connection layer 51. A part of the contacts 521 of the other chip is electrically connected to the corresponding wire guides 21 on the chip structure 20 via the corresponding electrical connection layer 51, and the rest of the contacts 521 are electrically connected to the first end portions 141 of the corresponding second wires 14 on the carrier board structure 10 via the corresponding electrical connection layer 51. The chip 52 may be a Light Emitting Diode (LED), an integrated circuit, or the like.

According to the above, the chip structure 20, which is pre-configured and manufactured by a semiconductor process method to form the wire guides 21, is fixedly disposed in the accommodating groove 15 of the carrier structure 10, and the second dielectric layer 32 is disposed on the top portion 11 of the carrier structure 10 to protect the chip structure 20, so that the wire guides 21 of the chip structure 20 are exposed to the second dielectric layer 32. Since the corresponding laser through hole is not required to be formed on the second dielectric layer 32 on the top 11 of the carrier structure 10 by laser drilling, the problems of short circuit or empty connection of adjacent wires due to the connection of the wires caused by the laser drilling precision and the limitation of thermal hole expansion can be improved, thereby achieving the purpose of improving reliability and stability.

The above description is only an example of the present invention, and is not intended to limit the scope of the present invention.