阅读说明：本技术 半导体器件的封装焊接结构 (Packaging welding structure of semiconductor device ) 是由 林志东 黄治浩 魏鸿基 郭佳衢 于 2021-07-28 设计创作，主要内容包括：本发明公开了一种半导体器件的封装焊接结构,包括衬底、沟道层、势垒层、第一金属层、第二金属层、第一钝化层、第三金属层、上金属层和保护层,通过沟道层、势垒层、第一金属层、第二金属层、第一钝化层组合可用于ESD防护,该部分结构设置在第三金属层下方,同时在第三金属层及保护层上方设置上金属层。上金属层可以改善因保护层的蚀刻导致第三金属层表面粗糙而影响引线质量的问题,提高封装良率和器件可靠性,同时采用电镀工艺可以有效节省成本。该技术可以广泛应用在各种半导体器件的封装制程中,可以明显改善封装良率。(The invention discloses a packaging and welding structure of a semiconductor device, which comprises a substrate, a channel layer, a barrier layer, a first metal layer, a second metal layer, a first passivation layer, a third metal layer, an upper metal layer and a protective layer. The upper metal layer can solve the problem that the surface of the third metal layer is rough due to the etching of the protective layer to influence the quality of the lead, the packaging yield and the reliability of the device are improved, and meanwhile, the electroplating process can effectively save the cost. The technology can be widely applied to the packaging process of various semiconductor devices, and can obviously improve the packaging yield.)

1. A package soldering structure of a semiconductor device, characterized in that: the packaging and welding structure is arranged outside an active region of the semiconductor device and comprises a substrate, a channel layer, a barrier layer, a first metal layer, a second metal layer, a first passivation layer, a third metal layer, an upper metal layer and a protective layer, wherein the channel layer is arranged in a first preset region on the substrate, the first metal layer is arranged on the substrate outside the first preset region, the barrier layer is arranged in a second preset region on the channel layer, the second metal is arranged in a third preset region on the barrier layer, the first passivation layer covers the channel layer, the barrier layer, the second metal layer and the first metal layer, the third metal layer is arranged on the first passivation layer above the barrier layer, the protective layer covers the third metal layer and the first passivation layer, and an opening region is arranged above the third metal layer, the upper metal layer is arranged on the opening region and protrudes to extend to the top surface of the peripheral protective layer.

2. The package solder structure of semiconductor device according to claim 1, wherein: the upper metal layer comprises a seed layer and an electroplating metal layer which are sequentially stacked, the seed layer covers the bottom and the side wall of the opening area and extends to the top surface of the protective layer on the periphery, and the electroplating metal layer is arranged above the seed layer, fills the opening area and protrudes out of the opening area.

3. The package solder structure of a semiconductor device according to claim 2, wherein: the thickness of the electroplating metal layer is 3-5 microns.

4. The package solder structure of a semiconductor device according to claim 2, wherein: the seed layer comprises a TiW layer and an electroplating seed layer, the thickness of the TiW layer is 10-80 angstroms, and the thickness of the electroplating seed layer is 1000-3500 angstroms.

5. The package solder structure of semiconductor device according to claim 4, wherein: the electroplating metal layer, the electroplating seed layer and the third metal layer are all made of gold.

6. The package solder structure of semiconductor device according to claim 1, wherein: the upper metal layer is located in the area range of the protective layer above the third metal layer at the projection edge of the protective layer.

7. The package solder structure of semiconductor device according to claim 6, wherein: the distance between the projected edge of the upper metal layer on the protective layer and the outer edge of the top surface of the protective layer above the third metal layer is 0.5-2 microns.

8. The package solder structure of a semiconductor device according to any one of claims 1 to 7, wherein: the semiconductor device further comprises a second passivation layer arranged between the channel layer and the first passivation layer.

9. The package solder structure of a semiconductor device according to any one of claims 1 to 7, wherein: the thickness of the protective layer around the opening region is 6000-8000 angstroms.

10. The package solder structure of a semiconductor device according to any one of claims 1 to 7, wherein: the thickness of the first metal layer is 500-2000 angstroms, the thickness of the second metal layer is 1000-3000 angstroms, and the thickness of the third metal layer is 3-5 microns.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a packaging and welding structure of a semiconductor device.

Background

There are three ways of circuit connection in a chip package: flip chip Bonding, tape automated Bonding, Wire Bonding (Wire Bonding), one of the most widely used processes in semiconductor packaging at present, is the Wire Bonding process, which assumes the function of tightly connecting the internal chip and the external frame. The wire bonding process can be classified into ball bonding and wedge bonding according to the process technology, and can be classified into thermocompression bonding, ultrasonic bonding and thermosonic bonding according to the bonding principle. Each bonding wire must be attached to the chip without error during the bonding process, and any error can cause quality problems.

The conventional common lead bonding process relates to a two-time bonding process, wherein a first bonding adopts a spherical welding mode to weld a lead on a bonding pad of a chip, a second bonding adopts wedge welding, and one end of the lead which is welded on a device is led out and welded on an external frame to connect the chip and the external frame, so that signal transmission is realized. In the prior thermosonic welding process, in the two bonding processes, the metal wire and the pressure welding point are simultaneously heated and ultrasonic waves are added, so that the contact surface generates plastic deformation, an oxide film on the interface is damaged and activated, and the two metals on the contact surface are mutually diffused to realize connection.

At present, a wire bonding process is also selected for packaging wires after the HBT device manufacturing process is completed. In order to protect the reliability of the HBT device, a protective layer is manufactured on the surface of the device in the manufacturing process of the HBT device, an opening is only formed in a PAD area of the protective layer, and the surface of a PAD (PAD) is etched in the process of etching the opening in the protective layer, so that the surface of the PAD becomes rough, and the bonding process of a lead is influenced. In addition, the ESD protection design near the package position needs to be considered during the device design, and if the ESD protection structure is added at the package position, the device area will increase, and the electrical performance will be affected by improper design.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a packaging and welding structure of a semiconductor device.

In order to achieve the above purpose, the technical scheme of the invention is as follows:

a package welding structure of a semiconductor device is arranged outside an active region of the semiconductor device and comprises a substrate, a channel layer, a barrier layer, a first metal layer, a second metal layer, a first passivation layer, a third metal layer, an upper metal layer and a protection layer, wherein the channel layer is arranged in a first preset region on the substrate, the first metal layer is arranged on the substrate outside the first preset region, the barrier layer is arranged in a second preset region on the channel layer, the second metal is arranged in a third preset region on the barrier layer, the first passivation layer covers the channel layer, the barrier layer, the second metal layer and the first metal layer, the third metal layer is arranged on the first passivation layer above the barrier layer, and the protection layer covers the third metal layer and the first passivation layer, and an opening area is arranged above the third metal layer, and the upper metal layer is arranged on the opening area and protrudes to extend to the top surface of the peripheral protective layer.

In an optional embodiment, the upper metal layer includes a seed layer and an electroplated metal layer stacked in sequence, the seed layer covers the bottom and the sidewalls of the opening region and extends to the top surface of the peripheral protective layer, and the electroplated metal layer is disposed above the seed layer, fills the opening region and protrudes above the opening region.

In an optional embodiment, the thickness of the electroplated metal layer is 3-5 microns.

In an optional embodiment, the seed layer comprises a TiW layer and an electroplating seed layer, the thickness of the TiW layer is 10-80 angstroms, and the thickness of the electroplating seed layer is 1000-3500 angstroms.

In an optional embodiment, the plating metal layer, the plating seed layer, and the third metal layer are all made of gold.

In an alternative embodiment, the upper metal layer is located within the area of the protective layer above the third metal layer at the projected edge of the protective layer.

In an alternative embodiment, the distance between the projected edge of the upper metal layer on the protective layer and the outer edge of the top surface of the protective layer above the third metal layer is 0.5-2 microns.

In an optional embodiment, the semiconductor device further comprises a second passivation layer disposed between the channel layer and the first passivation layer.

In an optional embodiment, the thickness of the protective layer around the opening region is 6000 to 8000 angstroms.

In an optional embodiment, the thickness of the first metal layer is 500-2000 angstroms, the thickness of the second metal layer is 1000-3000 angstroms, and the thickness of the third metal layer is 3-5 microns.

The invention has the beneficial effects that:

(1) and packaging the lead on the surface of the upper metal layer above the third metal layer, wherein the upper metal layer can increase the thickness of the third metal layer, effectively improve the surface roughness of the third metal layer and avoid the phenomenon of wire breakage caused by infirm bonding in the process of wire bonding, thereby improving the quality of the lead, increasing the reliability of the device and effectively saving the cost.

(2) The film layer structure combination below the third metal layer can be used for ESD protection, damage of ESD to devices is effectively reduced, design diversity is increased, the area of the devices is reduced, electrical performance is improved, and the fact that the surface of the third metal layer is rougher due to the fact that the height difference of the devices is caused by the fact that the ESD protection structure is integrated below the third metal layer can be reduced, and therefore the strength and the reliability of lead bonding are affected.

(3) The lead wire packaging structure can be widely applied to the packaging process of various semiconductor devices, the lead wire quality in the packaging process is improved, the packaging yield is improved, and the application value is great.

Drawings

Fig. 1 is a schematic view of a package-bonding structure of a semiconductor device of an embodiment of the present invention;

fig. 2a-2d are process flow diagrams of package solder structures of semiconductor devices according to embodiments of the present invention.

Detailed Description

The invention is further explained below with reference to the figures and the specific embodiments. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The definitions of the top and bottom relationships of the relative elements and the front and back sides of the figures described herein are understood by those skilled in the art to refer to the relative positions of the components and thus all of the components may be flipped to present the same components and still fall within the scope of the present disclosure.

In the embodiment of the invention, the device above the active region of the semiconductor device is a Heterojunction Bipolar Transistor (HBT) device, and the packaging welding structure is arranged outside the active region. The package bonding structure of the HBT device as the device of the active region is taken as an example below.

Referring to fig. 1, a package soldering structure of a semiconductor device includes a substrate 1, a channel layer 2, a barrier layer 3, a first metal layer 4, a second metal layer 5, a first passivation layer 6, a second passivation layer 7, a third metal layer 8, an upper metal layer 9, and a protective layer 10. The substrate 1 is made of GaAs, Si, SiC, GaN or sapphire, the channel layer 2 is arranged in a first preset area on the substrate 1, the barrier layer 3 is arranged in a second preset area on the channel layer 2, the channel layer 2 is made of n-type GaAs, and the barrier layer 3 is made of p-type GaAs. The first metal layer 4 is arranged on the substrate 1 at a position outside the first preset area, and the second metal 5 is arranged on the barrier layer 3 at a third preset area, wherein the first metal layer 4 can be AuGe/Ni/Ag/Au and has a thickness of 500-2000 angstroms, preferably 1000 angstroms, and the second metal layer 5 can be Ti/Pt/Au and has a thickness of 1000-3000 angstroms, preferably 2000 angstroms. A second passivation layer 7 is disposed over the channel layer 2, the first passivation layer 6 is covered on the second passivation layer 7, the barrier layer 3, the second metal layer 5 and the first metal layer 4, wherein the material of the first passivation layer 6 and the second passivation layer 7 may be SiO₂Or Si₃N₄The thickness is 2000-5000 angstroms, preferably 3000 angstroms. A PN junction is formed between the channel layer 2 and the barrier layer 3, and a structure formed by the channel layer 2, the barrier layer 3, the first metal layer 4, the second metal layer 5, the first passivation layer 6 and the second passivation layer 7 above the substrate 1 can be used for ESD protection and used as an ESD protection structure. The manufacture of the channel layer 2, the barrier layer 3, the first metal layer 4, the second metal layer 5, the first passivation layer 6 and the second passivation layer 7 is the corresponding film in the HBT deviceThe layer is manufactured on the same layer, most ESD current in the device comes from the outside of the circuit, when the device in the active area works normally, the ESD current is in a cut-off state (high-resistance state) and does not affect the normal work of the device, when the circuit generates abnormal overvoltage and reaches the breakdown voltage of the circuit, the ESD current is rapidly changed from the high-resistance state to the low-resistance state, a low-resistance conduction path is provided for instant current, and meanwhile, the abnormal high voltage is clamped within a safety level, so that the protected HBT device is protected; when the abnormal overvoltage disappears, the circuit is restored to a high-resistance state, and the circuit works normally.

Further, the third metal layer 8 is disposed on the first passivation layer 6 above the barrier layer 3, the material of the third metal layer 8 may be gold or copper, the thickness of the third metal layer 8 is 3-5 micrometers, and preferably 4 micrometers, and the third metal layer 8 may be disposed as a PAD, so that the ESD protection structure is designed below the PAD. The protective layer 10 covers the third metal layer 8 and the first passivation layer 6, an opening region 81 is arranged above the third metal layer 8, the third metal layer 8 is exposed in the opening region 81, and the height of the opening region 81 is 6000-8000 angstroms.

In a specific embodiment, the upper metal layer 9 is disposed on the opening region 81 and protrudes to extend to the top surface of the protective layer 10 at the periphery. The upper metal layer 9 is located in the range of the protective layer 10 above the third metal layer 8 at the projection edge of the protective layer 10, and is 0.5-2 micrometers, preferably 1 micrometer away from the outer edge of the top surface of the protective layer 10 above the third metal layer 8. The upper metal layer 9 is disposed above the opening region 81 and extends to the top surface of the surrounding passivation layer, so as to increase the contact area of the lead and avoid metal disconnection.

In a specific embodiment, the upper metal layer 9 includes a seed layer 91 and a metal plating layer 92 stacked in sequence, the seed layer 91 covers the bottom and the sidewalls of the open region 81 and extends to the top surface of the peripheral protective layer 10, and the metal plating layer 92 is disposed above the seed layer 91, fills the open region 81 and protrudes above the open region 81. The thickness of the electroplated metal layer 92 is 3-5 micrometers, and preferably 4 micrometers. The seed layer 91 includes a TiW layer and an electroplating seed layer, and the electroplating metal layer 92 and the electroplating seed layer are made of gold. The thickness of the TiW layer is 10-80 angstroms, preferably 60 angstroms, and the thickness of the electroplating seed layer is 1000-3500 angstroms, preferably 2000 angstroms.

In this embodiment, the ESD protection structure is disposed below the third metal layer 8, the device has a higher height difference, and the opening region 81 is etched through the protection layer 10, and meanwhile, the etching solution corrodes the third metal layer 8, so that the surface of the third metal layer 8 becomes rougher, and even a wire breaking problem may be caused during lead packaging, which affects the packaging yield. An upper metal layer 9 is thus provided above the third metal layer 8. Thereby it can effectively improve the problem that 8 rough surfaces of third metal level influence the lead wire quality to go up the formation of metal level 9 for the design of the integrated ESD protection architecture below third metal level 8 is more reasonable, under the circumstances that does not influence the ESD protection, can guarantee good encapsulation lead wire effect, improves the reliability of device. The upper metal layer 9 adopts an electroplating process, so that the process cost is reduced, the seed layer 91 can improve the adhesion of metal, and the stripping and falling phenomena are avoided.

Referring to fig. 2a-2d and the flow chart of fig. 1, the above-described upper metal layer 9 structure is prepared by the following method:

referring to fig. 2a, a protective layer 10 with a thickness of 6000 to 8000 angstroms is formed on a wafer on which a device process and an ESD protection structure are completed, and an opening region 81 is etched above the third metal layer 8;

referring to fig. 2b, a layer of TiW with a thickness of 60 angstroms and a layer of gold (i.e., a plating seed layer) with a thickness of 2000 angstroms are sequentially sputtered on the surface of the structure to form a seed layer 91;

referring to fig. 2c, coating a photoresist layer 93 on the surface of the seed layer 91, and exposing and developing to form a display window above the third metal layer 8, wherein the width of the display window is greater than the opening region 81;

referring to fig. 2d, a 4 μm thick electroplated metal layer 92 is deposited over the opening region 81 and the display window by electroplating, and a photoresist layer 93 is stripped by chemical solutions such as N-methylpyrrolidone;

the gold (i.e., the plating seed layer) exposed outside the plated metal layer 92 is removed by reverse plating and the exposed TiW is etched by wet etching to obtain the final structure, referring to fig. 1.

The packaging welding structure manufactured in the traditional mode etches PAD in the etching process of the protective layer simultaneously to cause rough surface of PAD, the design of the ESD protection structure added below is more obvious, the wire bonding yield is greatly influenced, and the rough surface of PAD easily causes the infirm wire bonding. Compared with a package welding structure manufactured in a traditional mode, the package welding structure provided by the invention can meet the requirement of designing an ESD protection structure below the PAD, and meanwhile, the upper metal layer is added above the PAD, so that the bonding strength of a lead is prevented from being influenced by the rough surface of the PAD during packaging, the packaging yield is improved, and the cost is effectively saved. The packaging welding structure is suitable for packaging processes of various semiconductor devices and has great application value.

The above embodiments are only intended to further illustrate the package bonding structure of the semiconductor device of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.