阅读说明：本技术 半导体结构 (Semiconductor structure ) 是由 廖忠志 于 2021-06-30 设计创作，主要内容包括：一种半导体结构,包括一第一晶体管和一第二晶体管,其各自具有一源极端、一漏极端,以及一栅极端。半导体结构还包括：一编程线；一第一金属板,设置于第一晶体管和第二晶体管之上；一第一绝缘体,设置于第一金属板之上；一第二金属板,设置于第一绝缘体之上；一第二绝缘体,设置于第二金属板之上；以及一第三金属板,设置于第二绝缘体之上。第一金属板、第一绝缘体,以及第二金属板形成一第一反熔丝元件。第二金属板、第二绝缘体,以及第三金属板形成一第二反熔丝元件。(A semiconductor structure includes a first transistor and a second transistor each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes: a programming line; a first metal plate disposed over the first transistor and the second transistor; a first insulator disposed on the first metal plate; a second metal plate disposed on the first insulator; a second insulator disposed on the second metal plate; and a third metal plate disposed on the second insulator. The first metal plate, the first insulator, and the second metal plate form a first antifuse element. The second metal plate, the second insulator, and the third metal plate form a second antifuse element.)

1. A semiconductor structure, comprising:

a first transistor and a second transistor, wherein each of the first transistor and the second transistor has a source terminal, a drain terminal, and a gate terminal;

a programming line;

a first metal plate disposed over the first transistor and the second transistor;

a first insulator disposed on the first metal plate;

a second metal plate disposed on the first insulator;

a second insulator disposed on the second metal plate; and

a third metal plate disposed on the second insulator, wherein the first metal plate, the first insulator, and the second metal plate form a first antifuse element, wherein the second metal plate, the second insulator, and the third metal plate form a second antifuse element, wherein the source terminal of the first transistor is electrically connected to the first metal plate, the source terminal of the second transistor is electrically connected to the third metal plate, and the program line is electrically connected to the second metal plate.

Technical Field

The present disclosure relates to a semiconductor structure.

Background

The semiconductor Integrated Circuit (also known as "IC") industry has experienced exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each of which has smaller, more complex circuits than the previous generation. In the course of IC development, functional Density (i.e., the number of Interconnected devices per Chip Area) generally increases, but Geometry Size (i.e., the smallest component (or line) that can be created using a process) generally decreases. Such a scaled-down process generally has the advantages of improving production efficiency and reducing associated costs. The foregoing scaling down process also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advancements.

For example, antifuses (Anti-fuses) have been used in ICs. Antifuses are typically Open fuses (i.e., fuses that are Open Circuit (Open Circuit) or High Impedance (High Impedance)). After Programming, the two ends of the fuse are Electrically Shorted (Electrically short), allowing current to flow between the two ends. Antifuses have been implemented using transistors (transistors) whose Breakdown Path (Breakdown Path) is usually from the Gate (Gate) of the Transistor to either the Channel (Channel) of the Transistor or the Drain (Drain) of the Transistor. As ICs continue to scale down, the reliability, operating Margin, and Resistance Variation (Resistance Variation) of such antifuse technology also become an issue.

Disclosure of Invention

In some embodiments, the present disclosure provides a semiconductor structure comprising: a first transistor and a second transistor, wherein each of the first transistor and the second transistor has a source terminal, a drain terminal, and a gate terminal; a programming line; a first metal plate disposed over the first transistor and the second transistor; a first insulator disposed on the first metal plate; a second metal plate disposed on the first insulator; a second insulator disposed on the second metal plate; and a third metal plate disposed over the second insulator, wherein the first metal plate, the first insulator, and the second metal plate form a first antifuse element, wherein the second metal plate, the second insulator, and the third metal plate form a second antifuse element, wherein the source terminal of the first transistor is electrically connected to the first metal plate, the source terminal of the second transistor is electrically connected to the third metal plate, and the program line is electrically connected to the second metal plate.

In some embodiments, the present disclosure provides a semiconductor structure comprising: a first transistor and a second transistor, wherein each of the first transistor and the second transistor has a source terminal, a drain terminal, and a gate terminal; a word line conductor electrically connected to the gate terminals of the first and second transistors; a programming line conductor; and a vertically stacked pair of anti-fuse elements including a first metal plate, a second metal plate, and a third metal plate, wherein the first metal plate, the second metal plate, and the third metal plate are stacked on the first transistor and the second transistor and separated from each other by a plurality of insulators, the source terminal of the first transistor is electrically connected to the first metal plate, the source terminal of the second transistor is electrically connected to the third metal plate, and the programming line conductor is electrically connected to the second metal plate.

In some embodiments, the present disclosure provides a semiconductor structure comprising: a first transistor having a source terminal, a drain terminal, and a gate terminal; a word line conductor electrically connected to the gate terminal of the first transistor; a bit line conductor electrically connected to the drain terminal of the first transistor; a programming line conductor; and a vertically stacked pair of anti-fuse elements comprising three metal plates vertically stacked, wherein the metal plates are separated from each other by a plurality of insulators, the source terminal of the first transistor is electrically connected to an uppermost one and a lowermost one of the metal plates, and the program line conductor is electrically connected to a middle one of the metal plates.

Drawings

The embodiments of the disclosure can be understood in more detail by reading the following detailed description and examples in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A, 1B, 16A, 16B, 16C, 17 are schematic diagrams showing fuse arrays according to some embodiments of the present disclosure.

FIG. 1C is a diagram illustrating the specific operation of a fuse array according to one embodiment of the present disclosure.

Fig. 2, 3, 6, 7, 9, 10, 11, 13, 14, 15, 18, 20, 21 are cross-sectional views showing a portion of a fuse array according to some embodiments.

Fig. 4, 22 are schematic diagrams showing particular routing of a fuse array according to some embodiments.

Fig. 5, 8, 12, 19 are layout diagrams showing a portion of a fuse array according to some embodiments.

FIG. 23 is a layout diagram showing a portion of a controller for a fuse array according to some embodiments. Figure 24 is a cross-sectional view showing a portion of a semiconductor device incorporating a fuse array, according to some embodiments.

Wherein the reference numerals are as follows:

200: device for measuring the position of a moving object

201: substrate

202, 202(X, Y), 202(X +1, Y), 202(X, Y +1), 202(X +1, Y + 1): controller

204, 204T, 204B, 204(X, Y), 204T (X, Y), 204B (X, Y), 204(X, Y +1), 204T (X, Y +1), 204B (X, Y + 1): fuse element

206_x，206_x-1: interconnection layer

207_x，207_x-1: dielectric layer

208-1, 208-2, 208-3, 208-4, 208-5, 208-6, 208-7, 208-8, 208-9, 208-10, 208-21, 208-22, Via-X-1, Via1, V1, VG: pass-through element

210-1, 210-2, 210-3, 210-4, 210-5, 210-6, 210-7, 210-8, 210-11, 210-21, 210-22: metal wire

250, 252, 254: metal plate

251, 253: insulator

260, 262: signal line

280: active region

BL1, BL2, BL3, BL4, BL-X, BL-X + 1: bit line

Cell: cells

CTRL _ MOS: control terminal

And (4) Fuse: fuse wire

M1: metal layer (interconnect layer)

Program line, Program line-Y +1, Program line-2, Program line-3, Program line-4: programming line

A resistor: resistor with a resistor element

V _ P, V _ R: voltage of

WL1, WL2, WL3, WL4, WL-Y, WL-Y + 1: word line

x: x axis

X: x coordinate

y: y axis

Y: y coordinate

z: z axis

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Also, in the following description, the execution of the first process before the second process may include an embodiment in which the second process is executed immediately after the first process, and may also include an embodiment and a flow in which additional processes may be executed between the first and second processes. Various features may be arbitrarily drawn in different scales for simplicity and clarity. Furthermore, in the description below, the first feature may include an embodiment in which the first and second features are formed in direct contact over the second feature, and may also include an embodiment in which an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

Furthermore, spatially relative terms such as "below," "in.. below," "above," and the like may be used herein for ease of description. As shown, the feature or relationship of a feature to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary use of the word "below …" can include both an orientation of "above …" and "below …". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Further, when a number or range of numbers is described by "about", "approximately", etc., the term covers the number within some variation (e.g., +/-10% or other variation) of the number. Unless otherwise indicated, the present invention may be described in accordance with the knowledge of one skilled in the art in light of the specific techniques disclosed herein. For example, the term "about 5 nm" may encompass the size range of "4.5 nm to 5.5 nm" or "4.0 nm to 5.0 nm".

The present disclosure generally relates to semiconductor devices. More particularly, the present disclosure relates to a semiconductor device having an antifuse (or antifuse element) Integrated therewith. In this disclosure, the words "Anti-Fuse" and "Fuse" are used interchangeably. Traditionally, antifuses are implemented using transistors, whose Breakdown Path (Breakdown Path) is usually from the Gate (Gate) of the transistor to the Channel (Channel) of the transistor or the Drain (Drain) of the transistor. However, such antifuses may be adversely affected by the shrinking transistor size. For example, in certain designs, the reliability and operating margins of such antifuses may also be affected when the transistors are made smaller or three-dimensional, such as in FinFET or Gate-all-around (Gate-all) devices. In addition, flow changes implemented in Front End of Line (FEOL) and mid-Line (MEOL) flows can sometimes adversely affect the performance of the antifuse. It is an object of the present disclosure to overcome such problems. In particular, the present disclosure provides a novel antifuse implemented at a metal layer and over a transistor. In an embodiment of the present disclosure, a fuse structure provides two fuse elements having fuse elements vertically stacked to reduce a cell size, and two ends of each fuse element are metal plates. Once programmed (Programming), the resistance between the terminals of the new fuse will become very small (metal to metal), which is much smaller than the conventional fuse. In a conventional fuse, a Silicon Channel (Silicon Channel) is located in a conductive Path (connecting Path), and its resistance is higher than that of metal. As a result, the Read Current (Read Current) of the new fuse is higher than that of the conventional fuse. In some embodiments of the present disclosure, one Fuse Element (Fuse Cell) has two Fuse elements (Fuse elements) connected in parallel, which improves the reliability of its programmability. Since the new fuse is implemented on a metal layer, the transistor and the trimming of the fuse can be decoupled, providing more freedom for adjusting the programming voltage of the fuse. These and other aspects of the novel fuse are discussed further below in conjunction with fig. 1A-1C, 2. Referring to fig. 1A-24, schematic, operational, cross-sectional and/or layout views of a semiconductor device 200 according to some embodiments are shown.

In some embodiments, the device 200 is part of an IC Chip (Chip), System on Chip (SoC), or a portion thereof, which includes various Passive (Passive) and Active (Active) microelectronic devices, such as: a Resistor (Resistor), a Capacitor (Capacitor), an Inductor (Inductor), a Diode (Diode), a p-type Field Effect Transistor (PFET), an n-type Field Effect Transistor (NFET), a Fin-type Field Effect Transistor (FinFET), a nanoflake FET, a nanowire FET, other types of multi-gate FETs, a Metal-Oxide Semiconductor Field Effect Transistor (Metal-Oxide Semiconductor Field Effect Transistor, MOSFET or MOS FET), a Complementary Metal-Oxide Semiconductor (CMOS) Transistor, a Bipolar Junction Transistor (BJT), a lateral diffusion MOS (Laterally Diffused MOS) Transistor, a high voltage MOS, a high frequency MOS Transistor, or other suitable components or combinations thereof. In some embodiments, the apparatus 200 includes a Non-Volatile Memory (NVM), such as: Non-Volatile Random Access Memory (NVRAM), Flash Memory (Flash Memory), EEPROM (Electrically-Erasable Programmable Read-Only Memory), EPROM (Electrically-Programmable Read-Only Memory), or other suitable Memory types or combinations thereof. Fig. 1A-24 have been simplified for clarity in order to better understand the inventive concepts of the present disclosure. Other functionality may be added to the apparatus 200, and certain functionality described below may be replaced, modified or eliminated in other embodiments of the apparatus 200.

Fig. 1A is a circuit diagram illustrating a device 200 according to the present disclosure, wherein the device 200 includes a Fuse Array (Fuse Array) and includes four Fuse cells (so a 2 × 2 Array). Each fuse element includes a controller Device 202 and a fuse element 204T or 204B. The fuse elements are connected to Word Lines (WL) and Bit Lines (BL). In the fuse array of FIG. 1A, there are four controllers 202 arranged in rows (Row) and columns (Column), named for their X and Y coordinates (Column), 202(X, Y), 202(X +1, Y), 202(X, Y +1), and 202(X +1, Y +1), respectively. For example, each of X, Y may be 0 or any positive integer. The fuse array of fig. 1A may be part of a larger fuse array of device 200. Each controller 202 has a Gate Terminal (Gate Terminal), a Source Terminal (Source Terminal), and a Drain Terminal (Drain Terminal). The gate terminals of the controllers 202 on the same row are all connected to the same word line. For example, the gate terminals of the controller 202(X, Y) and the controller 202(X +1, Y) are connected to the same word line WL-Y, and the gate terminals of the controller 202(X, Y +1) and the controller 202(X +1, Y +1) are connected to the same word line WL-Y + 1. The drain terminals of the controllers 202 on the same column are all connected to the same bit line. For example, the drain terminals of the controller 202(X, Y) and the controller 202(X, Y +1) are connected to the same bit line BL-X, and the drain terminals of the controller 202(X +1, Y) and the controller 202(X +1, Y +1) are connected to the same bit line BL-X + 1. The source terminal of the controller 202 is connected to a fuse element 204, which will be described in detail below. The controllers 202 of the embodiment of FIG. 1A may all be N-type Metal-Oxide Semiconductor Field Effect Transistors (NMOSFETs). Alternatively, the controllers 202 may all be P-type Metal-Oxide Semiconductor Field Effect Transistors (PMOSFETs).

In the fuse array of FIG. 1A, there may be four fuse elements (i.e., two pairs), named 204T (X, Y), 204B (X, Y), 204T (X, Y +1), 204B (X, Y + 1). In the further discussion below (as shown in fig. 2), fuse element 204T (X, Y) is vertically stacked on top of fuse element 204B (X, Y) to form a pair of fuse elements labeled 204(X, Y), and fuse element 204T (X, Y +1) is vertically stacked on top of fuse element 204B (X, Y +1) to form another pair of fuse elements labeled 204(X, Y + 1). Two controllers 202 in the same column share a pair of fuse elements 204. Each fuse element 204T or 204B has two terminals. One of the two terminals is connected to the source terminal of the associated controller 202, and the other of the two terminals is connected to a Program Line (Program Line). In FIG. 1A, there are two Program lines, "Program line-Y" and "Program line-Y + 1". Each controller 202 can be selected by setting the associated bit line and word line to a particular voltage. The program line may be set to a particular voltage for a particular period of time so that the associated fuse element 204 may be programmed.

In the example of FIG. 1B, controller 202(X, Y) may be selected and Program line-Y may be used to Program fuse element 204B (X, Y). Once programmed, the two terminals of the fuse element 204B (X, Y) are Shorted (Shorted), so that the fuse element 204B (X, Y) becomes a Low Resistance Path (e.g., a Low Resistance resistor) that connects the Program line-Y to the source terminal of the controller 202(X, Y). In the example of fig. 1B, the unprogrammed fuse element 204T (X, Y) may remain as an Open Circuit (or a high resistance path).

Fig. 1C illustrates the operation of a fuse array according to an embodiment of the present disclosure, wherein the controller 202 is N-type metal oxide semiconductor field effect transistors (NMOSFETs). The word line, bit line, and program line are all set to specific voltages to program or read the fuse element 204. To program a fuse element, the selected (or associated) program line is set to a high voltage V _ P (e.g., V _ P is higher than 2.5V in one embodiment), the selected word line is set to a voltage between 1/4 and 1/2 of V _ P to enable (Turn On) the associated controller 202, and the selected bit line is set to a low voltage, such as: 0V. At the same time, the unselected program lines and word lines are set to a low voltage (e.g., 0V, or other predetermined low voltage in one embodiment), while the unselected bit lines are set to a voltage between 1/4-1/2 of the high voltage V _ P. Specifically, fuse element 204B (X, Y) is associated with (or selected from) Program line-Y, word line WL-Y, and bit line BL-X; the fuse element 204T (X, Y) is associated with the Program line-Y, the word line WL-Y, and the bit line BL-X + 1; the fuse element 204B (X, Y +1) is associated with the Program line-Y +1, the word line WL-Y +1, and the bit line BL-X; the fuse element 204T (X, Y +1) is associated with a Program line-Y +1, a word line WL-Y +1, and a bit line BL-X + 1.

For example, to Program the fuse element 204B (X, Y), the Program line-Y can be set to the high voltage V _ P, the word line WL-Y can be set to a voltage between 1/4 and 1/2 of the high voltage V _ P, the bit line BL-X can be set to a low voltage, such as: 0V, Program line-Y +1 and word line WL-Y +1 can be set to a low voltage, and bit line BL-X +1 can be set to a voltage between 1/4 and 1/2 of the high voltage V _ P.

To read a fuse element, the selected programming line is set to a voltage V _ R (e.g., V _ R may be 0.75V in one embodiment, and between 0.6V and 1.2V in various embodiments), the selected word line is set to a voltage lower than or equal to V _ R, and the selected bit line is sensed (e.g., by a sense amplifier) to detect the resistance (Impedance) of the fuse element. At the same time, the unselected program lines and word lines can be set to a low voltage (e.g., 0V, or other predetermined low voltage in one embodiment), while the unselected bit lines can be set to 0V, a predetermined low voltage, or left Floating. For example, to read the fuse element 204B (X, Y), the Program line-Y can be set to a high voltage V _ R, the word line WL-Y can be set to a voltage lower than or equal to the high voltage V _ R, the Program line-Y +1 and the word line WL-Y +1 can be set to a low voltage, and the bit line BL-X +1 can be sensed to detect the resistance of the fuse element 204B (X, Y). If the fuse element is sensed or detected as having a low impedance, the fuse element should have been shorted (or successfully programmed). Conversely, if the fuse element is sensed or detected as having a high impedance, the fuse element should not yet be programmed or fail to program.

In some embodiments, the controller 202 is P-type metal oxide semiconductor field effect transistors (PMOSFETs), and the voltages applied to the word lines and bit lines in FIG. 1C are adjusted for PMOS operation. For example, to program a fuse element in these embodiments, the selected program line is set to a high voltage vp (e.g., high voltage vp is higher than 2.5V in one embodiment), the selected word line is set to a low voltage, such as: 0V, or other predetermined low voltage, to activate the associated controller 202, and the selected bit line is set to a voltage between 1/4 and 1/2 of the high voltage V _ P. At the same time, the unselected program and bit lines are set to a low voltage (e.g., 0V, or other predetermined low voltage in one embodiment), while the unselected word lines are set to a voltage between 1/4-1/2 of the high voltage V _ P. For example, to read a fuse element in these embodiments, the selected programming line is set to a voltage V _ R (e.g., V _ R may be 0.75V in one embodiment, and V _ R may range from 0.6V to 1.2V in various embodiments), the selected word line is set to 0V or other predetermined low voltage, and the selected bit line is sensed (e.g., by a sense amplifier) to detect the resistance (Impedance) of the fuse element. At the same time, the unselected program lines can be set to a low voltage (e.g., 0V, or other predetermined low voltage in one embodiment), the unselected word lines can be set to a high voltage V _ R, and the unselected bit lines can be set to 0V, a predetermined low voltage, or left Floating (Floating).

Fig. 2 is a cross-sectional view of a display device 200, particularly a pair of fuse elements 204T, 204B (collectively 204). The pair of fuse elements 204T, 204B are commonly implemented with three Metal plates (Metal plates) 250, 252, 254, and may be separated by two insulators 251, 253. In particular, fuse element 204B includes metal plates 250, 252, which may be separated by an insulator 251; and the fuse element 204T includes metal plates 252, 254, which may be separated by an insulator 253. The metal plate 252 is shared by both the fuse elements 204T and 204B. By stacking Fuse elements 204B and 204T vertically above each other, the present disclosure may improve Fuse Cell Density (Fuse Cell Density).

The pair of fuse elements 204 may be located in a Metal Interconnect Layer (Metal Interconnect Layer)206_xAmong them, for example: metal layer 4 (or M4, where x is 4), metal layer 5 (or M5, where x is 5), or other metal interconnect layers. In the following discussion, the terms "metal Interconnect Layer" and "Interconnect Layer" are used interchangeably. In some embodiments, the pair of fuse elements 204 may be located in an interconnect layer 206_xOf these, it is higher than metal layer 3 (or M3), so the following interconnect layers may be used, for example: metal layer 1 (or M1), metal layer 2 (or M2), and metal layer 3 (or M3) to implement a portion of Routing (Routing) to/from (from/to) fuse element 204. Interconnect layer 206_xIncludes one or more Dielectric layers (Dielectric Layer)207_xMetal Line 210 (e.g., Metal lines 210-1, 210-3), and a Via 208 (e.g., vias 208-2, 208-3), wherein the Via 208 is embedded in the dielectric layer 207_xAmong them. The fuse element 204 may also be embedded in the dielectric layer 207_xAnd connected to the metal wires and the pass-through member. In an illustrative embodiment, the interconnect layer 206_xIs arranged at another interconnection layer206_x-1Above. For example, if the interconnect layer 206_xIs an M4 layer (i.e., x ═ 4), then interconnect layer 206 is formed_x-1May be an M3 layer. And an interconnect layer 206_xSimilarly, interconnect layer 206_x-1Includes one or more Dielectric layers (Dielectric Layer)207_x-1A Metal Line 210 (e.g., Metal Line 210-1), and a Via 208 (e.g., Via 208-1), wherein the Via 208 is embedded in the dielectric layer 207_x-1Among them. Interconnect layer 206_xAnd an interconnect layer 206_x-1May be disposed on a Substrate (Substrate) 201. In various embodiments, the device 200 may further comprise one or more interconnect layers disposed on the interconnect layer 206_x-1And a substrate 201. In some embodiments, the device 200 may further comprise one or more interconnect layers, which are located at the interconnect layer 206_xAbove. In addition, the device 200 may further include Source/Drain contacts (Source/Drain contacts), Gate contacts (Gate contacts), Source/Drain Contact vias (Source/Drain contacts Via), and Gate contacts Via (Gate contacts Via) for providing electrical connections (electrical Connectivity) to various transistors and other devices in the substrate 201.

In some embodiments, the substrate 201 comprises a Silicon (Si) substrate, such as a Silicon Wafer (Silicon Wafer). Alternatively, the substrate 201 may include another semiconductor, such as germanium (Ge); compound semiconductors (Compound semiconductors), for example: silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or an Alloy Semiconductor (Alloy Semiconductor), such as: silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), and indium gallium phosphide (GaInP); or a combination of the above. In yet another alternative, the substrate 201 comprises a semiconductor on a Silicon-on-Insulator (SOI) substrate.

The substrate 201 includes Active devices (Active devices), such as: p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar (Bipolar) transistors, High Voltage transistors (High Voltage transistors), and High Frequency transistors (High Frequency transistors). The transistors may be Planar transistors (Planar transistors) or Multi-Gate transistors (Multi-Gate transistors), for example: FinFETs, Nanowire (Nanowire) FETs, and Nanosheet (nanoshiet) FETs. Transistors typically include Source/Drain terminals (Source/Drain Terminal) and Gate terminals (Gate Terminal). The substrate 201 may further include passive components, such as: a Resistor (Resistor), a Capacitor (Capacitor), and an Inductor (Inductor). For example, the controllers 202 (fig. 1A) may be implemented in or on the substrate 201, and in some embodiments, each controller 202 may be a planar transistor or a multi-gate transistor.

The substrate 201 may also include one or more Isolation structures (Isolation structures) for isolating various transistors, resistors, capacitors, and inductors. The Isolation structure may include Shallow Trench Isolation (Shallow Trench Isolation), Deep Trench Isolation (Deep Trench Isolation), Field Oxide (Field Oxide), Local Oxidation of Silicon (LOCOS), or other suitable structures; and may comprise silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), fluorine-doped Silicate Glass (FSG), Low-k Dielectric Material (Low-k Dielectric Material), and/or other suitable insulating materials. The substrate 201 may also include one or more dielectric layers over the various transistors, resistors, capacitors, and inductors. For example, one or more of the dielectric layers may comprise silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), silicon nitride with oxygen (O) or carbon (C) elements, doped or undoped silicate glass, silicon oxide and/or other materials.

In some embodiments, dielectric layer 207_xAnd 207_x-1May have the same or similar composition and include materials such as: tetraethylorthosilicate (TEOS) Oxide, undoped Silicate Glass (Un-Doped Silicate Glass), Doped Silicon oxides (Doped Silicon Oxide) such as Borophosphosilicate Glass (Borophosphosilicate Glass BPSG), Fluoride Doped Silica Glass (Fluoride Doped Silica Glass, FSG), aluminum Silicate (aluminum Silicate Glass, Silicon oxynitride (aluminum Silicate Glass, Silicon Oxide), Silicon Silicate Glass (Silicon Silicate Glass, Silicon Oxide), Silicon Silicate Glass (Silicon Silicate Glass, Silicon Silicate (FSG), Silicon Silicate Glass, Silicon Silicate, Silicon (Silicon Silicate, Silicon Silicate Glass, Silicon Silicate Glass, Silicon (FSG), Silicon Silicate, Silicon (FSG), Silicon Silicate, Silicon (FSG), Silicon Silicate, Silicon (FSG), Silicon (F) and Silicon (FSG), Silicon (F) and/or (F) and/or (,Phosphosilicate Glass (PSG), Boron-Doped silicon dioxide Glass (BSG), and/or other suitable dielectric materials. The dielectric layer 207 may be deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, a Flowable Chemical Vapor Deposition (FCVD) process, or other suitable Deposition technique_xAnd 207_x-1。

Each pass-through element 208 may include a Conductive Barrier Layer (Conductive Barrier Layer) and a Metal Fill Layer (Metal Fill Layer) over the Conductive Barrier Layer. The Conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or Conductive Nitride (Conductive Nitride), for example: titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and/or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. In some embodiments, the conductive barrier layer may also be omitted in the pass-through member 208.

Each metal line 210 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, electroplating, or other suitable processes. Similar to the feedthrough member 208, in some embodiments, the metal line 210 may further include a conductive barrier layer, which may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as: titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof. The Metal lines 210 and the through devices 208 may be formed by a Damascene Process, a Dual-Damascene Process, a Metal Patterning Process, or other suitable processes.

Still referring to FIG. 2, in one embodiment, each metal plate250. 252, 254 comprise a titanium nitride (TiN) based metal or metal compound. Alternatively, each of the metal plates 250, 252, 254 comprises a single metal or a stack of metals, wherein the single or multiple metals are selected from Ti, TiN, Ni, Mo, Pt, Co, Ru, W, TaN, Cu, or combinations thereof. Each of the metal plates 250, 252, 254 may be formed by CVD, PVD, ALD, plating, or other suitable process. In some embodiments, bottom metal plate 250 and top metal plate 254 each have less than 200 angstromsFor example: in the range of about 30 angstroms to about 200 angstroms. In some embodiments, the thickness of intermediate metal plate 252 is approximately in the range of 30 to 200 angstroms. In the present embodiment, the top metal plate 254 is smaller than both the middle metal plate 252 and the bottom metal plate 250. The portion of the middle plate 252 and the bottom plate 250 extending beyond the top plate 254 may provide a Landing Area for the pass-through member 208-2.

Each of the insulators 251, 253 includes a dielectric material or a stack of multiple dielectric materials. In some embodiments, each of the insulators 251, 253 includes a material selected from: SiO 2₂、SiOC、SiON、SiOCN、Si₃N₄Carbon doped SiO₂Nitrogen doped SiO₂Carbon and nitrogen doped SiO₂、HfO₂、Ta₂O₅、TiO₂、ZrO₂、Al₂O₃、Y₂O₃Or a combination thereof. Each of the insulators 251, 253 can be deposited using CVD, ALD, or other suitable methods. In some embodiments, the thickness of each of insulators 251, 253 is in the range of approximately 5 to 50 angstroms. The thickness is designed in consideration of a voltage sufficient to cause the insulators 251 and 253 to collapse when the fuse element 204 is programmed. If insulators 251 and 253 are too thick (e.g., thicker than desired)) Then canThe voltage required to collapse the insulators 251, 253 may be too high for the device 200. If the insulator 251 or 253 is too thin (e.g., less than thickness)) The operation of fuse element 204 may become unstable or unreliable. Various features of the fuse element 204 (including the metal plates 250, 252, 254, and insulators 251, 253) may be formed by deposition methods as described above, for example: dry Etching (Dry Etching), Reactive Ion Etching (Reactive Ion Etching), or other suitable Etching processes.

FIG. 2 further illustrates physical and electrical connections (e.g., the controller 202 and programming lines) between the fuse element 204 and other elements of the fuse array according to one embodiment. In this embodiment, the bottom metal plate 250 is directly connected to the interconnect layer 206_x-1Metal line 210-1 in (a). The metal line 210-1 is disposed on a pass device 208-1, wherein the pass device 208-1 is electrically connected to a source terminal of a controller 202, such as: a controller 202(X, Y) or 202(X, Y +1), implemented in or on the substrate 201. Although not shown in FIG. 2, the pass-through device 208-1 and the source terminal of the controller 202 are connected via a Metal Feature, such as: metal lines, through-members, and contact points. The intermediate metal plate 252 is directly connected to the interconnect layer 206_x208-2. The pass-through member 208-2 is disposed under the metal line 210-2 and connected to the interconnect layer 206_xMetal line 210-2 of (1), wherein the interconnect layer 206_xIs electrically connected to the program line. Although not shown in FIG. 2, metal line 210-2 and the program line are connected via metal components, such as: a metal wire and a pass-through member. The top metal plate 254 is directly connected to the interconnect layer 206_x208-3. The pass-through member 208-3 is disposed under the metal line 210-3 and connected to the interconnect layer 206_xMetal line 210-3 of (1), wherein the interconnect layer 206_xIs electrically connected to the source terminal of another controller 202, such as: a controller 202(X +1, Y) or 202(X +1, Y +1), implemented in or on the substrate 201. Although not shown in FIG. 2, the metal line 210-3 and the source terminal of controller 202 are connected via metal components, such as: metal lines, through-members, and contact points. Likewise, by vertically stacking fuse elements 204T and 204B, the present disclosure may provide a high density of fuse elements, but each fuse element 204T and 204B may be programmed separately and separately, thereby providing great design flexibility.

As discussed with reference to fig. 1A-1C, each fuse element 204T and 204B can be programmed (or shorted) by applying a particular voltage to the associated program line, word line, or bit line for a particular period of time. When a fuse element is successfully programmed, the insulators 251 or 253 will collapse due to the voltage applied to the metal plates sandwiching (Sandwich) the respective insulators. For example, when fuse element 204B is successfully programmed, insulator 251 collapses due to the voltage applied to metal plates 252 and 250 and becomes a low resistance path for current to pass through. Similarly, when fuse element 204T is successfully programmed, insulator 253 collapses due to the voltage applied to metal plates 252 and 254 and becomes a low resistance path for current to pass through.

The Fuse element 204, the pass through elements 208-1, 208-2, 208-3, and the metal lines 210-1, 210-2, 210-3 may be located within a Fuse Region (Fuse Region) of the device 200. FIG. 2 also shows metal lines and vias in a Non-fuse Region (Non-fuse Region) including a via 208-21 in interconnect layer 206_x-1A metal line 210-21 therein, and an interconnection layer 206 therein_xA through element 208-22 and a wire 210-22. The pass-through members 208-22 are disposed over the metal lines 210-21. The pass-through members 208-22 are taller (or longer) than the pass-through members 208-2 and 208-3 in the fuse region, which is directly below the metal plates 252, 254, metal lines 210-22, 210-2, 210-3, but they may have the same thickness (vertical dimension).

FIG. 3 further illustrates physical and electrical connections (e.g., the controller 202 and programming lines) between the fuse element 204 and other elements of the fuse array according to one embodiment. Many features of the embodiment of FIG. 3 are the same as the embodiment of FIG. 2, so bothThe figures may have similar element designations. The foregoing common features include: interconnect layer 206_xInterconnect layer 206_x-1Dielectric layer 207_xAnd 207_x-1A through-member 208, a metal wire 210, metal plates 250, 252, 254, and insulators 251, 253. For the sake of simplicity, these features will not be described repeatedly. In addition, the substrate 201 is not shown in FIG. 3 for simplicity.

As shown in fig. 3, the bottom metal plate 250 is not directly connected to the interconnect layer 206_x-1Of the metal wire or through-member. In contrast, bottom metal plate 250 is directly connected to interconnect layer 206_xThrough the element 208-7 and then via the interconnect layer 206_xA metal line 210-6 and a through-element 208-6, interconnect layer 206_x-1A metal line 210-4 and a pass-through device 208-4, and finally to a source terminal of a controller 202, for example: a controller 202(X, Y) or 202(X, Y +1), implemented in or on the substrate 201. The connection between the top metal plate 254 and the source terminal of the second controller 202 is similar. In other words, the top metal plate 254 is directly connected to the interconnect layer 206_xThrough the element 208-9 and then via the interconnect layer 206_xA metal line 210-8 and a through-element 208-10, interconnect layer 206_x-1A metal line 210-5 and a pass-through device 208-5, and finally to a source terminal of a controller 202, for example: a controller 202(X +1, Y) or 202(X +1, Y +1), implemented in or on the substrate 201. The intermediate metal plate 252 is directly connected to the interconnect layer 206_xThrough the element 208-8 and then via the interconnect layer 206_xOne metal line 210-7 in the set, and finally to the program line. In the embodiment shown in FIG. 3, all direct connections to the metal plates 250, 252, 254 are located at the same interconnect layer 206_xIn (1). On the other hand, the through-members 208-7, 208-8, 208-9 that fall directly on the metal plates 250, 252, 254 may have a length that is less than that of the interconnect layer 206 that does not fall directly on the metal plates 250, 252, 254_xThe other pass-through members on the metal plates 250, 252, 254 in (a) are made shorter. Additionally, the top metal plate 254 is smaller than the middle metal plate 252, and the middle metal plate 252 is smaller than the bottom metal plate 250. Bottom metal plate 25A portion of 0 extending beyond intermediate metal plate 252 may provide a landing zone for pass-through member 208-7. A portion of the middle metal plate 252 extending beyond the top metal plate 254 may provide a landing zone for the pass-through member 208-8.

Fig. 4 is a wiring (Routing) diagram showing certain signal lines of an example fuse array in the device 200. In this example, the fuse array is a 4x4 array, i.e., there are four controllers 202 on each row and four controllers 202 on each column. Controller 202 is shown as a "Cell" in the figure. A Pair (Pair) of fuse elements 204 is shared by two adjacent cells. Each pair of fuse elements 204 includes a fuse element 204T Vertically stacked (Vertically Stack) on another fuse element 204B, as shown in fig. 2 and 3. There are four program lines in this example fuse array: program line-1, Program line-2, Program line-3, and Program line-4. Each programming line includes a signal line 260 routed through the same interconnect layer in which the fuse element 204 is located (e.g., interconnect layer 206 of FIGS. 2 and 3)_x). Therefore, the signal line 260 may also be referred to as an "In-cell" programming line. For example, the signal line 260 may be the metal line 210-2 of FIG. 2 or the metal line 210-7 of FIG. 3. Each programming line also includes a signal line 262 that may be routed within an interconnect layer (e.g., interconnect layer 206)_x-1Or a lower interconnect layer) below the interconnect layer in which the fuse element 204 is located (e.g.: interconnect layer 206_x). The signal line 262 may be ultimately connected to a Selector (Selector) or a Driver Circuit (Driver Circuit) in the device 200. The signal lines 260, 262 may be interconnected via Metal bonding pads or pass-through members, such as the pass-through member 208. The programming line 260 within the cell may be routed horizontally (along the "x" direction) in this example. In one embodiment, the programming lines 260 within the cell may run within an interconnect level (i.e., the M4 level or higher), which is located above a third interconnect level of the device 200. There are four word lines WL1, WL2, WL3, WL4 in this example fuse array, which are routed horizontally (along the "x" direction). In one embodiment, the word lines may also be distributedAmong the second interconnect layer above the transistors of device 200 (i.e., the M2 interconnect layer). These word lines may ultimately be connected to selector or driver circuits in the device 200. There are four bit lines BL1, BL2, BL3, BL4 in this example fuse array, which are routed vertically (along the "y" direction). In one embodiment, these bit lines may also run in the first interconnect layer (i.e., the M1 interconnect layer) above the transistors of device 200. These bit lines can be connected to Ground (Ground) or Sense amplifiers (Sense amplifiers) that operate according to a fuse array.

FIG. 5 is a Layout (Layout) diagram illustrating a portion of the fuse array of FIG. 1A according to one embodiment. In particular, fig. 5 is a layout diagram showing various metal components for the fuse element 204(X, Y). The lower controllers 202(X, Y) and 202(X, Y +1) share a boundary ("cell boundary") as indicated by the Dashed Box (dash Box). Fig. 5 shows from a top view that the metal plates 250 and 252 have the same size and shape and completely overlap each other (i.e., they are Coextensive), while the top metal plate 254 is smaller than the metal plates 250 and 252 and is surrounded by the metal plates 250 and 252. There is some Clearance area (Clearance) from the edge of the top metal plate 254 to the edges of the metal plates 252 and 250. The bit lines BL-X and BL-X +1 are routed vertically (in the "y" direction). The (intracellular) program lines and word lines WL are routed horizontally (in the "x" direction). In one embodiment, bit lines BL-X and BL-X +1 are routed in the M1 interconnect level, word lines WL are routed in the M2 interconnect level (i.e., the interconnect level directly above the M1 interconnect level), and (intra-cell) program lines 210-2 are routed in the M4 interconnect level or higher (i.e., the M4 interconnect level, the M5 interconnect level, etc.).

Fig. 6 and 7 are sectional views showing the device 200 along the Cross-section cut-1 line and the Cross-section cut-2 line in fig. 5, respectively. Fig. 6 has the same components as those in the fuse region of fig. 2, and the description thereof is omitted for simplicity. Some of the components of fig. 7, including: fuse element 204, metal lines 210-1 and 210-3, and pass-through element 208-3 are the same as those shown in the fuse region of FIG. 2. FIG. 7 is a further illustration ofThe open metal line 210-3 is connected to the interconnect layer 206_xAnd the pass-through member 208-11 is disposed in the interconnect layer 206_x-1Over metal line 210-9.

FIG. 8 is a layout diagram illustrating a portion of the fuse array of FIG. 1A in accordance with one embodiment. In particular, fig. 8 is a layout diagram showing various metal components for the fuse element 204(X, Y). The lower controllers 202(X, Y) and 202(X +1, Y) are shown in dashed boxes that they share a boundary ("cell boundary"). Fig. 8 shows, in a top view, that the bottom metal plate 250 is larger than the middle metal plate 252, and that the middle metal plate 252 is larger than the top metal plate 254. The middle metal plate 252 is surrounded on three sides by the top metal plate 250 and shares one side with the metal plate 250 (see also fig. 9, which shows that one side of the metal plate 252 is the side that is vertically aligned with the metal plate 250). The top metal plate 254 is completely surrounded by the middle metal plate 252. There is some Clearance area (Clearance) from the edge of the top metal plate 254 to the edges of the metal plates 252 and 250. The bit lines BL-X and BL-X +1 are routed vertically (in the "y" direction). The (intracellular) program lines and word lines WL are routed horizontally (in the "x" direction). In one embodiment, bit lines BL-X and BL-X +1 are routed in the M1 interconnect level, word lines WL are routed in the M2 interconnect level (i.e., the interconnect level directly above the M1 interconnect level), and (intra-cell) program lines 210-7 are routed in the M4 interconnect level or higher (i.e., the M4 interconnect level, the M5 interconnect level, etc.).

Fig. 9, 10, 11 are sectional views showing the device 200 along the "Cross-section cut-3 (Cross-section cut-1)" line, "Cross-section cut-4 (Cross-section cut-4)" line, and "Cross-section cut-5 (Cross-section cut-5)" line in fig. 8, respectively. Fig. 9, 10, 11 and 3 have the same components in the fuse region, and the description thereof is omitted for simplicity.

FIG. 12 is a layout diagram illustrating a portion of the fuse array of FIG. 1A according to another embodiment. In particular, fig. 12 is a layout diagram showing various metal components for the fuse element 204(X, Y). The lower controllers 202(X, Y) and 202(X +1, Y) are shown in dashed boxes that they share a boundary ("cell boundary"). Fig. 12 shows, in a top view, that the bottom metal plate 250 is larger than the middle metal plate 252, and that the middle metal plate 252 is larger than the top metal plate 254. The middle metal plate 252 is surrounded on three sides by the top metal plate 250 and shares one side with the metal plate 250 (see also fig. 13, which shows that one side of the metal plate 252 is the side that is vertically aligned with the metal plate 250). The top metal plate 254 is completely surrounded by the middle metal plate 252. There is some Clearance area (Clearance) from the edge of the top metal plate 254 to the edges of the metal plates 252 and 250. The bit lines BL-X and BL-X +1 are routed vertically (in the "y" direction). The (intracellular) program lines and word lines WL are routed horizontally (in the "x" direction). In one embodiment, bit lines BL-X and BL-X +1 are routed in the M1 interconnect level, word lines WL are routed in the M2 interconnect level (i.e., the interconnect level directly above the M1 interconnect level), and (intra-cell) program lines 210-7 are routed in the M4 interconnect level or higher (i.e., the M4 interconnect level, the M5 interconnect level, etc.).

Fig. 13, 14, 15 are sectional views showing the device 200 along the "Cross-section cut-6 (Cross-section cut-6)" line, "Cross-section cut-7 (Cross-section cut-7)" line, and "Cross-section cut-8 (Cross-section cut-8)" line in fig. 12, respectively. Fig. 13, 14, 15 and 3 have the same components in the fuse region, and the description thereof is omitted for simplicity.

FIG. 16A illustrates a fuse array (a 2x1 array) according to device 200 in another embodiment. This embodiment is the same as that described in the embodiment of fig. 1A, but differs therefrom. In the embodiment shown in fig. 1A, a fuse cell includes a controller 202 and a fuse element 204T or 204B, but two adjacent fuse cells 202 share a pair of fuse elements 204T and 204B. In the embodiment shown in FIG. 16A, a fuse cell includes a controller 202 and a pair of fuse elements 204T and 204B, where the fuse elements 204T and 204B are connected in parallel between a program line and a source line of the controller 202. Fig. 16A shows two such fuse cells. In practice, a pair of Fuse elements 204T and 204B can be programmed and sensed (or read) simultaneously as a Fuse Unit. If at least one of them is successfully programmed, a short circuit is established between the program line and the source terminal of the controller 202. This gives the fuse a very high reliability of operation. In the example of fig. 16B, both fuse elements 204T and 204B are successfully programmed and may result from a low resistance path (i.e., resistor) connected in parallel between the program line and the source terminal of controller 202. This is the general case. In the example of FIG. 16C, fuse element 204T was successfully programmed and provided a low resistance path, but fuse element 204B failed to be programmed and remained open. Such a situation will not typically occur. However, even in this case, the program line may be connected to the source terminal of the controller 202 through a low resistance path (i.e., in this case, through the middle metal plate 252 and the top metal plate 254), and the fuse cell (or fuse cell) operation is also considered successful.

Fig. 17 illustrates a fuse array (a 2x2 array) of device 200, wherein each fuse cell includes a controller 202 and a pair of fuse elements 204T and 204B, wherein fuse elements 204T and 204B are connected in parallel between a program line and a source terminal of controller 202. Fuse cells in the same column may share a Common programming Line (Common Program Line). Fuse cells in the same column may share a Common Bit Line (Common Bit Line). Otherwise, it is the same as fig. 2, but omitted in fig. 16A for simplicity.

FIG. 18 is a cross-sectional view showing a portion of the fuse cell of FIG. 16A according to an embodiment. Many features of the embodiment of fig. 18 are the same as the embodiment of fig. 2, so that like elements are labeled in both figures. The foregoing common features include: substrate 201, interconnect layer 206_xInterconnect layer 206_x-1Dielectric layer 207_xAnd 207_x-1A through-member 208, a metal wire 210, metal plates 250, 252, 254, and insulators 251, 253. For the sake of simplicity, these features will not be described repeatedly. In the embodiment of FIG. 18, the apparatus 200 further includes an interconnect layer 206_xThrough element 208-12. The pass-through member 208-12 physically and electrically connects the metal line 210-3 to the metal line 210-1, thereby shorting the top metal plate 254 and the bottom metal plate 250 together.

FIG. 19 is a layout diagram illustrating a portion of the fuse array of FIG. 17 in accordance with one embodiment. In particular, fig. 19 is a layout diagram showing various metal components for the fuse element 204(X, Y). The lower controller 202(X, Y) represents a boundary ("cell boundary") in a dashed box. Fig. 19 shows, in a top view, that the bottom metal plate 250 is larger than the middle metal plate 252, and that the middle metal plate 252 is larger than the top metal plate 254. There is some clearance from the edge of the top metal plate 254 to the edge of the middle metal plate 252. In addition, there is some clearance from the edge of the middle metal plate 252 to the edge of the bottom metal plate 250. The bit lines BL-X are routed vertically (in the "y" direction). The (intracellular) program lines and word lines WL are routed horizontally (in the "x" direction). In one embodiment, bit lines BL-X are routed in the M1 interconnect level, word lines WL are routed in the M2 interconnect level (i.e., the interconnect level directly above the M1 interconnect level), and (intra-cell) program lines 210-2 are routed in the M4 interconnect level or higher (i.e., the M4 interconnect level, the M5 interconnect level, etc.).

Fig. 20 and 21 are sectional views showing the device 200 along the Cross-section cut-9 line and the Cross-section cut-10 line in fig. 19, respectively. Fig. 20, 21 and 18 have the same components in the fuse region, and the description thereof is omitted for simplicity.

Fig. 22 is a wiring diagram showing certain signal lines of an exemplary fuse array in device 200, in which the fuse cells include a controller 202 and a pair of fuse elements 204 (i.e., 204T and 204B), as described in fig. 16A. In this example, the fuse array is a 4x4 array, i.e., there are four controllers 202 on each row and four controllers 202 on each column. Controller 202 is shown as a "cell" in the figure. A pair of fuse elements 204 is connected in parallel with a cell. Each pair of fuse elements 204 includes a fuse element 204T vertically stacked above another fuse element 204B, as shown in FIG. 18. FIG. 22 is otherwise identical to FIG. 4, for example: the layout of the program lines (including signal lines 262, 260), word lines, and bit lines.

Fig. 23 shows a layout of the controller 202 according to an embodiment. The controller 202 includes an active region 280 longitudinally oriented in the "y" direction and a Gate Electrode 282 longitudinally oriented in the "x" direction perpendicular to the "y" direction. The gate electrode 282 may be joined (Engage) to the active region 282 to form a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In some embodiments, the active region 280 may be a Block (Block) of semiconductor material or a plurality of fins (Fin) of semiconductor material. In one embodiment, the Gate electrode 282 may be a High-k Metal Gate (High-k Metal Gate). The controller 202 further includes a Source Contact disposed in a Source Region (Source Region) of the active Region 280 and a Drain Contact disposed in a Drain Region (Drain Region) of the active Region 280. The controller 202 also includes a pass-through element (via 1) that connects the source contact to the top metal plate 254 or the bottom metal plate 250 of a fuse element. The controller 202 also includes another pass through device (via 1), which connects the drain contact to the bit line. The device 200 also includes Dummy gates (Dummy gates) or Dielectric gates (Dielectric gates) at the boundaries of the controller 202 for isolation purposes.

FIG. 24 is a cross-sectional view showing a portion of device 200 in accordance with an embodiment. As shown, the substrate 201 includes a Well Region (Well Region) and an active Region (e.g., doped with an n-type or p-type dopant). The active regions are separated from each other by dielectric gates and/or other isolation features. The source region and the drain region of the controller 202 are both disposed in the active region. A gate electrode (or gate) is disposed over the active region to form a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Contacts are provided on the source and drain terminals of the mosfet. Furthermore, the gate electrode may be connected to a metal line in the M1 interconnect layer via the pass-through element VG, while the source and drain contacts may be connected to a metal line in the M1 interconnect layer via the pass-through element V1. Even though not shown in fig. 24, the device 200 also includes a plurality of interconnect layers above the M1 interconnect layer, such as: m2 layer, M3 layer, M4 layer, and M5 layer, and so on. For example, according to one embodiment, one of the gate electrodes may be electrically connected to a word line disposed in the M2 layer, and one of the source contacts may be electrically connected to a top or bottom metal plate of a fuse element 204 disposed in the M4 layer.

Although not by way of limitation, one or more embodiments of the present disclosure provide a number of benefits to integrated circuits and their formation. For example, embodiments of the present disclosure provide a novel antifuse (or fuse) implemented at a metal layer and over a transistor. The new fuse structure provides two fuse cells with vertically stacked fuse elements to reduce the cell size, while both ends of each fuse element are metal plates. The new antifuse structure provides very reliable operation both when programmed and when read. With this new fuse structure, the transistor and fuse trimming can be decoupled, providing more freedom for adjusting the programming voltage of the fuse. Embodiments of the present disclosure may be integrated into existing processes.

In one aspect, the present disclosure relates to a semiconductor structure comprising: a first transistor and a second transistor, wherein each of the first transistor and the second transistor has a source terminal, a drain terminal, and a gate terminal; a programming line; a first metal plate disposed over the first transistor and the second transistor; a first insulator disposed on the first metal plate; a second metal plate disposed on the first insulator; a second insulator disposed on the second metal plate; and a third metal plate disposed over the second insulator, wherein the first metal plate, the first insulator, and the second metal plate form a first antifuse element, wherein the second metal plate, the second insulator, and the third metal plate form a second antifuse element, wherein the source terminal of the first transistor is electrically connected to the first metal plate, the source terminal of the second transistor is electrically connected to the third metal plate, and the program line is electrically connected to the second metal plate.

In some embodiments, the semiconductor structure further comprises: a first bit line electrically connected to the drain terminal of the first transistor; and a second bit line electrically connected to the drain terminal of the second transistor. In some embodiments, the semiconductor structure further comprises: a word line electrically connected to the gate terminals of the first and second transistors.

In some embodiments, each of the first metal plate, the second metal plate, and the third metal plate comprises titanium, titanium nitride, nickel, molybdenum, platinum, cobalt, ruthenium, tungsten, tantalum nitride, copper, or combinations thereof. In some embodiments, each of the first insulator and the second insulator comprises SiO₂、SiOC、SiON、SiOCN、Si₃N₄Carbon doped SiO₂Nitrogen doped SiO₂Carbon and nitrogen doped SiO₂A dielectric metal oxide, or a combination thereof. In some embodiments, each of the first insulator and the second insulator has a thickness between about 5 angstroms and about 50 angstroms.

In one embodiment, the first metal plate is disposed on and in physical contact with a first metal line electrically connected to the source terminal of the first transistor, the third metal plate is disposed under a second metal line electrically connected to the source terminal of the second transistor via a through element, and the first metal line and the second metal line are disposed in two adjacent interconnect layers. In a further embodiment, the second metal plate is disposed under a third metal line and connected to the third metal line via another through via, and the second metal line and the third metal line are disposed in the same interconnect layer.

In another embodiment, the first metal plate is disposed on a first metal line electrically connected to the source terminal of the first transistor, the first metal plate is disposed under a second metal line and connected to the second metal line through a first through device, the second metal line is connected to the first metal line through a second through device, and the first metal line and the second metal line are disposed in two adjacent interconnect layers. In a further embodiment, the third metal plate is disposed on a third metal line, the third metal line is electrically connected to the source terminal of the second transistor, the third metal plate is disposed under a fourth metal line and connected to the fourth metal line through a third through via, the fourth metal line is connected to the third metal line through a fourth through via, and the third metal line and the fourth metal line are disposed in two adjacent interconnect layers. In a further embodiment, the second metal plate is disposed under a fifth metal line and connected to the fifth metal line through a fifth through via, wherein the second metal line, the fourth metal line, and the fifth metal line are disposed in a same interconnect layer, and wherein the first metal line and the third metal line are disposed in a same interconnect layer.

In some embodiments, the semiconductor structure further comprises: a plurality of stacked metal layers disposed above the first transistor and the second transistor, wherein the first metal plate, the first insulator, the second metal plate, the second insulator, and the third metal plate are disposed between a first metal layer and a second metal layer and directly above the first one of the metal layers, and at least two of the metal layers are disposed below the first metal layer.

In another example aspect, the present disclosure is directed to a semiconductor structure comprising: a first transistor and a second transistor, wherein each of the first transistor and the second transistor has a source terminal, a drain terminal, and a gate terminal; a word line conductor electrically connected to the gate terminals of the first and second transistors; a programming line conductor; and a vertically stacked pair of anti-fuse elements including a first metal plate, a second metal plate, and a third metal plate, wherein the first metal plate, the second metal plate, and the third metal plate are stacked on the first transistor and the second transistor and separated from each other by a plurality of insulators, the source terminal of the first transistor is electrically connected to the first metal plate, the source terminal of the second transistor is electrically connected to the third metal plate, and the programming line conductor is electrically connected to the second metal plate.

In some embodiments, the semiconductor structure further comprises: a first bit line electrically connected to the drain terminal of the first transistor; and a second bit line electrically connected to the drain terminal of the second transistor. In some embodiments, each of the first metal plate, the second metal plate, and the third metal plate comprises titanium, titanium nitride, nickel, molybdenum, platinum, cobalt, ruthenium, tungsten, tantalum nitride, copper, or combinations thereof. In some embodiments, the insulator comprises SiO₂、SiOC、SiON、SiOCN、Si₃N₄Carbon doped SiO₂Nitrogen doped SiO₂Carbon and nitrogen doped SiO₂、HfO₂、Ta₂O₅、TiO₂、ZrO₂、Al₂O₃、Y₂O₃Or a combination thereof.

In some embodiments, the semiconductor structure further comprises: and a plurality of metal layers vertically stacked and disposed above the first transistor and the second transistor, wherein the anti-fuse element is disposed between two adjacent metal layers.

In yet another example aspect, the present disclosure is directed to a semiconductor structure comprising: a first transistor having a source terminal, a drain terminal, and a gate terminal; a word line conductor electrically connected to the gate terminal of the first transistor; a bit line conductor electrically connected to the drain terminal of the first transistor; a programming line conductor; and a vertically stacked pair of anti-fuse elements comprising three metal plates vertically stacked, wherein the metal plates are separated from each other by a plurality of insulators, the source terminal of the first transistor is electrically connected to an uppermost one and a lowermost one of the metal plates, and the program line conductor is electrically connected to a middle one of the metal plates.

In the semiconductor structure of an embodiment, each of the metal plates includes titanium, titanium nitride, nickel, molybdenum, platinum, cobalt, ruthenium, tungsten, tantalum nitride, copper, or a combination thereof. In the semiconductor structure of another embodiment, the insulators are allComprising SiO₂、SiOC、SiON、SiOCN、Si₃N₄Carbon doped SiO₂Nitrogen doped SiO₂Carbon and nitrogen doped SiO₂A dielectric metal oxide, or a combination thereof.

The foregoing outlines features of many embodiments so that those skilled in the art may better understand the present disclosure in various aspects. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Various changes, substitutions, or alterations to the disclosure may be made without departing from the spirit and scope of the disclosure.