阅读说明：本技术 一种单片集成的功率模块的封装结构及其制备方法 (Packaging structure of monolithic integrated power module and preparation method thereof ) 是由 王振宇 王志腾 钱文冰 于 2021-09-10 设计创作，主要内容包括：本发明实施例公开了一种单片集成的功率模块封装结构及其制备方法,所述封装结构包括单片集成设置的多管功率芯片和散热底盘,所述多管功率芯片和散热底盘之间通过一层粘合剂连接,所述多管功率芯片上集成有多个按照预设绝缘间隔设置的晶体管。多管功率芯片含有多个不同种类的晶体管,晶体管之间有一定距离以确保绝缘,配合引线键合来构成电路,可以独立满足一个电力电子应用场景；散热底盘的一面刻蚀有凹槽,芯片贴合后封盖住凹槽的顶部,形成微管道,流通散热工质以带走热。主要为了增强封装散热性能、减小封装体积以及降低封装过程中的芯片对准精度要求和贴片时的界面连接技术要求。(The embodiment of the invention discloses a monolithic integrated power module packaging structure and a preparation method thereof, wherein the packaging structure comprises a multi-tube power chip and a heat dissipation chassis which are monolithically integrated, the multi-tube power chip and the heat dissipation chassis are connected through a layer of adhesive, and a plurality of transistors which are arranged at intervals according to preset insulation are integrated on the multi-tube power chip. The multi-tube power chip comprises a plurality of transistors of different types, a certain distance is reserved between the transistors to ensure insulation, and a circuit is formed by matching with lead bonding, so that a power electronic application scene can be independently met; one side of the heat dissipation chassis is etched with a groove, the chip is attached and then covers the top of the groove to form a micro-pipeline, and a heat dissipation working medium flows to take away heat. The packaging structure mainly aims to enhance the packaging heat dissipation performance, reduce the packaging volume and reduce the chip alignment precision requirement in the packaging process and the interface connection technical requirement in the process of mounting.)

1. The packaging structure of the monolithic integrated power module is characterized by comprising a multi-tube power chip and a heat dissipation chassis, wherein the multi-tube power chip and the heat dissipation chassis are arranged in a monolithic integration mode, the multi-tube power chip is used for providing a logic operation function after being electrified, the heat dissipation chassis is used for heat dissipation of the chip during working, the multi-tube power chip and the heat dissipation chassis are connected through a layer of adhesive, and a plurality of transistors are integrated on the multi-tube power chip and are arranged at intervals according to preset insulation.

2. The package structure of a monolithically integrated power module of claim 1 wherein said adhesive comprises a conductor adhesive and an insulating adhesive, said conductor adhesive being in a patterned distribution design and electrically connected to said plurality of transistors, said insulating adhesive filling said pattern of voids disposed in said conductor adhesive.

3. The package structure of the monolithically integrated power module as claimed in claim 1, wherein a heat dissipation groove is etched on the heat dissipation chassis, the adhesive is covered above the heat dissipation groove, an insulating heat dissipation working medium flows through the heat dissipation groove, the heat dissipation groove is communicated with a liquid inlet and outlet of the heat dissipation working medium, and the liquid inlet and outlet is vertically arranged on the heat dissipation chassis in a penetrating manner.

4. The package structure of a monolithically integrated power module as claimed in claim 2, wherein the plurality of transistors on the multi-tube power chip are respectively provided with a port, the different transistors are electrically connected by a wire connecting port, and each transistor is electrically connected to the lower conductor adhesive by a wire connecting port.

5. The package structure of a monolithically integrated power module of claim 1 further comprising a protective enclosure disposed over the multi-tube power chip and the heat sink chassis.

6. Method for preparing a package structure of a monolithically integrated power module according to any of claims 1 to 5, characterized in that the method comprises:

processing and etching a heat dissipation groove and a liquid inlet and outlet on the upper surface of the silicon carbide substrate to manufacture a heat dissipation chassis;

then aligning the absolute position of the chip, bonding the single integrated multi-tube power chip with the heat dissipation chassis through an adhesive, and sealing the heat dissipation groove on the heat dissipation chassis;

finally, the terminals of each transistor are electrically connected to the underlying conductor adhesive using leads.

7. The method of claim 6, further comprising:

when the wafer layout design is carried out, the combination of the multiple transistors is taken as a whole instead of an independent transistor, the types and the positions of the transistors are planned in the combination, enough insulation distance is reserved, and when the wafer is cut, the single transistor is not cut, but the combination of the multiple transistors which are designed in advance is integrally cut, so that the multi-tube power chip is formed.

Technical Field

The embodiment of the invention relates to the technical field of semiconductor power module packaging, in particular to a packaging structure of a single-chip integrated power module and a preparation method thereof.

Background

A power electronic device, also called a power device or a power module, is a high-power electronic device (usually, current is tens to thousands of amperes, and voltage is more than hundreds of volts) mainly used for an electric energy conversion and control circuit of power equipment, and its internal chip generates heat in a huge amount during operation. The traditional power chip only comprises one transistor, most of the packaging of the power module is that a copper-clad ceramic substrate is placed on a heat dissipation chassis and attached, a plurality of single-tube power chips are placed on the substrate and attached, and metal leads are adopted to connect ports of the plurality of chips, so that the packaging method is a standard packaging method called a multi-chip interconnection module (MCM). Furthermore, after a groove is etched on the surface of one substrate, the other substrate is attached and covered to obtain the heat dissipation chassis with the micro-pipeline, so that the heat dissipation capacity is enhanced. However, the packaging structure has at least three layers, and the packaging volume is large; in the aspect of heat dissipation, although the chassis is provided with the micro-pipeline in the improved structure and circulates a heat dissipation working medium to take away heat, the path from the chip to the heat dissipation plate is long, the number of the passing bonding layers is large, so that the thermal resistance is still too high, the heat capacity is too low, and the heat dissipation performance of the package in steady state and transient state is limited.

In addition, in the packaging process of the power module, the position of the chip needs to be accurately aligned, the size of the chip is small (the length and the width are in millimeter order, and the thickness is in 10 micrometer order), and the requirement on the accuracy of the position alignment is high. In addition, the chip is thin and soft, and if the chip and the substrate are attached by adopting press bonding or pressure-assisted sintering, the chip is easily damaged by pressure if the chip is not stable and accurate enough when placed.

Disclosure of Invention

Therefore, the embodiment of the invention provides a monolithic integrated power module packaging structure and a preparation method thereof, and aims to solve the problems of large packaging volume, poor heat dissipation, high requirement on chip alignment precision, easy damage of a bonded chip and the like in the prior art.

In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:

according to a first aspect of the embodiments of the present invention, a monolithic integrated power module package structure is provided, where the package structure includes a multi-tube power chip and a heat dissipation chassis, the multi-tube power chip is configured to provide a logic operation function after being powered on, the heat dissipation chassis is configured to dissipate heat during chip operation, the multi-tube power chip and the heat dissipation chassis are connected by a layer of adhesive, and a plurality of transistors are integrated on the multi-tube power chip and are arranged at preset insulation intervals.

Further, the adhesive includes a conductor adhesive designed in a pattern distribution and electrically connected to the plurality of transistors and an insulating adhesive filled in the pattern distribution voids provided in the conductor adhesive.

Furthermore, a heat dissipation groove is formed in the heat dissipation chassis in an etching mode, the adhesive is covered above the heat dissipation groove, insulating heat dissipation working media flow through the heat dissipation groove, the heat dissipation groove is communicated with a liquid inlet and outlet of the heat dissipation working media, and the liquid inlet and outlet are arranged on the heat dissipation chassis in a vertically penetrating mode.

Furthermore, ports are respectively arranged on a plurality of transistors on the multi-tube power chip, different transistors are electrically connected through a wire connecting port, and each transistor is electrically connected with the lower conductor adhesive through the wire connecting port.

Further, the package structure further includes a protective enclosure disposed over the multi-tube power chip and the heat dissipation chassis.

According to a first aspect of the embodiments of the present invention, a method for manufacturing a package structure of a monolithically integrated power module is provided, the method including:

processing and etching a heat dissipation groove and a liquid inlet and outlet on the upper surface of the silicon carbide substrate to manufacture a heat dissipation chassis;

then aligning the absolute position of the chip, bonding the single integrated multi-tube power chip with the heat dissipation chassis through an adhesive, and sealing the heat dissipation groove on the heat dissipation chassis;

finally, the terminals of each transistor are electrically connected to the underlying conductor adhesive using leads.

Further, the method further comprises:

when the wafer layout design is carried out, the combination of the multiple transistors is taken as a whole instead of an independent transistor, the types and the positions of the transistors are planned in the combination, enough insulation distance is reserved, and when the wafer is cut, the single transistor is not cut, but the combination of the multiple transistors which are designed in advance is integrally cut, so that the multi-tube power chip is formed.

The embodiment of the invention has the following advantages:

1. the thermal resistance is greatly reduced. In the traditional structure, at least two layers of adhesives and one layer of ceramic substrate are separated from a heat dissipation working medium from a chip to a heat dissipation chassis.

2. The volume is small. The traditional micro-assembly method has at least three layers of modules above and below the modules, so that the size of the modules is overlarge. The packaging structure of the invention has only two layers above and below, and the volume of the module can be made smaller.

3. The alignment accuracy requirement is low. In the conventional method, one power chip only comprises one transistor, the size is small, and the relative positions of a plurality of chips are required to be controlled when the power chip is attached to a substrate, so that high alignment accuracy (about +/-0.1 μm) is required. The packaging structure of the invention only has one power chip, has larger volume and low requirement on alignment precision (about +/-10 mu m).

4. The technical requirement on interface connection during pasting is low. In the traditional method for bonding the chip and the substrate, in order to prevent the tiny chip from being damaged by the uneven surface of the adhesive, pressureless sintering is often adopted, so that the adhesive is fluffy and has high thermal resistance. According to the packaging structure, the chip and the heat dissipation chassis can be subjected to press bonding or pressure-assisted sintering, and the area of the chip and the area of the heat dissipation chassis are large, so that the stress is uniform easily, and the damage of the chip is not worried.

5. And avoids material lattice defects. In the wafer process, a certain distance is reserved between the transistors instead of the close dependence of the traditional mode, and in the actual production process, the position of the transistors can be adjusted to avoid the lattice defect area of the semiconductor material.

6. A simplified method for processing a heat dissipation chassis. In order to process a micro pipeline, a traditional heat dissipation chassis needs two layers of substrates, after the micro pipeline is processed on one layer, the two layers are attached to form a heat dissipation plate, and a power module is attached to the upper part of the heat dissipation plate. In the packaging structure, the heat dissipation plate is only provided with one layer, and after the groove is etched and processed on the upper part, the monolithic integrated power module on the upper part is directly attached to the groove and covers the top of the groove to form the micro-pipeline.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.

The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions that the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the effects and the achievable by the present invention, should still fall within the range that the technical contents disclosed in the present invention can cover.

Fig. 1 is a schematic structural diagram of a package structure of a monolithically integrated power module according to embodiment 1 of the present invention;

fig. 2 is an exploded perspective view of a package structure of a monolithically integrated power module according to embodiment 1 of the present invention;

fig. 3 is a comparative diagram of a method for manufacturing a multi-tube power chip and an existing single-tube power chip in a method for manufacturing a package structure of a monolithically integrated power module according to embodiment 2 of the present invention;

in the figure: 1. a multi-tube power chip; 2. a lead wire; 3. a transistor; 4. a conductor adhesive; 5. a liquid inlet and outlet; 6. an insulating adhesive; 7. a heat dissipation chassis; 8. a groove; 9. a port; 10. a housing; 11. a wafer; 12. a combination of multiple transistors.

Detailed Description

The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

As shown in fig. 1 and fig. 2, the present embodiment proposes a monolithic integrated power module package structure, which includes a multi-tube power chip 1 and a heat dissipation chassis 7, the multi-tube power chip 1 is used for providing a logic operation function after being powered on, the heat dissipation chassis 7 is used for dissipating heat during chip operation, the multi-tube power chip 1 and the heat dissipation chassis 7 are connected by a layer of adhesive, the multi-tube power chip 1 is integrated with a plurality of transistors 3 arranged at preset insulation intervals, and the single-tube integrated multi-tube power chip 1 in this example is composed of four transistors 3.

The adhesive comprises a conductor adhesive 4 and an insulating adhesive 6, the conductor adhesive 4 is in a pattern distribution design and is electrically connected with the plurality of transistors 3, and the insulating adhesive 6 is filled in the pattern distribution gaps arranged on the conductor adhesive 4.

A heat dissipation groove 8 is formed in the heat dissipation chassis 7 in an etching mode, the adhesive is covered above the heat dissipation groove 8 in a sealing mode, the heat dissipation groove 8 is sealed up and down to form a pipeline, insulating heat dissipation working media flow through the heat dissipation groove 8, the heat dissipation groove 8 is communicated with a liquid inlet and outlet 5 of the heat dissipation working media, and the liquid inlet and outlet 5 is arranged on the heat dissipation chassis 7 in a vertically through mode.

The plurality of transistors 3 on the multi-tube power chip 1 are respectively provided with ports 9, the different transistors 3 are electrically connected through the wires 2 to the ports 9, and each transistor 3 is electrically connected to the lower conductor adhesive 4 through the wires 2 to the ports 9.

The package structure further comprises a protective casing 10 disposed above the multi-tube power chip 1 and the heat dissipation chassis 7, and plays a role in protecting the internal structure.

The packaging structure of the monolithic integrated power module provided by the embodiment of the invention has the following advantages:

1. the thermal resistance is greatly reduced. In the traditional structure, at least two layers of adhesives and one layer of ceramic substrate are separated from a heat dissipation working medium from a chip to a heat dissipation chassis.

2. The volume is small. The traditional micro-assembly method has at least three layers of modules above and below the modules, so that the size of the modules is overlarge. The packaging structure of the invention has only two layers above and below, and the volume of the module can be made smaller.

3. The alignment accuracy requirement is low. In the conventional method, one power chip only comprises one transistor, the size is small, and the relative positions of a plurality of chips are required to be controlled when the power chip is attached to a substrate, so that high alignment accuracy (about +/-0.1 μm) is required. The packaging structure of the invention only has one power chip, has larger volume and low requirement on alignment precision (about +/-10 mu m).

4. The technical requirement on interface connection during pasting is low. In the traditional method for bonding the chip and the substrate, in order to prevent the tiny chip from being damaged by the uneven surface of the adhesive, pressureless sintering is often adopted, so that the adhesive is fluffy and has high thermal resistance. According to the packaging structure, the chip and the heat dissipation chassis can be subjected to press bonding or pressure-assisted sintering, and the area of the chip and the area of the heat dissipation chassis are large, so that the stress is uniform easily, and the damage of the chip is not worried.

5. And avoids material lattice defects. In the wafer process, a certain distance is reserved between the transistors instead of the close dependence of the traditional mode, and in the actual production process, the position of the transistors can be adjusted to avoid the lattice defect area of the semiconductor material.

6. A simplified method for processing a heat dissipation chassis. In order to process a micro pipeline, a traditional heat dissipation chassis needs two layers of substrates, after the micro pipeline is processed on one layer, the two layers are attached to form a heat dissipation plate, and a power module is attached to the upper part of the heat dissipation plate. In the packaging structure, the heat dissipation plate is only provided with one layer, and after the groove is etched and processed on the upper part, the monolithic integrated power module on the upper part is directly attached to the groove and covers the top of the groove to form the micro-pipeline.

Example 2

Corresponding to embodiment 1 above, this embodiment proposes a method for manufacturing a package structure of a monolithically integrated power module, where the method includes:

a heat dissipation groove 8 and a liquid inlet and outlet 5 are processed and etched on the upper surface of the silicon carbide substrate to manufacture a heat dissipation chassis 7;

then, aligning the absolute position of the chip, bonding the single-chip integrated multi-tube power chip 1 with a heat dissipation chassis 7 through an adhesive, and sealing a heat dissipation groove 8 on the heat dissipation chassis 7;

finally, the terminal 9 of each transistor 3 is electrically connected to the underlying conductor adhesive 4 using a wire.

Further, as shown in fig. 3, the left diagram in fig. 3 is the preparation of the existing single-tube power chip, and the right diagram in fig. 3 is the preparation of the multi-tube power chip of the present embodiment, and the method further includes:

when the layout design of the wafer 11 is performed, the multi-transistor combination 12 is taken as a whole, instead of a single transistor 3, the type and the position of the transistor 3 are planned in the combination, and a sufficient insulation distance is reserved, and when the wafer 11 is cut, the single transistor 3 is not cut, but the pre-designed multi-transistor combination 12 is cut off integrally, so that the multi-transistor power chip 1 is formed.

Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.