阅读说明：本技术 包括电容器的半导体封装件 (Semiconductor package including capacitor ) 是由 严柱日 朴真敬 裵汉俊 于 2020-09-03 设计创作，主要内容包括：包括电容器的半导体封装件。一种半导体封装件包括：设置在基板上方的子半导体封装件,子半导体封装件包括：上表面上具有芯片焊盘的子半导体芯片,围绕子半导体芯片的侧表面的模塑层,以及形成在子半导体芯片和模塑层上方的重分布层,重分布层包括重分布导电层,重分布导电层连接至子半导体芯片的芯片焊盘并延伸到模塑层的边缘,同时在其端部具有重分布焊盘；第一子封装件互连器,其连接至重分布焊盘,以电连接子半导体芯片和基板；电容器,其形成在模塑层中,并且包括第一电极、第二电极以及主体部分,第一电极和第二电极具有分别连接至重分布导电层的上表面。(A semiconductor package includes a capacitor. A semiconductor package includes: a sub-semiconductor package disposed over the substrate, the sub-semiconductor package comprising: a sub-semiconductor chip having a chip pad on an upper surface thereof, a molding layer surrounding a side surface of the sub-semiconductor chip, and a redistribution layer formed over the sub-semiconductor chip and the molding layer, the redistribution layer including a redistribution conductive layer connected to the chip pad of the sub-semiconductor chip and extending to an edge of the molding layer while having the redistribution pad at an end thereof; a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; and a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer.)

1. A semiconductor package, comprising:

a substrate;

a sub-semiconductor package disposed over the substrate, the sub-semiconductor package comprising: a sub-semiconductor chip having a chip pad on an upper surface thereof; a molding layer surrounding a side surface of the sub-semiconductor chip; and a redistribution layer formed over the sub-semiconductor chip and the molding layer, the redistribution layer including a redistribution conductive layer connected to the chip pad of the sub-semiconductor chip and extending to an edge of the molding layer while having a redistribution pad at an end of the redistribution conductive layer;

a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate;

a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer; and

at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate.

2. The semiconductor package of claim 1, wherein the redistribution conductive layer comprises a ground redistribution conductive layer applied with a ground voltage and a power redistribution conductive layer applied with a power voltage, and

wherein the first electrode is connected to the ground redistribution conductive layer and the second electrode is connected to the power redistribution conductive layer.

3. The semiconductor package of claim 2, wherein the redistribution conductive layer further comprises at least one signal redistribution conductive layer located between the ground redistribution conductive layer and the power redistribution conductive layer.

4. The semiconductor package of claim 3, wherein the body portion overlaps the at least one signal redistribution conductive layer.

5. The semiconductor package of claim 2, wherein each of the first and second electrodes is disposed closer to the chip pad than the redistribution pad.

6. The semiconductor package of claim 1, wherein the redistribution layer further comprises a redistribution insulating layer formed between the redistribution conductive layer and the upper surfaces of the sub-semiconductor chip and the molding layer, and

wherein the redistribution conductive layer is connected to the chip pad, the first electrode, and the second electrode through an opening formed in the redistribution insulating layer.

7. The semiconductor package according to claim 1, wherein the sub-semiconductor package further comprises a sub-via penetrating the molding layer while being connected to a lower surface of each of the first electrode and the second electrode, and

wherein the semiconductor package further comprises:

a second sub-package interconnect disposed between the mold layer and the substrate, the second sub-package interconnect connected to the sub-vias.

8. The semiconductor package of claim 7, wherein the first sub-package interconnector includes bond wires, and

wherein the second sub-package interconnector includes at least one of a solder ball and a conductive bump.

9. The semiconductor package of claim 7, further comprising:

a dummy second sub-package interconnector disposed between the mold layer and the substrate without being connected to the sub-vias.

10. The semiconductor package of claim 7, wherein a first direct current path passes through the redistribution conductive layer, the first sub-package interconnect, and the substrate, and

wherein a second direct current path passes through the redistribution conductive layer, the first electrode or the second electrode, the sub-vias, the second sub-package interconnect, and the substrate.

11. The semiconductor package of claim 1, wherein the sub-semiconductor package further comprises a sub-via that penetrates the mold layer and has an upper surface connected to the redistribution conductive layer, and

wherein the semiconductor package further comprises:

a second sub-package interconnect disposed between the mold layer and the substrate, the second sub-package interconnect connected to the sub-vias.

12. The semiconductor package of claim 11, wherein the sub-vias are connected to the redistribution conductive layer connected to the first electrode while being spaced apart from the first electrode, and

wherein the sub-via is connected to the redistribution conductive layer connected to the second electrode while being spaced apart from the second electrode.

13. The semiconductor package of claim 11, wherein the sub-vias are disposed between the first electrode and the redistribution pad or between the second electrode and the redistribution pad.

14. The semiconductor package of claim 11, wherein the first sub-package interconnector includes bond wires, and

wherein the second sub-package interconnector includes at least one of a solder ball and a conductive bump.

15. The semiconductor package of claim 11, further comprising:

a dummy second sub-package interconnector disposed between the mold layer and the substrate without being connected to the sub-vias.

16. The semiconductor package of claim 11, wherein a first direct current path passes through the redistribution conductive layer, the first sub-package interconnect, and the substrate, and

wherein a second direct current path passes through the redistribution conductive layer, the sub-vias, the second sub-package interconnect, and the substrate.

17. The semiconductor package of claim 1, wherein the at least one main semiconductor chip comprises a memory, and

the sub-semiconductor chip includes a memory controller.

18. The semiconductor package of claim 1, wherein the substrate includes a substrate pad disposed at each of a first side edge and a second side edge of the substrate in a first direction, and

wherein the at least one main semiconductor chip comprises:

at least one first main semiconductor chip connected to the substrate pad disposed at the first side edge of the substrate through a first interconnector; and

at least one second main semiconductor chip connected to the substrate pad disposed at the second side edge of the substrate through a second interconnector.

19. The semiconductor package of claim 18, wherein the at least one first main semiconductor chip comprises a plurality of first main semiconductor chips stacked offset in the first direction from a first side toward a second side, and

wherein the at least one second main semiconductor chip includes a plurality of second main semiconductor chips stacked offset from the second side toward the first side in the first direction.

20. The semiconductor package of claim 18, wherein the redistribution pad is disposed at each of a first side edge and a second side edge of the molding layer in the first direction, and

wherein the first sub-package interconnector connects the redistribution pad disposed at the first side edge of the mold layer and the substrate pad disposed at the first side edge of the substrate to each other, and connects the redistribution pad disposed at the second side edge of the mold layer and the substrate pad disposed at the second side edge of the substrate to each other.

21. The semiconductor package according to claim 20, wherein the chip pads of the sub-semiconductor chip are disposed along first and second side edges of the sub-semiconductor chip in the first direction, and along first and second side edges of the sub-semiconductor chip in a second direction, the second direction being perpendicular to the first direction.

22. The semiconductor package of claim 21, wherein the chip pad disposed at a first side edge of the sub-semiconductor chip in the first direction and the second direction extends toward the redistribution pad disposed at a first side edge of the molding layer in the first direction, and

wherein the chip pad disposed at a second side edge of the sub-semiconductor chip in the first direction and the second direction extends toward the redistribution pad disposed at a second side edge of the molding layer in the first direction.

Technical Field

This patent document relates to semiconductor packages, and more particularly, to semiconductor packages including capacitors.

Background

Recently, demands for high-speed operation and large-capacity data processing of semiconductor devices have increased. For this reason, the number of signals simultaneously transmitted to the semiconductor device or the signal transmission speed needs to be increased.

However, there is a problem in that power/ground noise increases as the semiconductor device operates at high speed and the number of signals transmitted at the same time increases. Therefore, a method of adding a capacitor (i.e., decoupling capacitor) for stabilizing power supply/ground supply to the power transmission path is currently used.

Disclosure of Invention

In an embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package disposed over the substrate, the sub-semiconductor package comprising: a sub-semiconductor chip having a chip pad on an upper surface thereof; a molding layer surrounding a side surface of the sub-semiconductor chip; and a redistribution layer formed over the sub-semiconductor chip and the molding layer, the redistribution layer including a redistribution conductive layer connected to the chip pad of the sub-semiconductor chip and extending to an edge of the molding layer while having the redistribution pad at an end thereof; a first sub-package interconnector connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer; and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate.

Drawings

Fig. 1 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

Fig. 2 is a plan view illustrating a portion of the semiconductor package shown in fig. 1, in which a first chip stack, a second chip stack, and an interconnector connected to the first chip stack and the second chip stack are omitted.

Fig. 3 is a sectional view illustrating the semiconductor package shown in fig. 1.

Fig. 4 is a plan view illustrating the sub semiconductor package of fig. 1.

Fig. 5 is a sectional view taken along line a2-a 2' of fig. 4.

Fig. 6 is a sectional view taken along line A3-A3' of fig. 4.

Fig. 7A is a diagram for explaining an example of the effect of the semiconductor package according to the embodiment of the present disclosure.

Fig. 7B is a diagram for explaining an effect of the semiconductor package according to the comparative example.

Fig. 8 is a sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

Fig. 9 is a plan view illustrating the sub semiconductor package of fig. 8.

Fig. 10 is a sectional view taken along line a4-a 4' of fig. 9.

Fig. 11 is a sectional view taken along line a5-a 5' of fig. 9.

Fig. 12A is a diagram for explaining an example of the effect of a semiconductor package according to another embodiment of the present disclosure.

Fig. 12B is a diagram for explaining an effect of the semiconductor package according to the comparative example.

Fig. 13 is a sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

Fig. 14 is a plan view illustrating a sub semiconductor package in a semiconductor package according to another embodiment of the present disclosure.

Fig. 15 is a sectional view taken along line a6-a 6' of fig. 14.

Fig. 16 is a sectional view taken along line a7-a 7' of fig. 14.

Fig. 17A is a diagram for explaining an example of the effect of a semiconductor package according to another embodiment of the present disclosure.

Fig. 17B is a diagram for explaining the effect of the semiconductor package of the comparative example.

Fig. 18 shows a block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment.

Fig. 19 shows a block diagram illustrating another electronic system including a semiconductor package according to an embodiment.

Detailed Description

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

The drawings are not necessarily to scale. In some instances, the scale of at least some of the structures in the figures may have been exaggerated in order to clearly illustrate some of the features of the described embodiments. In presenting specific examples in the drawings or description of two or more layers having a multilayer structure, the relative positional relationship of such layers or the order of arrangement of such layers shown reflects a specific implementation of the described or illustrated example, and different relative positional relationship or order of arrangement of such layers may be possible. Additionally, the described or illustrated examples of a multilayer structure may not reflect all of the layers present in a particular multilayer structure (e.g., there may be one or more additional layers between the two illustrated layers). As a specific example, when a first layer in a multilayer structure described or illustrated is referred to as being "on" or "over" a second layer or as being "on" or "over" a substrate, the first layer may be formed directly on the second layer or the substrate, but may also represent a structure in which one or more other intermediate layers may be present between the first layer and the second layer or the substrate.

Fig. 1 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure. Fig. 2 is a plan view illustrating a portion of the semiconductor package shown in fig. 1, in which a first chip stack, a second chip stack, and an interconnector connected to the first chip stack and the second chip stack are omitted. Fig. 3 is a sectional view illustrating the semiconductor package of fig. 1. Fig. 1 and 2 are top views of a semiconductor package and a portion thereof, respectively. Fig. 3 illustrates a cross-section taken along line a1-a 1' of fig. 1 and 2. Fig. 4 is a plan view illustrating the sub semiconductor package of fig. 1, fig. 5 is a sectional view taken along line a2-a2 'of fig. 4, and fig. 6 is a sectional view taken along line A3-A3' of fig. 4.

First, referring to fig. 1 to 3, a semiconductor package according to an embodiment of the present disclosure may include a substrate 100, a sub semiconductor package 110 disposed over the substrate 100, and a first chip stack 120 and a second chip stack 130 disposed over the sub semiconductor package 110.

The substrate 100 may be a substrate such as a Printed Circuit Board (PCB) for a semiconductor package, which has a circuit and/or wiring structure to transmit an electrical signal.

The substrate 100 may have an upper surface and a lower surface located opposite to the upper surface. The sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 may be disposed over an upper surface of the substrate 100. External connection terminals 140 for connecting the semiconductor package with the outside may be disposed over the lower surface of the substrate 100. For reference, the upper and lower surfaces to be described below are expressions indicating relative positions of respective surfaces of the component, and do not indicate absolute positions. For example, in the case where the semiconductor package is turned upside down unlike the illustration, the surface on which the sub-semiconductor package 110 and the first and second chip laminates 120 and 130 are disposed may be a lower surface of the substrate 100, and the surface on which the external connection terminals 140 are disposed may be an upper surface of the substrate 100.

Substrate 100 may include upper surface substrate pads 102 and lower surface substrate pads 104. The upper surface substrate pad 102 may be disposed on an upper surface of the substrate 100 to electrically connect the sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 with the substrate 100. The lower surface substrate pad 104 may be disposed on the lower surface of the substrate 100 to electrically connect the external connection terminal 140 with the substrate 100. For reference, the substrate pad may mean a conductive element or a terminal exposed on the surface of the substrate 100 to electrically connect the substrate 100 with other components. As an example, the upper surface substrate pads 102 may be bond fingers for wire bonding, and the lower surface substrate pads 104 may be ball lands (ball lands) for bonding with solder balls. The upper surface substrate pads 102 and the lower surface substrate pads 104 may be connected to circuitry and/or wiring structures within the substrate 100.

The upper surface substrate pad 102 may be disposed at both side edges of the substrate 100 that do not overlap with the sub semiconductor package 110. For example, the upper surface substrate pads 102 may be disposed at both side edges of the substrate 100 in the first direction. For reference, a first side of the two sides in the first direction may correspond to an upper side of fig. 1 and 2, and a left side of fig. 3. Further, a second side of the two sides in the first direction may correspond to a lower side of fig. 1 and 2, and a right side of fig. 3. In the present embodiment, the upper-surface substrate pads 102 may be arranged in a row at each of both side edges of the substrate 100 in a second direction intersecting the first direction. However, the present embodiment is not limited thereto. The number, arrangement, etc. of the upper surface substrate pads 102 may be variously modified at each of the two side edges of the substrate 100.

The sub semiconductor package 110 may have a smaller planar area than the upper surface of the substrate 100. The sub-semiconductor package 110 may be disposed to expose at least both side edges of the substrate 100 in the first direction and/or the upper surface substrate pad 102. As an example, the sub semiconductor package 110 may be disposed at a central region of the substrate 100. The sub-semiconductor package 110 may be attached to the upper surface of the substrate 100 by an insulating adhesive material (not shown) such as a Die Attach Film (DAF).

The sub-semiconductor package 110 may include a sub-semiconductor chip 114, a sub-molding layer 116 surrounding lower and side surfaces of the sub-semiconductor chip 114, and a redistribution structure 118 formed over upper surfaces of the sub-semiconductor chip 114 and the sub-molding layer 116.

The sub-semiconductor chip 114 may be a semiconductor chip that performs various functions required for the operation of the first main semiconductor chip 124 and/or the second main semiconductor chip 134. As an example, in the case where each of the first and second main semiconductor chips 124 and 124 includes a nonvolatile memory such as a NAND flash memory, the sub semiconductor chip 114 may include a controller for controlling the first and second main semiconductor chips 124 and 134. However, the present embodiment is not limited thereto, and the sub-semiconductor chip 114 may include volatile memories such as a Dynamic Random Access Memory (DRAM) and a static ram (sram), non-volatile memories such as a NAND flash memory, a resistive ram (rram), a phase-change ram (pram), a magnetoresistive ram (mram), and a ferroelectric ram (fram), or other various active elements or passive elements.

The sub semiconductor chip 114 may have a lower surface facing the upper surface of the substrate 100, an upper surface located opposite to the lower surface thereof, and a side surface connecting the upper and lower surfaces thereof. In the present embodiment, the sub-semiconductor chip 114 may have four side surfaces. The four side surfaces may be located at both sides in the first direction and both sides in the second direction, respectively. For reference, a first side of the two sides in the second direction may correspond to a right side of fig. 1 and 2, and a second side of the two sides in the second direction may correspond to a left side of fig. 1 and 2.

The sub-semiconductor chip 114 may be located at a central region of the sub-semiconductor package 110. This is to make lengths of the redistribution conductive layers 118B, which will be described later, as similar to each other as possible.

The sub-chip pad 115 may be disposed on an upper surface of the sub-semiconductor chip 114. The sub-semiconductor chip 114 may have a relatively small planar area, and the number of sub-chip pads 115 may be relatively large. As an example, a case may be assumed where the sub semiconductor chip 114 is a memory controller and the first main semiconductor chip 124 and the second main semiconductor chip 134 are memories. In this case, although the size of the sub semiconductor chip 114 is reduced as the technology is developed, a large number of sub chip pads 115 corresponding to a large number of input/output signals may be required in order to connect the respective first and second chip stacks 120 and 130 with the sub semiconductor chip 114 through independent channels. Due to this fact, the sub-chip pads 115 may be arranged along the entire edge of the sub-semiconductor chip 114. That is, the sub-chip pads 115 may be arranged along the first and second side edges of the sub-semiconductor chip 114 in the first direction, and arranged along the first and second side edges of the sub-semiconductor chip 114 in the second direction.

The sub-molding layer 116 may have an upper surface substantially at the same height as the upper surface of the sub-semiconductor chip 114 while surrounding the side surface of the sub-semiconductor chip 114. Accordingly, the sub-mold layer 116 may expose the upper surfaces of the sub-chip pad 115 and the sub-semiconductor chip 114. In this embodiment, the sub-mold layer 116 may cover the lower surface of the sub-semiconductor chip 114. However, the present embodiment is not limited thereto. In another embodiment, the sub mold layer 116 may have a lower surface having substantially the same height as the lower surface of the sub semiconductor chip 114. The sub-mold layer 116 may include various molding materials such as Epoxy Molding Compound (EMC).

The redistribution structure 118 may extend onto the upper surface of the sub-mold layer 116 while being electrically connected with the sub-chip pad 115. In other words, the sub-semiconductor package 110 according to the present embodiment may be a fan-out package.

In detail, the redistribution structure 118 may include a first redistribution insulating layer 118A, a redistribution conductive layer 118B, and a second redistribution insulating layer 118C. A first redistribution insulating layer 118A may be formed over the upper surfaces of the sub-semiconductor chip 114 and the sub-molding layer 116. The first redistribution insulating layer 118A may have an opening exposing the sub chip pad 115. A redistribution conductive layer 118B may be formed over the first redistribution insulating layer 118A. The redistribution conductive layer 118B may be electrically connected with the sub chip pad 115 through the opening of the first redistribution insulation layer 118A. The second redistribution insulating layer 118C may cover the first redistribution insulating layer 118A and the redistribution conductive layer 118B. The second redistribution insulating layer 118C may have an opening exposing an end of the redistribution conductive layer 118B. The first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include an insulating material such as an oxide, a nitride, or an oxynitride. Alternatively, the first redistribution insulating layer 118A and the second redistribution insulating layer 118C may include a resin material such as epoxy, polyimide, Polybenzoxazole (PBO), benzocyclobutene (BCB), silicone, or acrylate. The redistribution conductive layer 118B may include a metallic material such as gold, copper, or a copper alloy.

Specifically, a portion of the redistribution conductive layer 118B exposed through the opening of the second redistribution insulating layer 118C will be hereinafter referred to as a redistribution pad 118 BP. The redistribution conductive layers 118B may extend from the sub-chip pad 115, and each redistribution conductive layer 118B may have a linear portion having a relatively small width and a plate-shaped end portion having a relatively large width and located at an end of the linear portion. The opening of the second redistribution insulating layer 118C may expose the plate-shaped end portion of the redistribution conductive layer 118B, and may have a planar area less than or equal to a planar area of the plate-shaped end portion while overlapping the plate-shaped end portion. In the top views of fig. 1 and 2, the first redistribution insulating layer 118A and the second redistribution insulating layer 118C of the redistribution structure 118 are not illustrated for convenience of explanation. Similar to the arrangement of the upper surface substrate pads 102, the redistribution pads 118BP may be disposed at first and second side edges of the sub-molding layer 116 in the first direction. Further, the redistribution pads 118BP may be arranged in a row in the second direction at each of the first side edge and the second side edge of the sub-mold layer 116. However, the present disclosure is not limited thereto, and the number, arrangement, etc. of the redistribution pads 118BP at each of the first and second side edges of the sub-mold layer 116 may be variously modified.

According to the arrangement of the redistribution pads 118BP, the redistribution conductive layer 118B may extend from the sub-chip pad 115 disposed at the first side edge of the sub-semiconductor chip 114 in the first and second directions to the redistribution pad 118BP disposed at the first side edge of the sub-molding layer 116 in the first direction. Further, the redistribution conductive layer 118B may extend from the sub chip pad 115 disposed at the second side edge of the sub semiconductor chip 114 in the first and second directions to the redistribution pad 118BP disposed at the second side edge of the sub molding layer 116 in the first direction. The redistribution conductive layer 118B extending from both side edges of the sub-semiconductor chip 114 in the second direction may have a bent shape toward the redistribution pad 118 BP. Further, the redistribution conductive layers 118B extending from both side edges of the sub-semiconductor chip 114 in the first direction may not need to be bent because these redistribution conductive layers 118B face the redistribution pads 118 BP. However, in order to have a length similar to that of the redistribution conductive layer 118B extending from both side edges of the sub-semiconductor chip 114 in the second direction, the redistribution conductive layer 118B extending from both side edges of the sub-semiconductor chip 114 in the first direction may also have a curved shape. As a result, the redistribution conductive layer 118B may have a tornado-like shape, e.g., a spiral shape, centered on the sub-semiconductor chip 114. By this connection scheme, variations in length of the redistribution conductive layer 118B may be reduced.

The sub-package interconnector 117 may connect the redistribution pad 118BP and the upper surface substrate pad 102. By this fact, the sub semiconductor chip 114 and the substrate 100 can be electrically connected. The sub-package interconnector 117 may be a bond wire having a first end connected to the upper surface substrate pad 102 and a second end connected to the redistribution pad 118 BP. However, the present embodiment is not limited thereto, and various types of electrical interconnects may be used as the sub-package interconnector 117.

First chip stack 120 may include a plurality of first main semiconductor chips 124. The first main semiconductor chip 124 may be formed over the sub semiconductor package 110 and may be stacked in a vertical direction with respect to the upper surface of the substrate 100. Although the present embodiment illustrates a case where the first chip stack 120 includes four first main semiconductor chips 124, the present disclosure is not limited thereto, and the number of first main semiconductor chips 124 included in the first chip stack 120 may be variously modified into one or more first main semiconductor chips 124.

Each of the first main semiconductor chips 124 may include a NAND flash memory as described above. However, the present disclosure is not limited thereto, and each of the first main semiconductor chips 124 may include volatile memory such as Dynamic Random Access Memory (DRAM) and static ram (sram), or non-volatile memory such as resistive ram (rram), phase change ram (pram), magnetoresistive ram (mram), and ferroelectric ram (fram).

The first main semiconductor chips 124 may be stacked with a predetermined offset in a direction toward the second side in the first direction (for example, in a direction toward the lower side in fig. 1 and the right side in fig. 3). By this fact, the first chip stack 120 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the first main semiconductor chip 124 may be referred to as a first offset direction. According to such offset stacking, the first side edge of the upper surface of each remaining first main semiconductor chip 124 except for the uppermost first main semiconductor chip 124 among the first main semiconductor chips 124 may be exposed without being covered by the first main semiconductor chip 124 placed immediately thereon. For example, an upper side of the upper surface of each of the remaining first main semiconductor chips 124 in fig. 1 and a left side of the upper surface of each of the remaining first main semiconductor chips 124 in fig. 3 may be exposed. A first side edge of the upper surface of the uppermost first main semiconductor chip 124 may be exposed without being covered by a lowermost second main semiconductor chip 134 of a second chip stack 130, which will be described later. The first chip pad 125 may be disposed on such an exposed portion of the first main semiconductor chip 124. The plurality of first chip pads 125 may be arranged in a row at a first side edge of the upper surface of each first main semiconductor chip 124 in the second direction. However, the present disclosure is not limited thereto, and the number and arrangement of the first chip pads 125 at the first side edge of the upper surface of each first main semiconductor chip 124 may be variously modified. For reference, since a portion of the first chip stack 120 hidden by the second chip stack 130 is not illustrated in the top view of fig. 1, a portion of the first chip stack 120, for example, a first side edge portion of the lowermost first main semiconductor chip 124 is illustrated.

Each of the first main semiconductor chips 124 may be attached to the sub-semiconductor package 110 or the first main semiconductor chip 124 disposed immediately therebelow by a first adhesive layer 122. The first adhesive layer 122 may be formed on the lower surface of each first main semiconductor chip 124 to have a shape overlapping the lower surface.

The first chip laminate 120 or the first main semiconductor chip 124 may have a smaller planar area than the sub-semiconductor package 110 and may have a larger planar area than the sub-semiconductor chip 114. The first chip stack 120 may be disposed to expose at least the redistribution pads 118BP disposed at both side edges of the sub-semiconductor package 110 in the first direction.

The first interconnector 127 may connect the first chip pads 125 adjacent in the vertical direction to each other, and may electrically connect the first chip pad 125 of the lowermost first main semiconductor chip 124 with the upper surface substrate pad 102 disposed at a first side edge of the substrate 100 in the first direction. By this fact, the first main semiconductor chips 124 may be electrically connected to each other, and the first chip stack 120 may be electrically connected to the substrate 100. The first interconnector 127 may be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the first interconnector 127.

The second chip stack 130 may include a plurality of second main semiconductor chips 134. The second main semiconductor chip 134 may be formed over the first chip stack 120 and may be stacked in a vertical direction. Although the present embodiment illustrates the case where the second chip stack 130 includes four second main semiconductor chips 134, the present disclosure is not limited thereto, and the number of second main semiconductor chips 134 included in the second chip stack 130 may be variously modified into one or more second main semiconductor chips 134. Further, although in the present embodiment, the number of the second main semiconductor chips 134 included in the second chip stack 130 is the same as the number of the first main semiconductor chips 124 included in the first chip stack 120, it should be noted that these numbers may be different from each other.

Each second master semiconductor chip 134 may include a NAND flash memory as described above. However, the present disclosure is not limited thereto, and each of the second main semiconductor chips 134 may include volatile memories such as Dynamic Random Access Memory (DRAM) and static ram (sram), or non-volatile memories such as resistive ram (rram), phase change ram (pram), magnetoresistive ram (mram), and ferroelectric ram (fram). In this embodiment, the second main semiconductor chip 134 is the same semiconductor chip as the first main semiconductor chip 124. However, in another embodiment, the second main semiconductor chip 134 may be a different semiconductor chip than the first main semiconductor chip 124.

The second main semiconductor chips 134 may be stacked with a predetermined offset in a direction toward a first side in the first direction (for example, in a direction toward an upper side in fig. 1 and a left side in fig. 3). By this fact, the second chip laminate 130 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the second main semiconductor chip 134 may be referred to as a second offset direction. The second offset direction may be opposite to the first offset direction. According to such offset stacking, except for the uppermost second main semiconductor chip 134 among the second main semiconductor chips 134, the second side of the upper surface of each remaining second main semiconductor chip 134 may be exposed without being covered by the second main semiconductor chip 134 placed immediately thereon. For example, a lower side edge of the upper surface of each remaining second main semiconductor chip 134 in fig. 1 and a right side edge of the upper surface of each remaining second main semiconductor chip 134 in fig. 3 may be exposed. The uppermost second main semiconductor chip 134 may be in a state where the entire upper surface thereof is exposed. The second chip pad 135 may be disposed on the exposed portion of the remaining second main semiconductor chips 134 except for the uppermost second main semiconductor chip 134, and the second chip pad 135 of the uppermost second main semiconductor chip 134 may also be disposed at the same position as the second chip pads 135 of the remaining second main semiconductor chips 134. The plurality of second chip pads 135 may be arranged in a row at a second side edge of the upper surface of each second main semiconductor chip 134 in the second direction. However, the present disclosure is not limited thereto, and the number and arrangement of the second chip pads 135 at the second side edge of the upper surface of each second main semiconductor chip 134 may be variously modified.

In the case where the second main semiconductor chips 134 are the same semiconductor chips as the first main semiconductor chips 124, each of the second main semiconductor chips 134 may correspond to a state in which each of the first main semiconductor chips 124 is rotated by 180 degrees about an axis extending in the vertical direction.

Each second main semiconductor chip 134 may be attached to the second main semiconductor chip 134 placed immediately therebelow or the uppermost first main semiconductor chip 124 of the first chip stack 120 by a second adhesive layer 132. The second adhesive layer 132 may be formed on the lower surface of each second main semiconductor chip 134 to have a shape overlapping the lower surface.

The second chip laminate 130 or the second main semiconductor chip 134 may have a smaller planar area than the sub-semiconductor package 110 and may have a larger planar area than the sub-semiconductor chip 114. The second chip laminate 130 may be disposed to expose at least both side edges of the sub-semiconductor packages 110 in the first direction. That is, the second chip laminate 130 may be disposed to expose the redistribution pad 118 BP.

The second interconnector 137 may connect the second chip pads 135 adjacent in the vertical direction to each other, and may electrically connect the second chip pad 135 of the lowermost second main semiconductor chip 134 with the upper surface substrate pad 102 disposed at the second side edge of the substrate 100 in the first direction. By this fact, the second main semiconductor chips 134 may be electrically connected to each other, and the second chip laminate 130 may be electrically connected to the substrate 100. The second interconnector 137 may be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the second interconnector 137.

In the top views of fig. 1 and 2, the sub-package interconnector 117, the first interconnector 127, and the second interconnector 137 are illustrated with solid lines and dotted lines for convenience of distinction. It should be noted, however, that of course, such solid and dashed lines do not reflect the actual shape of the interconnects 117, 127, and 137.

The sub-semiconductor package 110, the first chip laminate 120, and the second chip laminate 130 may be covered by a molding layer 150 formed over the substrate 100. The molding layer 150 may include various molding materials such as EMC.

The external connection terminals 140 may include solder balls. However, the present disclosure is not limited thereto, and various conductive terminals such as bumps may be used as the external connection terminals 140.

In the above semiconductor package, the first chip laminate 120 may be recognized as a single semiconductor chip while being connected with the upper surface substrate pad 102 of the substrate 100 through the first interconnector 127. Further, the second chip stack 130 may be identified as another single semiconductor chip different from the first chip stack 120 while being connected with the upper surface substrate pad 102 of the substrate 100 through the second interconnector 137. The sub-semiconductor chip 114 may be connected with the upper surface substrate pad 102 of the substrate 100 through the redistribution structure 118 and the sub-package interconnector 117.

Further, in the above-described semiconductor package, the sub-package interconnector 117 may be individually connected to the upper surface substrate pad 102, the first interconnector 127 may be individually connected to the upper surface substrate pad 102, the second interconnector 137 may be individually connected to the upper surface substrate pad 102, the sub-package interconnector 117 and the first interconnector 127 may be commonly connected to the upper surface substrate pad 102, or the sub-package interconnector 117 and the second interconnector 137 may be commonly connected to the upper surface substrate pad 102. The upper surface substrate pad 102 separately connected to the sub-package interconnector 117 may serve as a power supply voltage supply pad or a signal transmission pad of the sub-semiconductor chip 114. The upper surface substrate pad 102 separately connected to the first interconnector 127 may serve as a power voltage supply pad or a signal transmission pad of the first chip stack 120. The upper surface substrate pad 102 separately connected to the second interconnector 137 may serve as a power voltage supply pad or a signal transmission pad of the second chip laminate 130. The upper surface substrate pad 102 commonly connected to the sub-package interconnector 117 and the first interconnector 127, and/or the upper surface substrate pad 102 commonly connected to the sub-package interconnector 117 and the second interconnector 137 may be used as a ground voltage supply pad. This may mean supplying power or transmitting a signal from the substrate 100 to each of the sub semiconductor chip 114, the first chip stack 120, and the second chip stack 130.

Specifically, the power supply or the transmission of signals to the sub semiconductor chip 114 may be performed by the redistribution conductive layer 118B. However, since a large number of the redistribution conductive layers 118B are disposed in a limited space, the pitch and/or line width of the redistribution conductive layers 118B may be reduced. In this case, the impedance of the redistribution conductive layer 118B may increase, and thus a problem of interrupting the power supply may be caused. To solve this problem, as shown in the plan view of fig. 2, the sub semiconductor package 110 may further include a capacitor (see a dotted square) connected to the redistribution conductive layer 118B. The capacitor will be described in more detail below with reference to fig. 4 to 6.

Referring to fig. 4 to 6, the sub chip pads 115 on the upper surface of the sub semiconductor chip 114 may include a signal sub chip pad 115-S, a ground sub chip pad 115-G, and a power supply sub chip pad 115-P. Redistribution conductive layer 118B may include signal redistribution conductive layers 118B-S connected to signal chiplet pads 115-S, ground redistribution conductive layers 118B-G connected to ground chiplet pads 115-G, and power redistribution conductive layers 118B-P connected to power chiplet pads 115-P. Signal redistribution pads 118BP-S may be disposed at ends of the signal redistribution conductive layers 118B-S, ground redistribution pads 118BP-G may be disposed at ends of the ground redistribution conductive layers 118B-G, and power redistribution pads 118BP-P may be disposed at ends of the power redistribution conductive layers 118B-P. The sub semiconductor chip 114 may receive signals from the substrate (see 100 in fig. 1 to 3) through the signal redistribution conductive layer 118B-S. Further, the sub semiconductor chip 114 may be supplied with a ground voltage from the substrate (see 100 in fig. 1 to 3) through the ground redistribution conductive layer 118B-G. Further, the sub semiconductor chip 114 may be supplied with a power supply voltage from the substrate (see 100 in fig. 1 to 3) through the power redistribution conductive layer 118B-P. That is, the ground redistribution conductive layers 118B-G and the power redistribution conductive layers 118B-P may correspond to power supply paths from the substrate 100 to the sub semiconductor chips 114.

A capacitor 160 including a first electrode 162, a second electrode 164, and a body portion 166 therebetween may be disposed in the sub-molding layer 116. The body portion 166 may have various structures as long as it can store charges according to voltages applied to the first and second electrodes 162 and 164. As an example, the capacitor 160 may be an MLCC (multilayer ceramic capacitor). In this case, the body portion 166 may have a structure in which a plurality of ceramic dielectric layers and a plurality of internal electrodes are alternately stacked.

The capacitor 160 may be embedded in the sub-molding layer 116 along with the sub-semiconductor chip 114. That is, the side surfaces and the lower surface of the capacitor 160 may be surrounded by the sub-molding layer 116. On the other hand, the upper surface of the capacitor 160 (specifically, the upper surfaces of the first and second electrodes 162 and 164) may be exposed by being located at substantially the same height as the upper surface of the sub molding layer 116. The upper surface of the first electrode 162 may be connected to the ground redistribution conductive layers 118B-G and the upper surface of the second electrode 164 may be connected to the power redistribution conductive layers 118B-P. More specifically, the ground redistribution conductive layers 118B-G and the power redistribution conductive layers 118B-P may be connected to the upper surfaces of the first electrode 162 and the second electrode 164, respectively, through the openings of the first redistribution insulating layer 118A. On the other hand, the body portion 166 may be insulated from the redistribution conductive layer 118B. For this reason, there may be no opening in a portion of the first redistribution insulating layer 118A corresponding to the body portion 166. For reference, for convenience of description, the first electrode 162 of the capacitor 160 is represented by a non-shaded rectangle, and the second electrode 164 of the capacitor 160 is represented by a shaded rectangle. However, the hatching is only used to distinguish the first electrode 162 and the second electrode 164. In addition, the planar shapes of the first electrode 162 and the second electrode 164 may also be modified in various ways.

As described above, the redistribution conductive layer 118B may also be connected to the sub chip pad 115 through the opening of the first redistribution insulating layer 118A. Accordingly, the upper surface of the first electrode 162 and the upper surface of the second electrode 164 may be located at substantially the same height as the upper surface of the sub chip pad 115. The upper surface of the body portion 166 may be at a lower level than the upper surface of the first electrode 162 and/or the second electrode 164, as shown. In this case, the first redistribution insulating layer 118A and the sub-molding layer 116 may be interposed between the body portion 166 and the redistribution conductive layer 118B. However, in another embodiment, the upper surface of the body portion 166 may be located at substantially the same height as the upper surface of the first electrode 162 and/or the second electrode 164.

The capacitor 160 may be connected to the sub-chip pad 115 that supplies the power supply voltage and the ground voltage to the sub-semiconductor chip 114, and may function to prevent a power shortage from occurring during the operation of the sub-semiconductor chip 114. When the capacitor 160 is disposed adjacent to the sub-semiconductor chip 114, the power supply path can be shortened to more efficiently perform the function. In the present embodiment, the capacitor 160 may be disposed closer to the sub-chip pad 115 than the gravity distribution pad 118 BP.

In the present embodiment, four capacitors 160 may be respectively disposed to face four side surfaces of the sub-semiconductor chip 114. However, the present disclosure is not limited thereto, and the number and position of the capacitors 160 may be modified in various ways.

Further, one or more signal redistribution conductive layers 118B-S may be disposed between ground redistribution conductive layers 118B-G and power redistribution conductive layers 118B-P. Ground redistribution conductive layers 118B-G and power redistribution conductive layers 118B-P may be used to shield signal redistribution conductive layers 118B-S therebetween. Accordingly, interference between the signal redistribution conductive layer 118B-S disposed between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P and the other signal redistribution conductive layer 118B-S can be suppressed. For reference, in this case, the body portion 166 may overlap one or more signal redistribution conductive layers 118B-S disposed between the ground redistribution conductive layers 118B-G and the power redistribution conductive layers 118B-P.

According to the semiconductor package described above, the following effects can be achieved.

First, since the sub-chip pads 115 are disposed along the entire edge of the sub-semiconductor chip 114, a relatively large number of sub-chip pads 115 may be disposed compared to the size of the sub-semiconductor chip 114. In addition, by redistributing the sub chip pad 115 using a fan-out technique, the connection between the sub chip pad 115 and the chip pads 125 and 135 of the main semiconductor chips 124 and 134 can be easily achieved. For example, if the bonding wire is directly connected to the sub-semiconductor chip 114, the arrangement of the sub-chip pad 115 may be limited due to physical limitations such as the size and moving radius of the wire capillary. On the other hand, as in the present embodiment, if the sub chip pads 115 are redistributed by the fan-out technique using the redistribution pads 118BP, the design may not be affected by such a limitation.

Further, since the sub semiconductor packages 110 larger than the first main semiconductor chip 124 are disposed under the first chip stack 120 by using the fan-out technique, the first chip stack 120 may be stably formed. In the structure in which the first chip stack 120 is formed on the sub semiconductor chip 114, if the sub semiconductor chip 114 is smaller than the first main semiconductor chip 124, a problem of inclination of the first chip stack 120 may be caused. Such a problem may not be caused by substantially increasing the area of the sub-semiconductor chip 114 by using the fan-out technique.

Further, by adjusting the shape and/or arrangement of the redistribution conductive layer 118B connecting the chiplet pad 115 and the redistribution pad 118BP so that the redistribution conductive layer 118B has a similar length, the operating characteristics of the semiconductor package can be ensured. For example, when there is a first channel connected from the first chip stack 120 to the substrate 100 and a second channel connected from the second chip stack 130 to the substrate 100, the path of the first channel and the path of the second channel may have similar lengths. Accordingly, it is possible to maximally prevent the transfer rate of a signal (e.g., data) from becoming different from channel to channel.

Further, by disposing the capacitor 160 adjacent to the sub-semiconductor chip 114 in the sub-molding layer 116, even if the pitch and/or line width of the redistribution conductive layer 118B is reduced, it is possible to assist in supplying power to the sub-semiconductor chip 114.

Further, by placing one or more signal redistribution conductive layers 118B-S between ground redistribution conductive layers 118B-G and power redistribution conductive layers 118B-P, interference between signal redistribution conductive layers 118B-S may be suppressed.

Further, when the capacitor 160 is provided so as to be connected to the redistribution conductive layer 118B in the sub-semiconductor package 110 as in the present embodiment, an alternating current path through the capacitor 160 can be shortened, as compared with a case where a capacitor is arranged around the sub-semiconductor package 110. Therefore, the impedance of the power supply path can be further reduced. This will be further described with reference to fig. 7A and 7B.

Fig. 7A is a diagram for explaining an example of the effect of the semiconductor package according to the embodiment of the present disclosure, and fig. 7B is a diagram for explaining the effect of the semiconductor package according to the comparative example. Fig. 7B illustrates a case where the capacitor 160' is separately provided around the sub semiconductor package 110, unlike the present embodiment.

Referring to fig. 7A, because capacitor 160 is connected to a point of each of ground redistribution conductive layers 118B-G and power redistribution conductive layers 118B-P, a short alternating current path (see dashed arrow) may be formed through a portion of power redistribution conductive layers 118B-P, capacitor 160, and a portion of ground redistribution conductive layers 118B-G.

On the other hand, referring to fig. 7B, a long ac path (see a dotted arrow) may be formed through the entire power redistribution conductive layer 118-P, the sub-package interconnector 117, the substrate 100, the external connection terminal 140 for supplying a power voltage, the substrate 100, the capacitor 160', the substrate 100, the external connection terminal 140 for supplying a ground voltage, the substrate 100, the sub-package interconnector 117, and the entire ground redistribution conductive layer 118B-G.

As a result, according to the present embodiment, as shown in fig. 7A, a short alternating current path passing through the capacitor 160 can be formed, and therefore, the impedance of the power supply path can be reduced. Therefore, the power supply can be easily performed.

Fig. 8 is a sectional view illustrating a semiconductor package according to another embodiment of the present disclosure, fig. 9 is a plan view illustrating a sub semiconductor package of fig. 8, fig. 10 is a sectional view taken along line a4-a4 'of fig. 9, and fig. 11 is a sectional view taken along line a5-a 5' of fig. 9. FIG. 8 is based on a cross section along line A1-A1' of FIG. 1. Hereinafter, differences from the above-described embodiments will be mainly described.

First, referring to fig. 9 to 11, the sub-semiconductor package 210 of the present embodiment may include a sub-semiconductor chip 214, a sub-molding layer 216 surrounding at least a side surface of the sub-semiconductor chip 214, a redistribution structure including a first redistribution insulating layer 218A, a redistribution conductive layer 218B, and a second redistribution insulating layer 218C and formed over upper surfaces of the sub-semiconductor chip 214 and the sub-molding layer 216, and a capacitor 260 disposed in the sub-molding layer 216 and including a first electrode 262, a second electrode 264, and a body portion 266 therebetween. The sub-chip pad 215 may be disposed on the upper surface of the sub-semiconductor chip 214. The chiplet pads 215 can include signal chiplet pads 215-S, ground chiplet pads 215-G, and power chiplet pads 215-P. The redistribution conductive layer 218B may include a signal redistribution conductive layer 218B-S connected to the signal chiplet pad 215-S, a ground redistribution conductive layer 218-G connected to the ground chiplet pad 215-G, and a power redistribution conductive layer 218B-P connected to the power chiplet pad 215-P. The signal redistribution pads 218BP-S may be disposed at ends of the signal redistribution conductive layers 218B-S, the ground redistribution pads 218BP-G may be disposed at ends of the ground redistribution conductive layers 218B-G, and the power redistribution pads 218BP-P may be disposed at ends of the power redistribution conductive layers 218B-P. The ground redistribution conductive layers 218B-G may be connected to the ground chiplet pads 215-G and the first electrode 262 of the capacitor 260 through openings of the first redistribution insulating layer 218A. The power redistribution conductive layer 218B-P may be connected to the power chiplet pad 215-P and the second electrode 264 of the capacitor 260 through the opening of the first redistribution insulating layer 218A.

In addition, the sub semiconductor package 210 may further include sub vias 270 respectively connected to the first and second electrodes 262 and 264 of the capacitor 260.

The upper surfaces of the sub-vias 270 may be connected to the lower surfaces of the first and second electrodes 262 and 264, respectively. The sub-vias 270 may extend from the lower surfaces of the first and second electrodes 262 and 264 to the lower surface of the sub-mold layer 216 by passing through the sub-mold layer 216. The lower surface of the sub-via 270 may be exposed by being located at the same height as the lower surface of the sub-molding layer 216.

The sub semiconductor package 210 may be electrically connected to the substrate through an interconnector 280 connected to the exposed lower surface of the sub via 270 (see 200 in fig. 8). The interconnectors 280 connected to the sub-vias 270 will be referred to as second sub-package interconnectors 280 to distinguish them from first sub-package interconnectors described later. The second sub-package interconnector 280 may include conductors having various three-dimensional shapes such as balls and pillars, instead of conductors having a two-dimensional shape such as wires. For example, the second sub-package interconnector 280 may include solder balls or metal bumps. Although not shown, an additional insulating layer may be disposed between the lower surface of the sub-molding layer 216 and the second sub-package interconnector 280. Openings may be formed in the additional insulating layer to expose the sub-vias 270 to connect to the second sub-package interconnector 280.

Hereinafter, the electrical connection between the sub semiconductor package 210 and the substrate 200 will be described in more detail together with fig. 8. For reference, fig. 8 is shown based on a cross-section corresponding to line a1-a 1' of fig. 1, such that the capacitor 260, and the sub-vias 270 and second sub-package interconnects 280 connected thereto, are not actually visible. However, for convenience of description, one capacitor 260, and a sub-via 270 and a second sub-package interconnector 280 connected thereto are illustrated.

Referring to fig. 8 together with fig. 9 to 11, the sub semiconductor package 210 may be electrically connected to the substrate 200 through the first and second sub package interconnectors 217 and 280.

The first sub-package interconnect 217 may be substantially the same as the sub-package interconnect 117 of the above-described embodiment. That is, the first sub-package interconnector 217 may connect the redistribution pad 218BP and the substrate 200 to each other, thereby providing an electrical connection between the sub-semiconductor chip 214 and the substrate 200. The first sub-package interconnector 217 may be a bonding wire.

On the other hand, the second sub-package interconnector 280 may be connected to the redistribution conductive layer 218B through each of the sub-via 270 and the first and second electrodes 262 and 264 of the capacitor 260. Specifically, the second sub-package interconnector 280 may be connected to a point in the redistribution conductive layer 218B other than the redistribution pad 218 BP. Accordingly, electrical connection between the sub-semiconductor chip 214 and the substrate 200 may be provided.

Since the second sub-package interconnector 280 is interposed between the sub-semiconductor package 210 and the substrate 200, the sub-molding layer 216 may be spaced apart from the substrate 200 by a predetermined distance while not being attached to the substrate 200, unlike the sub-molding layer 116 of the above-described embodiment. The distance may correspond to a height of the second sub-package interconnect 280. The second sub-package interconnector 280 may provide electrical connection between the sub-semiconductor package 210 and the substrate 200, and may also function to support the sub-semiconductor package 210. The plurality of second sub-package interconnectors 280 may be disposed to overlap each of the first and second electrodes 262 and 264 of the capacitor 260. Since the first and second electrodes 262 and 264 of the capacitor 260 are disposed along the periphery of the sub-semiconductor chip 214, the second sub-package interconnector 280 may sufficiently support the sub-semiconductor package 210. In addition, one or more dummy second sub-package interconnectors 281 not connected to the sub-via 270 may be additionally disposed over the lower surface of the sub-molding layer 216. The dummy second sub-package interconnector 281 may prevent the sub-semiconductor packages 210 from being inclined in a direction, or may endure pressure generated when the first chip stack 220 and the second chip stack 230 are mounted over the sub-semiconductor packages 210.

Fig. 8 may further include a first chip stack 220 and a second chip stack 230 disposed over the sub semiconductor package 210. The first chip stack 220 may include a plurality of first main semiconductor chips 224 and a first adhesive layer 222 for attaching each first main semiconductor chip 224 to an underlying structure thereof. The first main semiconductor chips 224 may be offset-stacked in a first offset direction such that the first chip pad 225 disposed on the upper surface of each first main semiconductor chip 224 is exposed. The first chip stack 220 may be electrically connected to the substrate 200 through a first interconnector 227. The second chip laminate 230 includes a plurality of second main semiconductor chips 234 and a second adhesive layer 232 for attaching each of the second main semiconductor chips 234 to an underlying structure thereof. The second main semiconductor chips 234 may be offset-stacked in a second offset direction such that the second chip pads 235 disposed on the upper surface of each of the second main semiconductor chips 234 are exposed. The second chip laminate 230 may be electrically connected to the substrate 200 through a second interconnector 237. The first chip stack 220 and the second chip stack 230 may be covered with a molding layer 250. The external connection terminals 240 may be disposed over the lower surface of the substrate 200.

According to the semiconductor package of the present embodiment, all the advantages of the semiconductor package of the above embodiments can be obtained.

Further, as in the present embodiment, when the sub-via 270 connected to each of the first electrode 262 and the second electrode 264 of the capacitor 260 is provided in the sub-semiconductor package 210, and the second sub-package interconnector 280 connecting the sub-semiconductor package 210 and the substrate 200 is provided, a direct current path between the sub-semiconductor package 210 and the substrate 200 may be shortened, thereby reducing the impedance of the power supply path. Further, a plurality of direct current paths may be formed, so that the inductance of the power supply path may be reduced. As a result, power supply between the sub semiconductor package 210 and the substrate 200 may be easier. This will be further described with reference to fig. 12A and 12B.

Fig. 12A is a diagram for explaining an example of an effect of a semiconductor package according to another embodiment of the present disclosure; and fig. 12B is a diagram for explaining the effect of the semiconductor package according to the comparative example. Unlike the present embodiment, fig. 12B illustrates a case where the capacitor and the sub via hole are not present.

Referring to fig. 12A, a relatively long direct current path (see dotted arrow r) may be formed through the redistribution conductive layer 218B, the first sub-package interconnect 217, and the substrate 200. Further, a relatively short direct current path (see dotted arrow @) may be formed by a portion of the redistribution conductive layer 218B, the capacitor 260, the sub-via 270, the second sub-package interconnect 280, and the substrate 200.

That is, a short direct current path can be obtained as shown by the broken line arrow (c), and a plurality of direct current paths can be formed as shown by the broken line arrows (r) and (c).

On the other hand, referring to fig. 12B, in the comparative example, only a relatively long direct current path (see a dotted arrow) passing through the redistribution conductive layer 218B ', the first sub-package interconnector 217 ', and the substrate 200 ' may be formed.

As a result, according to the present embodiment, as shown in fig. 12A, a short direct current path and a plurality of direct current paths can be formed, so that the impedance and inductance of the power supply path can be reduced. Therefore, the power supply can be easily performed.

Fig. 13 is a sectional view illustrating a semiconductor package according to another embodiment of the present disclosure, fig. 14 is a plan view illustrating a sub-semiconductor package of the semiconductor package according to another embodiment of the present disclosure, fig. 15 is a sectional view taken along a line a6-a6 'of fig. 14, and fig. 16 is a sectional view taken along a line a7-a 7' of fig. 14. Hereinafter, differences from the above-described embodiments will be mainly described.

First, referring to fig. 14 to 16, similar to the above-described embodiment, the sub-semiconductor package 310 of the present embodiment may include a sub-semiconductor chip 314, a sub-molding layer 316 surrounding at least a side surface of the sub-semiconductor chip 314, a redistribution structure including a first redistribution insulating layer 318A, a redistribution conductive layer 318B, and a second redistribution insulating layer 318C and formed over upper surfaces of the sub-semiconductor chip 314 and the sub-molding layer 316, and a capacitor 360 disposed in the sub-molding layer 316 and including a first electrode 362, a second electrode 364, and a body portion (not shown) therebetween. The sub-chip pad 315 may be disposed on the upper surface of the sub-semiconductor chip 314. Sub-chip pads 315 may include signal sub-chip pads 315-S, ground sub-chip pads 315-G, and power sub-chip pads 315-P. Redistribution conductive layer 318B may include signal redistribution conductive layer 318B-S connected to signal chiplet pad 315-S, ground redistribution conductive layer 318B-G connected to ground chiplet pad 315-G, and power redistribution conductive layer 318B-P connected to power chiplet pad 315-P. Signal redistribution pads 318BP-S may be disposed at ends of signal redistribution conductive layers 318B-S, ground redistribution pads 318BP-G may be disposed at ends of ground redistribution conductive layers 318B-G, and power redistribution pads 318BP-P may be disposed at ends of power redistribution conductive layers 318B-P. The ground redistribution conductive layers 318B-G may be connected to the ground sub-chip pads 315-G and the first electrode 362 of the capacitor 360 through the opening of the first redistribution insulating layer 318A. The power redistribution conductive layer 318B-P may be connected to the power chiplet pad 315-P and the second electrode 364 of the capacitor 360 through the opening of the first redistribution insulating layer 318A.

In addition, the sub-semiconductor package 310 may further include sub-vias 370 connected to the ground redistribution conductive layers 318B-G and the power redistribution conductive layers 318B-P, respectively.

The sub-via 370 may be formed to be spaced apart from each of the first and second electrodes 362 and 364 of the capacitor 360. However, as described later, the sub-via 370 may also be disposed closer to the sub-chip pad 315 than the gravity distribution pad 318BP to shorten the direct current path. In addition, sub-vias 370 may be located between the first electrode 362 and the ground redistribution pads 318BP-G and between the second electrode 364 and the power redistribution pads 318 BP-P.

The sub-via 370 may be formed to penetrate the sub-mold layer 316 and extend from an upper surface to a lower surface of the sub-mold layer 316. That is, the upper surface of the sub-via hole 370 may be exposed by being located at substantially the same height as the upper surface of the sub-mold layer 316, and the lower surface of the sub-via hole 370 may be exposed by being located at substantially the same height as the lower surface of the sub-mold layer 316. Each of ground redistribution conductive layers 318B-G and power redistribution conductive layers 318B-P may be connected to an upper surface of sub-via 370 through an opening in first redistribution insulating layer 318A.

The sub-semiconductor package 310 may be electrically connected to the substrate through the second sub-package interconnector 380 connected to the lower surface of the sub-via 370 (see 300 of fig. 13). The second sub-package interconnector 380 may include conductors having various three-dimensional shapes such as balls and pillars instead of two-dimensional shapes such as wires. For example, the second sub-package interconnector 380 may include solder balls or metal bumps. Although not shown, an additional insulating layer may be disposed between the lower surface of the sub-molding layer 316 and the second sub-package interconnector 380. An opening may be formed in the additional insulating layer to expose the sub-via 370 to connect to the second sub-package interconnector 380.

Hereinafter, the electrical connection between the sub semiconductor package 310 and the substrate 300 will be described in more detail together with fig. 13. For reference, fig. 13 is shown based on a cross-section corresponding to line a1-a 1' of fig. 1, such that the capacitor 360, sub-via 370, and second sub-package interconnect 380 are not actually visible. However, for convenience of description, one capacitor 360 is illustrated, and the sub-via 370 and the second sub-package interconnector 380 near the one capacitor 360.

Referring to fig. 13 together with fig. 14 to 16, the sub semiconductor package 310 may be electrically connected to the substrate 300 through the first and second sub package interconnectors 317 and 380.

The first sub-package interconnect 317 may be substantially the same as the first sub-package interconnect 217 of the above-described embodiment. That is, the first sub-package interconnector 317 may provide electrical connection between the sub-semiconductor chip 314 and the substrate 300 by connecting the redistribution pad 318BP and the substrate 300 to each other. The first sub-package interconnector 317 may be a bonding wire.

On the other hand, the second sub-package interconnector 380 may be connected to the redistribution conductive layer 318B through the sub-via 370. Specifically, the second sub-package interconnector 380 may be connected to a point in the redistribution conductive layer 318B other than the redistribution pad 318 BP. Accordingly, electrical connection between the sub semiconductor chip 314 and the substrate 300 may be provided.

Since the second sub-package interconnector 380 is interposed between the sub-semiconductor package 310 and the substrate 300, the sub-molding layer 316 may not be attached to the substrate 300 and may be spaced apart from the substrate 300 by a predetermined distance. The distance may correspond to the height of the second sub-package interconnect 380. The second sub-package interconnector 380 provides electrical connection between the sub-semiconductor package 310 and the substrate 300, and may also support the sub-semiconductor package 310. The plurality of second sub-package interconnectors 380 may be disposed adjacent to the first and second electrodes 362 and 364 of the capacitor 360, respectively. That is, since the second sub-package interconnector 380 is disposed along the periphery of the sub-semiconductor chip 314, the second sub-package interconnector 380 may sufficiently support the sub-semiconductor package 310. A dummy second sub-package interconnector 381 not connected to the sub-via 370 may be additionally disposed over the lower surface of the sub-molding layer 316. The dummy second sub-package interconnector 381 may prevent the sub-semiconductor package 310 from being inclined in a direction or may endure a pressure generated when the first chip stack 320 and the second chip stack 330 are mounted over the sub-semiconductor package 310.

Fig. 13 may further include a first chip stack 320 and a second chip stack 330 disposed over the sub semiconductor package 310. The first chip stack 320 may include a plurality of first main semiconductor chips 324 and a first adhesive layer 322 for attaching the first main semiconductor chips 324 to an underlying structure thereof. . The first main semiconductor chips 324 may be offset-stacked in a first offset direction such that the first chip pad 325 disposed on the upper surface of each of the first main semiconductor chips 324 is exposed. First chip stack 320 may be electrically connected to substrate 300 through first interconnector 327. The second chip laminate 330 includes a plurality of second main semiconductor chips 334 and a second adhesive layer 332 for attaching each of the second main semiconductor chips 334 to an underlying structure thereof. The second main semiconductor chips 334 may be offset-stacked in a second offset direction such that the second chip pads 335 disposed on the upper surface of each of the second main semiconductor chips 334 are exposed. The second chip laminate 330 may be electrically connected to the substrate 300 through a second interconnector 337. First chip-stack 320 and second chip-stack 330 may be covered with a molding layer 350. The external connection terminals 340 may be disposed over the lower surface of the substrate 300.

According to the semiconductor package of the present embodiment, all the advantages of the semiconductor package of the above embodiments can be obtained.

Specifically, when the sub-via 370 connected to each of the ground and power redistribution conductive layers 318B-G and 318B-P and the second sub-package interconnector 380 connecting the sub-via 370 and the substrate 300 are provided in the sub-semiconductor package 310, a direct current path between the sub-semiconductor package 310 and the substrate 300 may be shortened, and thus a power supply path of a power source may be reduced, as compared to a case where the sub-via does not exist in the sub-semiconductor package 310. Further, a plurality of direct current paths can be formed, so that the inductance of the power supply path can be reduced. As a result, power can be supplied between the sub-semiconductor package 310 and the substrate 300 more easily. This will be further described with reference to fig. 17A and 17B.

Fig. 17A is a diagram for explaining an example of an effect of a semiconductor package according to another embodiment of the present disclosure, and fig. 17B is a diagram for explaining an effect of a semiconductor package of a comparative example. Unlike the present embodiment, fig. 17B illustrates a case where there is no sub-via in the sub-semiconductor package 310.

Referring to fig. 17A, a relatively long direct current path (see dotted arrow r) may be formed through the redistribution conductive layer 318B, the first sub-package interconnect 317, and the substrate 300. Further, a relatively short dc path (see dashed arrow) may be formed through a portion of the redistribution conductive layer 318B, the sub-via 370, the second sub-package interconnect 380, and the substrate 300.

That is, a short direct current path can be obtained as shown by the broken line arrow (c), and further, a plurality of direct current paths can be formed as shown by the broken line arrows (r) and (c).

On the other hand, referring to fig. 17B, in the comparative example, only a relatively long direct current path (see a dotted arrow) is formed through the redistribution conductive layer 318B ', the first sub-package interconnector 317 ', and the substrate 300 '.

As a result, according to the present embodiment, as shown in fig. 17A, a short direct current path and a plurality of direct current paths can be formed, so that the impedance and inductance of the power supply path can be reduced. Therefore, the power supply can be easily performed.

With the embodiments of the present disclosure, a high-capacity and multifunctional semiconductor package may be realized by forming a chip stack including one or more main semiconductor chips over a sub semiconductor package. Further, power supply in the semiconductor package can be assisted by providing a capacitor in the sub-semiconductor package.

Fig. 18 shows a block diagram of an exemplary electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of a semiconductor package according to the described embodiments.

The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or stored data is stored in response to a read/write request from the host 7830.

Fig. 19 shows a block diagram illustrating an electronic system 8710, the electronic system 8710 including at least one of the semiconductor packages according to the described embodiments. The electronic system 8710 may include a controller 8711, an input/output device 8712, and a memory 8713. The controller 8711, the input/output device 8712, and the memory 8713 may be coupled to each other by a bus 8715 that provides a data movement path.

In an embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to embodiments of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 can store commands and/or data and the like to be executed by the controller 8711.

The memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, the flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a Solid State Disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

The electronic system 8710 may also include an interface 8714 configured to send and receive data to and from a communication network. The interface 8714 may be of a wired or wireless type. For example, interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a Personal Digital Assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If electronic system 8710 represents equipment capable of performing wireless communication, electronic system 8710 may be used in a communication system using CDMA (code division multiple access), GSM (global system for mobile communication), NADC (north american digital cellular), E-TDMA (enhanced time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband internet) technologies.

While various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined in the following claims.

Cross Reference to Related Applications

This application claims priority from korean patent application No.10-2020-0061540, filed on 22/5/2020, hereby incorporated by reference in its entirety.